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1. 发明申请

US20190188596A1 SUPERCONDUCTING SYSTEM ARCHITECTURE FOR HIGH-PERFORMANCE ENERGY-EFFICIENT CRYOGENIC COMPUTING 审中-公开
公开(公告)号：US20190188596A1
公开(公告)日：2019-06-20
申请号：US15774503
申请日：2016-11-10
申请人： Engin Ipek , Ben Feinberg , Shibo Wang , Mahdi N. Bojnordi , Ravi Patel , Eby G. Friedman
发明人： Engin Ipek , Ben Feinberg , Shibo Wang , Mahdi N. Bojnordi , Ravi Patel , Eby G. Friedman
IPC分类号： G06N10/00 , G06F7/38 , G06F9/30 , H03K19/195 , G11C11/44 , G11C11/16 , G11C19/32
CPC分类号： G06N10/00 , G06F1/16 , G06F7/381 , G06F9/3004 , G06F9/30105 , G06F9/3016 , G11C11/161 , G11C11/1673 , G11C11/1675 , G11C11/44 , G11C19/32 , H01L27/18 , H01L27/222 , H01L39/223 , H01L43/02 , H03K19/195
摘要： An energy efficient rapid single flux quantum (ERSFQ) logic register wheel includes a circular shift register having a plurality of destructive read out (DRO) cells. Each entry of the circular shift register includes a data block, a tag, and a valid bit. A compare and control logic is coupled to the circular shift register to compare a source specifier or a destination register specifier against a register tag stored in the wheel following each cycle of the register wheel. At least one or more read ports and at least one or more write ports are coupled to the circular shift register to write to or to read from a different entry each in the register wheel following each cycle of the register wheel. A RSFQ clearable FIFO with flushing and a crosspoint memory topology for integrating MRAM devices with ERSFQ circuits are also described.

2. 发明申请

US20190007051A1 Parametrically Activated Quantum Logic Gates 审中-公开
公开(公告)号：US20190007051A1
公开(公告)日：2019-01-03
申请号：US16012551
申请日：2018-06-19
申请人： Rigetti & Co, Inc.
发明人： Eyob A. Sete , Nicolas Didier , Marcus Palmer da Silva , Chad Tyler Rigetti , Matthew J. Reagor , Shane Arthur Caldwell , Nikolas Anton Tezak , Colm Andrew Ryan , Sabrina Sae Byul Hong , Prasahnt Sivarajah , Alexander Papageorge , Deanna Margo Abrams
IPC分类号： H03K19/195 , G06N99/00
CPC分类号： H03K19/195 , G06N10/00
摘要： In a general aspect, a quantum logic gate is performed in a quantum computing system. In some cases, a pair of qubits are defined in a quantum processor; the pair of qubits can include a first qubit defined by a first qubit device in the quantum processor and a second qubit defined by a tunable qubit device in the quantum processor. A quantum logic gate can be applied to the pair of qubits by communicating a control signal to a control line coupled to the tunable qubit device. The control signal can be configured to modulate a transition frequency of the tunable qubit device at a modulation frequency, and the modulation frequency can be determined based on a transition frequency of the first qubit device.

3. 发明申请

US20180240034A1 SYSTEMS AND METHODS FOR CREATING AND USING HIGHER DEGREE INTERACTIONS BETWEEN QUANTUM DEVICES 审中-公开
公开(公告)号：US20180240034A1
公开(公告)日：2018-08-23
申请号：US15752102
申请日：2016-08-11
申请人： D-Wave Systems Inc.
发明人： Richard G. Harris
IPC分类号： G06N99/00 , H01F38/14 , B82Y10/00 , H01L27/18 , H03K19/195
CPC分类号： G06N10/00 , B82Y10/00 , H01F38/14 , H01F2038/143 , H01L27/18 , H03K19/195
摘要： A higher degree of interactions between qubits is realizable. This disclosure generally relates to devices, and architectures for quantum instruments comprising quantum devices and techniques for operating the same. Systems and processors for creating and using higher degree interactions between qubits may be found herein. Higher order interactions include interactions among three or more qubits. Methods for creating and using higher degree interactions among three or more qubits on a quantum processor may be found herein.

4. 发明授权

US09905900B2 Superconductor circuits with active termination 有权
公开(公告)号：US09905900B2
公开(公告)日：2018-02-27
申请号：US14702044
申请日：2015-05-01
申请人： Quentin P. Herr , Aaron A. Pesetski , Pavel Borodulin
发明人： Quentin P. Herr , Aaron A. Pesetski , Pavel Borodulin
IPC分类号： H03K19/195 , H01P3/06 , H03K3/38
CPC分类号： H01P3/06 , H03K3/38 , H03K19/195
摘要： A microwave circuit is provided that comprises a plurality of transmission lines each configured to receive and propagate a respective waveform signal of a plurality of waveform signals, and a combiner that receives and combines the plurality of waveform signals from outputs of the plurality of transmission lines into a combined output waveform signal that is output terminated by an output termination resistor. The microwave circuit further comprises a compensation signal generator that generates a compensation signal to mitigate reflections associated with the transmission of signals through the microwave circuit.

5. 发明授权

US09887700B2 Phase-mode based superconducting logic 有权
公开(公告)号：US09887700B2
公开(公告)日：2018-02-06
申请号：US15361411
申请日：2016-11-26
申请人： Microsoft Technology Licensing, LLC
发明人： Douglas Carmean , Alexander Braun , Anna Y. Herr , Quentin P. Herr
IPC分类号： H03K19/195 , H03K3/38 , H03K19/00 , H03K3/037 , H03K19/20
CPC分类号： H03K19/195 , H03K3/037 , H03K3/38 , H03K19/0008 , H03K19/20
摘要： A device including Josephson junctions, and a terminal for receiving a sinusoidal clock signal for providing power to the Josephson junctions, is provided. The device further includes a terminal for receiving an input signal, a clock terminal for receiving a return-to-zero clock signal, and at least one latch. The device also includes at least one logic gate including at least a subset of the Josephson junctions, for processing the input signal and the return-to-zero clock signal to generate a first signal for the at least one latch. Additionally, the device includes at least one phase-mode logic inverter for processing the return-to-zero clock signal to generate a second signal for the at least one latch. The device also includes an output terminal for providing an output of the at least one latch by processing the first signal and the second signal.

6. 发明授权

US09864954B1 Optimized testing of a partially symmetric quantum-logic circuit 有权
公开(公告)号：US09864954B1
公开(公告)日：2018-01-09
申请号：US15434867
申请日：2017-02-16
申请人： International Business Machines Corporation
发明人： Pawel Jasionowski
IPC分类号： H03K19/195 , G06N99/00
CPC分类号： G06N99/002 , H03K19/195
摘要： A method and associated systems for using wreath products and invariance groups to test a partially symmetric quantum-logic circuits. A test system receives information that describes the architecture of a quantum-logic circuit to be tested. The system uses this information to hierarchically organize the circuit's inputs into non-overlapping blocks. The system creates set of groups associated with the blocks, and then generates an invariance group that contains one or more invariant permutations of the inputs by computing a wreath product of the set of groups. These invariant permutations identify a minimal number of tests required to verify the circuit for all possible input vectors. The system then directs a test apparatus to perform the resulting optimized test sequence upon the circuit.

7. 发明授权

US09853645B1 Low-power biasing networks for superconducting integrated circuits 有权
公开(公告)号：US09853645B1
公开(公告)日：2017-12-26
申请号：US15290583
申请日：2016-10-11
申请人： Hypres, Inc.
发明人： Oleg A. Mukhanov , Alexander F. Kirichenko , Dimitri Kirichenko
IPC分类号： H03K19/195
CPC分类号： H03K19/195 , H01B12/02 , H01B12/16 , H01L27/18 , H03K3/38 , Y10T29/49124
摘要： A superconducting integrated circuit, comprising a plurality of superconducting circuit elements, each having a variation in operating voltage over time; a common power line; and a plurality of bias circuits, each connected to the common power line, and to a respective superconducting circuit element, wherein each respective bias circuit is superconducting during at least one time portion of the operation of a respective superconducting circuit element, and is configured to supply the variation in operating voltage over time to the respective superconducting circuit element.

8. 发明授权

US09692423B2 System and method for circuit quantum electrodynamics measurement 有权
公开(公告)号：US09692423B2
公开(公告)日：2017-06-27
申请号：US14584659
申请日：2014-12-29
申请人： Robert Francis McDermott, III , Britton Louis Thomas Plourde , Maxim George Vavilov , Frank Karsten Wilhelm-Mauch , Luke Colin Gene Govia , Emily Joy Pritchett
发明人： Robert Francis McDermott, III , Britton Louis Thomas Plourde , Maxim George Vavilov , Frank Karsten Wilhelm-Mauch , Luke Colin Gene Govia , Emily Joy Pritchett
IPC分类号： H03K19/19 , H03K19/195 , B82Y10/00 , G06N99/00
CPC分类号： H03K19/1954 , B82Y10/00 , G06N99/002 , H03K19/19 , H03K19/195 , H03K19/1958
摘要： A system for quantum computation and a readout method using the same are provided. In some aspects, the system includes at least one qubit circuit coupled to a resonant cavity, wherein each of the at least one qubit circuit is described by multiple quantum states, and a controller configured to provide microwave irradiation to the resonant cavity such that a quantum state information of the at least one qubit circuit is transferred to a resonant cavity occupation. The system also includes a readout circuit, coupled to the resonant cavity, configured to receive signals corresponding to the resonant cavity occupation, and generate an output indicative of the quantum states of the at least one qubit circuit. Optionally, the system further includes at least one single flux quantum (“SFQ”) circuit coupled to the readout circuit and configured to receive the output therefrom.

9. 发明申请

US20170091650A1 SYSTEMS AND DEVICES FOR QUANTUM PROCESSOR ARCHITECTURES 审中-公开
公开(公告)号：US20170091650A1
公开(公告)日：2017-03-30
申请号：US15373910
申请日：2016-12-09
申请人： D-Wave Systems Inc.
发明人： Andrew Douglas King
IPC分类号： G06N99/00 , G06F15/76
CPC分类号： G06N99/002 , G06F15/76 , H03K19/195
摘要： Quantum processor architectures employ unit cells tiled over an area. A unit cell may include first and second sets of qubits where each qubit in the first set crosses at least one qubit in the second set. Angular deviations between qubits in one set may allow qubits in the same set to cross one another. Each unit cell is positioned proximally adjacent at least one other unit cell. Communicatively coupling between qubits is realized through respective intra-cell and inter-cell coupling devices.

10. 发明授权

US09595969B2 Reciprocal quantum logic comparator for qubit readout 有权
标题翻译：用于量子位读数的互补量子逻辑比较器
公开(公告)号：US09595969B2
公开(公告)日：2017-03-14
申请号：US15008022
申请日：2016-01-27
申请人： Donald L. Miller , Ofer Naaman
发明人： Donald L. Miller , Ofer Naaman
IPC分类号： G06N99/00 , H03K19/195 , H01L39/22 , H03K3/38 , G11C11/44
CPC分类号： H03K19/195 , G06N99/002 , G11C11/44 , H01L39/223 , H03K3/38
摘要： One aspect of the present invention includes a reciprocal quantum logic (RQL) readout system. The system includes an input stage on which a read pulse is provided and an output stage configured to propagate an output pulse. The system also includes an RQL comparator comprising a first Josephson junction and a second Josephson junction that are coupled to a qubit. A bias current switches between a first Josephson junction in a first quantum state of the qubit and a second Josephson junction in a second quantum state of the qubit. The first Josephson junction triggers to provide the output pulse on the output stage in the first quantum state in response to the read pulse and the second Josephson junction triggers to provide no output pulse on the output stage in the second quantum state in response to the read pulse.
摘要翻译：本发明的一个方面包括相互量子逻辑（RQL）读出系统。该系统包括其上提供读取脉冲的输入级和被配置为传播输出脉冲的输出级。该系统还包括RQL比较器，其包括耦合到量子位的第一约瑟夫逊结和第二约瑟夫逊结。偏置电流在量子位的第一量子态的第一约瑟夫逊结和量子位的第二量子态之间切换第二约瑟夫逊结。第一约瑟夫逊结触发器响应于读取脉冲在第一量子状态中在输出级上提供输出脉冲，并且第二约瑟夫逊结触发在第二量子态中在输出级上不响应读取而不提供输出脉冲脉冲。

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