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1. 发明申请

US20210083667A1 SEMICONDUCTOR LOGIC ELEMENT AND A LOGIC CIRCUITRY 有权
公开(公告)号：US20210083667A1
公开(公告)日：2021-03-18
申请号：US17247021
申请日：2020-11-24
申请人： HYPERION SEMICONDUCTORS OY
发明人： Artto AUROLA
IPC分类号： H03K19/0185 , H01L27/02 , H01L27/092 , H01L27/098 , H01L29/808 , H01L27/12 , H01L29/06 , H03K19/00 , H03K19/003 , H03K19/094 , H03K19/0952 , H03K19/20 , H01L29/78 , H01L29/10 , H01L29/36
摘要： Disclosed is a semiconductor logic element including a field effect transistor of the first conductivity type and a field effect transistor of the second conductivity type. A gate of the first FET is an input of the semiconductor logic element, a drain of the second FET is referred to as the output of the semiconductor logic element and a source of the second FET is the source of the semiconductor logic element. By applying applicable potentials to the terminals of the field effect transistors it is possible to influence the state of the output of the logic element. Also disclosed are different kinds of logic circuitries including the described logic element.

2. 发明申请

US20200153437A1 GATE DRIVER WITH SERIAL COMMUNICATION 审中-公开
公开(公告)号：US20200153437A1
公开(公告)日：2020-05-14
申请号：US16741898
申请日：2020-01-14
申请人： Texas Instruments Incorporated
发明人： Xiong Li , Toru Tanaka
IPC分类号： H03K19/0952 , H02M7/5387 , H03K17/06 , H03K5/19 , H03K17/22 , H03K19/017 , H02M7/537
摘要： A gate driver includes a drive signal input terminal, a drive signal output terminal, a gate drive circuit, and a serial communication interface. The drive signal input terminal is configured to receive a gate drive signal. The gate drive circuit is coupled to the drive signal input terminal and the drive signal output terminal. The gate drive circuit is configured to provide the gate drive signal to the drive signal output terminal. The serial communication interface is coupled to the drive signal input terminal.

3. 发明授权

US10587268B2 Gate driver with serial communication 有权
公开(公告)号：US10587268B2
公开(公告)日：2020-03-10
申请号：US16388353
申请日：2019-04-18
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Xiong Li , Toru Tanaka
IPC分类号： H03K19/0952 , H02M7/537 , H03K19/017 , H03K17/22 , H03K5/19 , H03K17/06 , H02M7/5387
摘要： A gate driver includes a drive signal input terminal, a drive signal output terminal, a gate drive circuit, and a serial communication interface. The drive signal input terminal is configured to receive a gate drive signal. The gate drive circuit is coupled to the drive signal input terminal and the drive signal output terminal. The gate drive circuit is configured to provide the gate drive signal to the drive signal output terminal. The serial communication interface is coupled to the drive signal input terminal.

4. 发明授权

US10389360B2 Depletion mode buried channel conductor insulator semiconductor field effect transistor 有权
公开(公告)号：US10389360B2
公开(公告)日：2019-08-20
申请号：US16173271
申请日：2018-10-29
申请人： HYPERION SEMICONDUCTORS OY
发明人： Artto Aurola
IPC分类号： H01L29/36 , H03K19/0185 , H01L29/10 , H01L29/78 , H03K19/20 , H03K19/0952 , H03K19/094 , H03K19/003 , H03K19/00 , H01L29/06 , H01L27/12 , H01L29/808 , H01L27/098 , H01L27/092 , H01L27/02 , H01L27/06
摘要： Disclosed is a semiconductor logic element including a field effect transistor of the first conductivity type and a field effect transistor of the second conductivity type. A gate of the first FET is an input of the semiconductor logic element, a drain of the second FET is referred to as the output of the semiconductor logic element and a source of the second FET is the source of the semiconductor logic element. By applying applicable potentials to the terminals of the field effect transistors it is possible to influence the state of the output of the logic element. Also disclosed are different kinds of logic circuitries including the described logic element.

5. 发明授权

US5978826A Adder with even/odd 1-bit adder cells 失效
标题翻译：加法器具有偶数/奇数1位加法器单元
公开(公告)号：US5978826A
公开(公告)日：1999-11-02
申请号：US755846
申请日：1996-11-26
申请人： Ravi Kumar Kolagotla
发明人： Ravi Kumar Kolagotla
IPC分类号： G06F7/50 , G06F7/503 , H03K19/00 , H03K19/094 , H03K19/0952
CPC分类号： G06F7/503 , G06F2207/3876
摘要： An integrated circuit including an adder that is a series of one-bit cascaded adder cells. The circuits that implement the adder cells are not all alike. The adder cells are of two types: an even adder cell and an odd adder cell. The even adder cells receive all inputs as noninverted inputs, provide as outputs a noninverted sum bit output and the inverse of the carry-out bit. The odd adder cells receive as inputs the inverse of the carry-in bit, all other inputs are noninverted, and provides as outputs a noninverted sum bit and a noninverted carry-out bit.
摘要翻译：一种集成电路，包括作为一系列一位级联加法器单元的加法器。实现加法器单元的电路不是一样。加法器单元有两种类型：偶数加法器单元和奇数加法器单元。偶数加法器单元接收所有输入作为非反相输入，提供非反相和位输出和进位位反相。奇数加法器单元接收进位位的反相作为输入，所有其他输入均不反相，并将输出提供为非反相和位和非反相进位位。

6. 发明授权

US5917360A Differential current-switch circuit, D/A conversion circuit and method of transient response reduction 失效
标题翻译：差分电流开关电路，D / A转换电路和瞬态响应降低方法
公开(公告)号：US5917360A
公开(公告)日：1999-06-29
申请号：US745209
申请日：1996-11-08
申请人： Nobuyuki Yasutake
发明人： Nobuyuki Yasutake
IPC分类号： H03M1/74 , H03K17/041 , H03K17/60 , H03K17/687 , H03K19/018 , H03K19/0952 , H03M5/04 , H03K17/16
CPC分类号： H03M5/04 , H03K17/04106 , H03K17/04113
摘要： When a pair of emitter-coupled transistor switches 22A and 22B are switched over, the D flipflop 26A shifts the base potential of a transistor buffer circuit 24 to reduce a potential fluctuation at a constant current source 21, reducing a current oscillation caused by the transient response of the constant current source 21 in which feedback control is performed by a comparator 214. In another construction, a potential oscillation waveform of the connected emitter node is stored in a RAM and the waveform read out of the RAM is added to the base of the transistor buffer circuit to reduce the current oscillation.
摘要翻译：当一对发射极耦合晶体管开关22A和22B被切换时，D触发器26A移动晶体管缓冲电路24的基极电位以减小恒定电流源21处的电位波动，从而减少由瞬变引起的电流振荡反馈控制由比较器214执行的恒流源21的响应。在另一种结构中，连接的发射极节点的电位振荡波形被存储在RAM中，并且从RAM中读出的波形被添加到晶体管缓冲电路减少电流振荡。

7. 发明授权

US5892382A Current mode logic circuit, source follower circuit and flip flop circuit 失效
标题翻译：电流模式逻辑电路，源极跟随器电路和触发器电路
公开(公告)号：US5892382A
公开(公告)日：1999-04-06
申请号：US904940
申请日：1997-08-01
申请人： Kimio Ueda , Yuuichi Hirano , Yoshiki Wada
发明人： Kimio Ueda , Yuuichi Hirano , Yoshiki Wada
IPC分类号： H01L21/8234 , H01L27/088 , H03K3/356 , H03K3/3562 , H03K19/094 , H03K19/0944 , H03K19/0952 , H03K3/289
CPC分类号： H03K3/3562 , H03K19/09432 , H03K3/35613 , H03K2217/0018
摘要： A current mode logic circuit has a first and second NMOS transistors N1 and N2, an input terminal IN connected to both gates of the first and second NMOS transistors N1 and N2 to input data, a reference voltage input terminal REF, an output terminal OUT connected to a drain of the first NMOS transistor N1, and a current power source I connected both sources of the first and second NMOS transistors N1 and N2. Body terminals of the first and second NMOS transistors N1and N2 are connected to the input terminal IN and the reference terminal REF, respectively so that the body voltage of each of the first and second NMOS transistors N1 and N2 is controlled.
摘要翻译：电流模式逻辑电路具有第一和第二NMOS晶体管N1和N2，连接到第一和第二NMOS晶体管N1和N2的两个栅极的输入端子IN以输入数据，参考电压输入端子REF，连接的输出端子OUT 连接到第一NMOS晶体管N1的漏极，以及连接第一和第二NMOS晶体管N1和N2的两个源极的电流电源I。第一和第二NMOS晶体管N1和N2的主体端子分别连接到输入端子IN和参考端子REF，以便控制第一和第二NMOS晶体管N1和N2中的每一个的体电压。

8. 发明授权

US5886578A Differential amplifier including bias circuit with bias resistor 失效
标题翻译：差分放大器包括带偏置电阻的偏置电路
公开(公告)号：US5886578A
公开(公告)日：1999-03-23
申请号：US883455
申请日：1997-06-26
申请人： Miyo Miyashita , Kazuya Yamamoto
发明人： Miyo Miyashita , Kazuya Yamamoto
IPC分类号： H03K5/08 , H03F3/45 , H03K5/02 , H03K19/0185 , H03K19/0952
CPC分类号： H03F3/45076 , H03K19/018564 , H03K5/02
摘要： A differential amplifier receiving a first input signal and a second input signal, respectively, and amplifying voltage difference between the first and second input signals to output an output signal includes a first source follower circuit receiving an external data signal as the first input signal, and having an output node; a second source following circuit having a constant current source FET and receiving a reference voltage as the second input signal; and a bias circuit providing a signal having the same phase as the data signal from the output node of the first source follower circuit and inputting that signal to a gate terminal of the constant current source FET of the second source follower circuit. By providing an input interface circuit connected to an external signal source and producing a phase inversion signal from an input data signal in a differential amplifier or in a first stage differential amplifier connected to other amplifiers in multiple stages, the differential gain can be improved to a value approximately equal to that obtained when differential inputs are supplied.
摘要翻译：分别接收第一输入信号和第二输入信号的差分放大器以及放大第一和第二输入信号之间的电压差以输出输出信号包括接收作为第一输入信号的外部数据信号的第一源极跟随器电路，以及具有输出节点; 第二源电路，具有恒流源FET并接收参考电压作为第二输入信号; 以及偏置电路，提供与来自第一源极跟随器电路的输出节点的数据信号具有相同相位的信号，并将该信号输入到第二源极跟随器电路的恒流源FET的栅极端子。通过提供连接到外部信号源的输入接口电路，并且从差分放大器中的输入数据信号或在多级连接到其它放大器的第一级差分放大器中产生相位反转信号，可以将差分增益提高到大约等于提供差分输入时获得的值。

9. 再颁专利

USRE36068E Methods for treatment of sundamaged human skin with retinoids 失效
标题翻译：用类维生素A治疗失败的人类皮肤的方法
公开(公告)号：USRE36068E
公开(公告)日：1999-01-26
申请号：US630872
申请日：1996-04-02
申请人： Albert M. Kligman
发明人： Albert M. Kligman
IPC分类号： A61K8/67 , A61Q19/00 , A61Q19/08 , H03K19/003 , H03K19/0952 , A61K31/20
CPC分类号： A61K8/671 , A61Q19/004 , A61Q19/08 , H03K19/00361 , H03K19/0952
摘要： Various effects of photoaging or sundamage of skin including impairment of differentiation of epidermal epithelial cells and loss of collagen fibers, abnormal changes in elastic fibers and deterioration of small blood vessels in the dermis of the skin are retarded by applying topically to the epidermis in a maintenance therapy program effective amounts of retinoids including retinoid derivatives and stereoisomers thereof such that epithelial growths are substantially reduced and prevented and the skin substantially regains and maintains its firmness, turgor and elasticity. Moreover, with persistent treatment dermal blood cells and vessels increase and the epidermis and dermis thicken, resulting in improved ability of the skin to sense, resist and recover from irritation or injury. Further, hyperpigmentation, lines and wrinkles due to aging are reduced and prevented. The treatment is particularly useful for human facial skin and preferably applied in amounts insufficient to cause excessive irritation.
摘要翻译：皮肤的光老化或杂合物的各种影响，包括表皮上皮细胞的分化受损和胶原纤维的损失，弹性纤维的异常变化和皮肤真皮中的小血管的恶化的各种影响，通过在维护中局部应用于表皮来延缓治疗方案有效量的类视色素包括类视色素衍生物和其立体异构体，使得上皮生长显着减少和预防，并且皮肤基本上恢复并保持其坚实性，膨胀性和弹性。此外，持续治疗皮肤血细胞和血管增加，表皮和真皮增厚，导致皮肤感觉，抵抗和恢复刺激或损伤的能力提高。此外，减少并防止由于老化引起的色素沉着过度，色素沉着和皱纹。该治疗对于人的面部皮肤特别有用，并且优选以不足以引起过度刺激的量施用。

10. 发明授权

US5572561A Frequency dividing circuit 失效
标题翻译：分频电路
公开(公告)号：US5572561A
公开(公告)日：1996-11-05
申请号：US466728
申请日：1995-06-06
申请人： Kunihiro Usami , Miki Kubota
发明人： Kunihiro Usami , Miki Kubota
IPC分类号： H03K23/00 , H03B19/00 , H03F3/30 , H03K3/356 , H03K19/0952 , H03K23/44 , H03K23/54 , H03K21/00
CPC分类号： H03K23/44 , H03K3/356017
摘要： A frequency dividing circuit includes a first inverter circuit supplied with a first frequency-divided signal, a second inverter circuit supplied with a second frequency-divided signal which has a complementary relationship to the first frequency-divided signal, and a first pair of push-pull circuits. There are also provided a first switch circuit performing a first switching operation in response to a first input signal and selectively supplying output signals of the first and second inverter circuits to the first pair of push-pull circuits so that one of the first pair of push-pull circuits performs a pull-up operation when the other one thereof performs a pull-down operation. Further, there are provided a second pair of push-pull circuits, and a second switch circuit performing a second switching operation in response to a second input signal which has a complementary relationship to the first input signal and selectively supplying output signals of the first pair of push-pull circuits to the second pair of push-pull circuits so that one of the second pair of push-pull circuits performs a pull-up operation when the other one thereof performs a pull-down operation. The first and second frequency-divided signals are output from the second pair of push-pull circuits.
摘要翻译：分频电路包括被提供有第一分频信号的第一反相器电路，提供有与第一分频信号互补的第二分频信号的第二反相器电路，以及第一对推压信号，拉电路。还提供了第一开关电路，其响应于第一输入信号执行第一开关操作，并且选择性地将第一和第二反相器电路的输出信号提供给第一对推挽电路，使得第一对推压当其中一个执行下拉操作时， - 电路执行上拉操作。此外，提供了第二对推挽电路和第二开关电路，响应于与第一输入信号具有互补关系的第二输入信号执行第二开关操作，并且选择性地提供第一对的输出信号的推挽电路到第二对推挽电路，使得第二对推挽电路中的一个在其另一个推挽电路执行下拉操作时执行上拉操作。第一和第二分频信号从第二对推挽电路输出。

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