专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07261981B2 System and method of smoothing mask shapes for improved placement of sub-resolution assist features 失效
标题翻译：平滑掩模形状的系统和方法，以改进子分辨率辅助特征的放置
公开(公告)号：US07261981B2
公开(公告)日：2007-08-28
申请号：US10707778
申请日：2004-01-12
申请人： Mark A. Lavin , Lars W. Liebmann , Scott M. Mansfield , Maharaj Mukherjee , Zengqin Zhao
发明人： Mark A. Lavin , Lars W. Liebmann , Scott M. Mansfield , Maharaj Mukherjee , Zengqin Zhao
IPC分类号： G03F1/00
CPC分类号： G03F1/36
摘要： A method is disclosed for providing associated shapes of an optical lithography mask in relation to predetermined main shapes of the mask. The method includes generating simplified layout patterns from the predetermined main shapes of the mask. Such layout patterns are generated by eliminating detail of the main shapes which leads to unmanufacturable associated shapes while preserving geometrically relevant shape information. The associated shapes are then generated relative to the simplified mask patterns.
摘要翻译：公开了一种相对于掩模的预定主要形状提供光刻掩模的相关形状的方法。该方法包括从掩模的预定主要形状生成简化的布局图案。通过消除导致不可制造的相关形状的主要形状的细节来产生这种布局图案，同时保留几何相关的形状信息。然后相对于简化的掩模图案生成相关联的形状。

2. 发明授权

US06996797B1 Method for verification of resolution enhancement techniques and optical proximity correction in lithography 失效
标题翻译：用于光刻中分辨率增强技术和光学邻近校正的验证方法
公开(公告)号：US06996797B1
公开(公告)日：2006-02-07
申请号：US10904600
申请日：2004-11-18
申请人： Lars W. Liebmann , James A. Culp , Ioana C. Graur , Maharaj Mukherjee
发明人： Lars W. Liebmann , James A. Culp , Ioana C. Graur , Maharaj Mukherjee
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F1/36 , G06F2217/12 , Y02P90/265
摘要： A method for model-based verification of resolution enhancement techniques (RET) and optical proximity correction (OPC) in lithography includes scaling shapes of a drawn mask layout to their corresponding intended wafer dimensions so as to create a scaled image. A first feature of the scaled image is shifted with respect to a second feature thereof in accordance with a predetermined maximum overlay error. An intersection parameter of the first and said second features of the scaled image is calculated so as to determine a yield metric of an ideal layout. A first feature of a simulated wafer image is shifted with respect to a second feature thereof in accordance with the predetermined maximum overlay error. An intersection parameter of the first and said second features of the simulated wafer image is calculated so as to determine a yield metric of a simulated layout, and the yield metric of the simulated wafer image is compared to the yield metric of the scaled image.
摘要翻译：用于光刻中的分辨率增强技术（RET）和光学邻近校正（OPC）的基于模型的验证的方法包括将绘制的掩模布局的形状缩放到其相应的预期晶片尺寸，以便创建缩放图像。根据预定的最大重叠误差，缩放图像的第一特征相对于其第二特征偏移。计算缩放图像的第一和第二特征的交点参数，以便确定理想布局的屈服度量。模拟晶片图像的第一特征相对于其第二特征根据预定的最大重叠误差而偏移。计算模拟晶片图像的第一和第二特征的交叉参数，以便确定模拟布局的屈服度量，并将模拟晶片图像的屈服度量与缩放图像的屈服度量进行比较。

3. 发明授权

US08473885B2 Physical design system and method 失效
公开(公告)号：US08473885B2
公开(公告)日：2013-06-25
申请号：US13413759
申请日：2012-03-07
申请人： John M. Cohn , James A. Culp , Ulrich A. Finkler , Fook-Luen Heng , Mark A. Lavin , Jin Fuw Lee , Lars W. Liebmann , Gregory A. Northrop , Nakgeuon Seong , Rama N. Singh , Leon Stok , Pieter J. Woeltgens
发明人： John M. Cohn , James A. Culp , Ulrich A. Finkler , Fook-Luen Heng , Mark A. Lavin , Jin Fuw Lee , Lars W. Liebmann , Gregory A. Northrop , Nakgeuon Seong , Rama N. Singh , Leon Stok , Pieter J. Woeltgens
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5009 , G06F17/5072
摘要： A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.

4. 发明授权

US06578190B2 Process window based optical proximity correction of lithographic images 有权
公开(公告)号：US06578190B2
公开(公告)日：2003-06-10
申请号：US09759013
申请日：2001-01-11
申请人： Richard A. Ferguson , Mark A. Lavin , Lars W. Liebmann , Alfred K. Wong
发明人： Richard A. Ferguson , Mark A. Lavin , Lars W. Liebmann , Alfred K. Wong
IPC分类号： G06F1750
CPC分类号： G03F1/70 , G03F1/36
摘要： A method of creating a pattern for a mask adapted for use in lithographic production of features on a substrate. The method comprises initially providing a mask pattern of a feature to be created on the substrate using the mask. The method then includes establishing target dimensional bounds of the pattern, determining simulated achievable dimensional bounds of the pattern, comparing the target dimensional bounds of the pattern to the simulated achievable dimensional bounds of the pattern, and determining locations where the simulated achievable dimensional bounds of the pattern differ from the target dimensional bounds of the pattern. In its preferred embodiment, the feature is an integrated circuit to be lithographically produced on a semiconductor substrate.

5. 发明授权

US5883813A Automatic generation of phase shift masks using net coloring 失效
公开(公告)号：US5883813A
公开(公告)日：1999-03-16
申请号：US810844
申请日：1997-03-04
申请人： Young O. Kim , Mark A. Lavin , Lars W. Liebmann , Glenwood S. Weinert
发明人： Young O. Kim , Mark A. Lavin , Lars W. Liebmann , Glenwood S. Weinert
IPC分类号： G03F1/08 , G06F17/50 , H01L21/027 , G06K9/00
CPC分类号： G06F17/5068
摘要： According to the preferred embodiment, a method is provided for automatically coloring VLSI design elements for the purpose of assigning binary properties to the elements. The preferred method is particularly applicable for use generating phase shift mask designs from VLSI CAD datasets. The preferred method uses net coloring to automatically generate a data set of colored elements. The preferred method is not dependent on the order in which the elements are operated upon. The preferred method has the additional advantage of being able to automatically detect conflicts that prevent the VLSI design from being optimally colored. The preferred method is equally applicable to hierarchical VLSI databases with nested components and traditional flat databases. When applied the hierarchical databases, the preferred method provides element coloring with minimal data flattening required.

6. 发明授权

US5537648A Geometric autogeneration of "hard" phase-shift designs for VLSI 失效
标题翻译： VLSI“硬”相移设计的几何自动生成
公开(公告)号：US5537648A
公开(公告)日：1996-07-16
申请号：US290625
申请日：1994-08-15
申请人： Lars W. Liebmann , Mark A. Lavin , Pia N. Sanda
发明人： Lars W. Liebmann , Mark A. Lavin , Pia N. Sanda
IPC分类号： G03F1/00 , G06F17/50 , G06F3/00 , G06F15/00
CPC分类号： G06F17/5068 , Y10S706/919 , Y10S706/92
摘要： A method implemented in a computer aided design (CAD) system automatically generates phase shifted mask designs for very large scale integrated (VLSI) chips from existing circuit design data. The system uses a series of basic geometric operations to design areas requiring phase assignment, resolve conflicting phase assignments, and eliminate unwanted phase edges. This process allows automatic generation of phase shift mask data from any circuit design that allows for phase shifting. Since the dimensional input for all geometric operations is directly linked to the design ground rules given to the circuit designers, any designable circuit layout can also be phase shifted with this algorithm. The autogeneration of phase shift patterns around an existing circuit design is broken down into four major tasks: 1. Define areas that need a phase assignment; 2. Make a first pass phase assignment unique to each critical feature and define "runs" of interrelated critical features; 3. Propagation phase assignment through the "runs"; and 4. Design trim features.
摘要翻译：在计算机辅助设计（CAD）系统中实现的一种方法是从现有的电路设计数据自动生成用于大规模集成（VLSI）芯片的相移掩模设计。该系统使用一系列基本几何操作来设计需要相位分配的区域，解决冲突的相位分配，并消除不需要的相位边缘。该过程允许从允许相移的任何电路设计自动生成相移掩模数据。由于所有几何运算的尺寸输入与给予电路设计者的设计基准规则直接相关，任何可设计的电路布局也可以通过该算法相移。现有电路设计周围的相移模式的自动生成分为四个主要任务：1.定义需要相位分配的区域; 2.对每个关键特征进行唯一的第一遍相位分配，并定义相关关键特征的“运行”; 传播阶段通过“运行”分配; 和4.设计修剪功能。

7. 发明申请

US20120167029A1 PHYSICAL DESIGN SYSTEM AND METHOD 失效
标题翻译：物理设计系统与方法
公开(公告)号：US20120167029A1
公开(公告)日：2012-06-28
申请号：US13413759
申请日：2012-03-07
申请人： John M. Cohn , James A. Culp , Ulrich A. Finkler , Fook-Luen Heng , Mark A. Lavin , Jin Fuw Lee , Lars W. Liebmann , Gregory A. Northrop , Nakgeuon Seong , Rama N. Singh , Leon Stok , Pieter J. Woltgens
发明人： John M. Cohn , James A. Culp , Ulrich A. Finkler , Fook-Luen Heng , Mark A. Lavin , Jin Fuw Lee , Lars W. Liebmann , Gregory A. Northrop , Nakgeuon Seong , Rama N. Singh , Leon Stok , Pieter J. Woltgens
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5009 , G06F17/5072
摘要： A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.
摘要翻译：一种用于设计复杂集成电路（IC）的设计系统，一种IC设计方法和程序产品。布局单元接收表示网格和字形格式的部分的电路描述。检查单元检查设计的网格和字形部分。精心设计单元从检查的设计生成目标布局。数据准备单元准备掩模制作的目标布局。模式高速缓存单元用先前缓存的结果有选择地替换设计的部分，以提高设计效率。

8. 发明授权

US07536664B2 Physical design system and method 失效
标题翻译：物理设计系统及方法
公开(公告)号：US07536664B2
公开(公告)日：2009-05-19
申请号：US10917193
申请日：2004-08-12
申请人： John M. Cohn , James A. Culp , Ulrich A. Finkler , Fook-Luen Heng , Mark A. Lavin , Jin Fuw Lee , Lars W. Liebmann , Gregory A. Northrop , Nakgeuon Seong , Rama N. Singh , Leon Stok , Pieter J. Woltgens
发明人： John M. Cohn , James A. Culp , Ulrich A. Finkler , Fook-Luen Heng , Mark A. Lavin , Jin Fuw Lee , Lars W. Liebmann , Gregory A. Northrop , Nakgeuon Seong , Rama N. Singh , Leon Stok , Pieter J. Woltgens
IPC分类号： G06F17/50 , G06F19/00
CPC分类号： G06F17/5081 , G06F17/5009 , G06F17/5072
摘要： A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.
摘要翻译：一种用于设计复杂集成电路（IC）的设计系统，一种IC设计方法和程序产品。布局单元接收表示网格和字形格式的部分的电路描述。检查单元检查设计的网格和字形部分。精心设计单元从检查的设计生成目标布局。数据准备单元准备掩模制作的目标布局。模式高速缓存单元用先前缓存的结果有选择地替换设计的部分，以提高设计效率。

9. 发明授权

US07147976B2 Binary OPC for assist feature layout optimization 失效
公开(公告)号：US07147976B2
公开(公告)日：2006-12-12
申请号：US11251981
申请日：2005-10-17
申请人： Lars W. Liebmann , Richard A. Ferguson , Allen H. Gabor , Mark A. Lavin
发明人： Lars W. Liebmann , Richard A. Ferguson , Allen H. Gabor , Mark A. Lavin
IPC分类号： G03F9/00 , G06F17/50
CPC分类号： G03F1/36
摘要： A method of forming a photolithographic mask layout with Sub-Resolution Assist Feature (SRAF) elements on a mask for correcting for proximity effects for a pattern imaged comprising the steps of developing a layout of mask features for printing main pattern features. Provide a table of SRAF element data including spacing of main pattern features and SRAF elements, applying SRAF elements to the mask layout as a function of spacing of main pattern features and SRAF elements, legalizing the SRAF elements as a function of style options, and providing a target pattern comprising a modified layout for the mask, identifying problem edge segments of an SRAF element of the target pattern at risk of causing a printing defect, applying a selected bias to the problem edge segments to modify the pattern where there are areas of SRAF element loss, and providing an output of a modified pattern with modified SRAF elements removing the areas of SRAF element loss. The system can provide SRAF elements to the mask layout as a function of spacing of main pattern features and SRAF elements may be based on data from the SRAF table; or the system can applying model based OPC for exposure dose values based on data from the SRAF table.

10. 发明授权

US5636131A Geometric autogeneration of"hard"phase-shift designs for VLSI 失效
标题翻译： VLSI“硬”相移设计的几何自动生成
公开(公告)号：US5636131A
公开(公告)日：1997-06-03
申请号：US440051
申请日：1995-05-12
申请人： Lars W. Liebmann , Mark A. Lavin , Pia N. Sanda
发明人： Lars W. Liebmann , Mark A. Lavin , Pia N. Sanda
IPC分类号： G03F1/00 , G06F17/50 , G06F15/00 , G06F3/00
CPC分类号： G06F17/5068 , Y10S706/919 , Y10S706/92
摘要： An apparatus implemented in a computer aided design (CAD) system automatically generates phase shifted mask designs for very large scale integrated (VLSI) chips from existing circuit design data. The system uses a series of basic geometric operations to design areas requiring phase assignment, resolve conflicting phase assignments, and eliminate unwanted phase edges. This apparatus allows automatic generation of phase shift mask data from any circuit design that allows for phase shifting. Since the dimensional input for all geometric operations is directly linked to the design ground rules given to the circuit designers, any designable circuit layout can also be phase shifted with this algorithm. The autogeneration of phase shift patterns around an existing circuit design is broken down into four major tasks: 1. Define areas that need a phase assignment; 2. Make a first pass phase assignment unique to each critical feature and define "runs" of interrelated critical features; 3. Propagation phase assignment through the "runs"; and 4. Design trim features.
摘要翻译：在计算机辅助设计（CAD）系统中实现的装置通过现有电路设计数据自动生成用于大规模集成（VLSI）芯片的相移掩模设计。该系统使用一系列基本几何操作来设计需要相位分配的区域，解决冲突的相位分配，并消除不需要的相位边缘。该装置允许从允许相移的任何电路设计自动生成相移掩模数据。由于所有几何运算的尺寸输入与给予电路设计者的设计基准规则直接相关，任何可设计的电路布局也可以通过该算法相移。现有电路设计周围的相移模式的自动生成分为四个主要任务：1.定义需要相位分配的区域; 2.对每个关键特征进行唯一的第一遍相位分配，并定义相关关键特征的“运行”; 传播阶段通过“运行”分配; 和4.设计修剪功能。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式