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1. 发明授权

US6066180A Automatic generation of phase shift masks using net coloring 有权
标题翻译：使用净色自动生成相移掩模
公开(公告)号：US6066180A
公开(公告)日：2000-05-23
申请号：US268414
申请日：1999-03-15
申请人： Young O. Kim , Mark A. Lavin , Lars W. Liebmann , Glenwood S. Weinert
发明人： Young O. Kim , Mark A. Lavin , Lars W. Liebmann , Glenwood S. Weinert
IPC分类号： G03F1/08 , G06F17/50 , H01L21/027 , G06K9/00
CPC分类号： G06F17/5068
摘要： According to the preferred embodiment, a method is provided for automatically coloring VLSI design elements for the purpose of assigning binary properties to the elements. The preferred method is particularly applicable for use generating phase shift mask designs from VLSI CAD datasets. The preferred method uses net coloring to automatically generate a data set of colored elements. The preferred method is not dependent on the order in which the elements are operated upon. The preferred method has the additional advantage of being able to automatically detect conflicts that prevent the VLSI design from being optimally colored. The preferred method is equally applicable to hierarchical VLSI databases with nested components and traditional flat databases. When applied the hierarchical databases, the preferred method provides element coloring with minimal data flattening required.
摘要翻译：根据优选实施例，提供了一种用于自动着色VLSI设计元件以便为元件分配二进制特性的方法。优选的方法特别适用于从VLSI CAD数据集产生相移掩模设计。首选方法使用净色来自动生成彩色元素的数据集。优选的方法不依赖于操作元件的顺序。优选的方法具有能够自动检测阻止VLSI设计被最佳着色的冲突的额外优点。优选的方法同样适用于具有嵌套组件和传统平面数据库的分层VLSI数据库。当应用分层数据库时，首选方法提供了元素着色，需要最少的数据平坦化。

2. 发明授权

US5883813A Automatic generation of phase shift masks using net coloring 失效
公开(公告)号：US5883813A
公开(公告)日：1999-03-16
申请号：US810844
申请日：1997-03-04
申请人： Young O. Kim , Mark A. Lavin , Lars W. Liebmann , Glenwood S. Weinert
发明人： Young O. Kim , Mark A. Lavin , Lars W. Liebmann , Glenwood S. Weinert
IPC分类号： G03F1/08 , G06F17/50 , H01L21/027 , G06K9/00
CPC分类号： G06F17/5068
摘要： According to the preferred embodiment, a method is provided for automatically coloring VLSI design elements for the purpose of assigning binary properties to the elements. The preferred method is particularly applicable for use generating phase shift mask designs from VLSI CAD datasets. The preferred method uses net coloring to automatically generate a data set of colored elements. The preferred method is not dependent on the order in which the elements are operated upon. The preferred method has the additional advantage of being able to automatically detect conflicts that prevent the VLSI design from being optimally colored. The preferred method is equally applicable to hierarchical VLSI databases with nested components and traditional flat databases. When applied the hierarchical databases, the preferred method provides element coloring with minimal data flattening required.

3. 发明授权

US5481473A System and method for building interconnections in a hierarchical circuit design 失效
标题翻译：用于在分层电路设计中构建互连的系统和方法
公开(公告)号：US5481473A
公开(公告)日：1996-01-02
申请号：US19970
申请日：1993-02-19
申请人： Young O. Kim , Philip J. Russell , Glenwood S. Weinert
发明人： Young O. Kim , Philip J. Russell , Glenwood S. Weinert
IPC分类号： G06F17/50 , H01L21/70
CPC分类号： G06F17/5081
摘要： A computer-based system and method is provided for creating a representation of interconnections between VLSI circuit design components. A VLSI circuit design component identifying a leaf design entity is stored in memory. Placements in the design where the design component appears are stored in memory. A set of links is formed to connect placements to one another. The links further specify placement of the design component in the circuit design. The interconnections themselves are then computed. The interconnections denote where placements of the VLSI circuit design component instances are interconnected, and may specify any meaningful coupling, such as electrical conductivity, magnetic, or optical. The interconnections are represented by a nested net graph which includes a list of nets, and instance counts associated with the nets. The nested net graph may also include a second list, which specifies instances of lower nested nets contained in the nested net graph. The nested net graph may further include a shape-to-net table attached at the root of the nested net graph. The shape-to-net table defines a mapping from the VLSI circuit design component to a corresponding net. Also provided is a system and method for building interconnections using a bridge component, or bridge net. The bridge net denotes the interconnection between two nets derived from a pair of VLSI circuit design component instances.
摘要翻译：提供了基于计算机的系统和方法来创建VLSI电路设计组件之间的互连的表示。识别叶设计实体的VLSI电路设计组件被存储在存储器中。设计组件出现的设计中的展示位置存储在内存中。形成一组链接以将展示位置彼此连接。链接进一步指定了设计组件在电路设计中的布局。然后计算互连本身。互连表示VLSI电路设计组件实例的布局相互连接，并且可以指定任何有意义的耦合，例如电导率，磁性或光学。互连由嵌套的网图表示，其包括网络列表和与网络相关联的实例计数。嵌套网图还可以包括第二列表，其指定嵌套网图中包含的较低嵌套网络的实例。嵌套网图可以进一步包括附加在嵌套网图的根处的形状到网表。形状到网格表定义了从VLSI电路设计组件到相应网络的映射。还提供了使用桥组件或桥网构建互连的系统和方法。桥网表示从一对VLSI电路设计组件实例导出的两个网络之间的互连。

4. 发明授权

US5519628A System and method for formulating subsets of a hierarchical circuit design 失效
标题翻译：用于制定分层电路设计子集的系统和方法
公开(公告)号：US5519628A
公开(公告)日：1996-05-21
申请号：US19927
申请日：1993-02-19
申请人： Philip J. Russell , Glenwood S. Weinert
发明人： Philip J. Russell , Glenwood S. Weinert
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A computer-based system and method is provided for building subsets of a hierarchical circuit design. A VLSI circuit design component is stored in computer memory. The design component identifies a leaf design entity in the hierarchical circuit design. A set of placements is determined representing positions in the hierarchical circuit design where the VLSI circuit design component appears. The placements form a subset of instances of the leaf design entity. A set of links is created. The links are associated in memory with both the VLSI circuit design component and the placements, and connect various ones of the placements to one another to further denote placement of the VLSI circuit design component within the hierarchical circuit design. A subset list is appended to the VLSI circuit design component in computer memory. The subset list denotes the previously-determined subset and includes placements where the VLSI circuit design component is identified in the hierarchical circuit design. The identified placements may indicate exclusion of a particular instance of a design component from the hierarchical circuit design, or inclusion of a particular instance.
摘要翻译：提供了一种基于计算机的系统和方法来构建分层电路设计的子集。 VLSI电路设计组件存储在计算机存储器中。设计组件在分层电路设计中识别叶设计实体。确定一组展示位置，表示在VLSI电路设计组件出现的分层电路设计中的位置。展示位置形成叶设计实体的实例的一个子集。创建一组链接。链路在存储器中与VLSI电路设计部件和放置相关联，并且将各种布置彼此连接以进一步表示VLSI电路设计部件在分级电路设计中的放置。子集列表附加到计算机存储器中的VLSI电路设计组件。子集列表表示先前确定的子集，并且包括在分级电路设计中识别VLSI电路设计组件的位置。所识别的布置可以指示从分层电路设计中排除设计组件的特定实例或者包括特定实例。

5. 发明授权

US5528508A System and method for verifying a hierarchical circuit design 失效
标题翻译：用于验证分层电路设计的系统和方法
公开(公告)号：US5528508A
公开(公告)日：1996-06-18
申请号：US19971
申请日：1993-02-19
申请人： Philip J. Russell , Glenwood S. Weinert
发明人： Philip J. Russell , Glenwood S. Weinert
IPC分类号： G06F17/50 , H01L21/98
CPC分类号： G06F17/5081
摘要： A computer-based system and method is provided for building a representation of a hierarchical circuit design and component intrusions for the components making up the circuit design, as well as for verifying a design so-represented. For a subject hierarchical circuit design, a VLSI circuit design component representing a leaf design entity is isolated. A set of locations in the design where the component appears is determined. These locations represent unique instances of the leaf design entity. A set of links is associated with the VLSI circuit design component and the locations. The links connect various ones of the locations to one another to denote placement of the component within the hierarchical circuit design. To complete the representation, a set of instance counts is computed, one instance count for each location in the design where the component is represented. Each instance count denotes the number of instances of the component represented at the location with which the instance count is associated. Additional features of the invention include applicability to numerous types of design components (e.g., devices, nets, microprocessors, resistors), correspondence between each node of the inverse layout graph and a unique placement in the hierarchical circuit design, and the ability to determine intrusions according to any measure of proximity.
摘要翻译：提供了一种基于计算机的系统和方法，用于构建组成电路设计的组件的分层电路设计和组件入侵的表示，以及用于验证如此表示的设计。对于主题分层电路设计，隔离了表示叶设计实体的VLSI电路设计组件。确定组件出现在设计中的一组位置。这些位置表示叶设计实体的唯一实例。一组链路与VLSI电路设计组件和位置相关联。链接将各个位置彼此连接以表示分层电路设计中的部件的放置。要完成表示，将计算一组实例计数，为组件所在的设计中的每个位置计算一个实例数。每个实例计数表示在与实例计数关联的位置处表示的组件的实例数。本发明的附加特征包括适用于许多类型的设计组件（例如，设备，网络，微处理器，电阻器），反向布局图的每个节点与分级电路设计中的唯一布置之间的对应关系以及确定入侵的能力根据任何接近程度。

6. 发明授权

US5497334A Application generator for use in verifying a hierarchical circuit design 失效
标题翻译：应用程序生成器用于验证分层电路设计
公开(公告)号：US5497334A
公开(公告)日：1996-03-05
申请号：US19924
申请日：1993-02-19
申请人： Philip J. Russell , Glenwood S. Weinert
发明人： Philip J. Russell , Glenwood S. Weinert
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5022
摘要： A computer based system and method is provided for generating a design verification scheme for a hierarchical circuit design. A set of directives received describing design checks to be performed on a hierarchical circuit design. The directives are functionally decomposed into primitive functions required to perform them. A primary iteration level is established for each directive, and a data flow dependency is determined for the directives. Based on the data now dependency, a sequence or operations is organized. The operations are optimized in one or more ways to improve the efficiency of the design verification process. The optimized operations are coded into an application program which executes in a computer processor. The application program accesses the VLSI circuit design under review and performs the directives using the data structures allocated during schema generation.
摘要翻译：提供了一种基于计算机的系统和方法，用于生成用于分级电路设计的设计验证方案。收到的一组指令描述了要在分层电路设计上执行的设计检查。这些指令在功能上被分解为执行它们所需的原始函数。为每个指令建立主迭代级别，并为指令确定数据流依赖性。根据现在的数据依赖性，组织了一个序列或操作。这些操作以一种或多种方式进行了优化，以提高设计验证过程的效率。优化的操作被编码成在计算机处理器中执行的应用程序。应用程序访问正在审查的VLSI电路设计，并使用在模式生成期间分配的数据结构来执行指令。

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