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1. 发明授权

US09046788B2 Method for monitoring focus on an integrated wafer 有权
标题翻译：用于监控集成晶圆的方法
公开(公告)号：US09046788B2
公开(公告)日：2015-06-02
申请号：US12122929
申请日：2008-05-19
申请人： Allen H. Gabor , Wai-Kin Li
发明人： Allen H. Gabor , Wai-Kin Li
IPC分类号： G03B27/52 , G03B27/68 , G03F7/20
CPC分类号： G03F7/70333 , G03F7/70508 , G03F7/70641
摘要： A method and apparatus are provided for improving the focusing of a substrate such as a wafer during the photolithography imaging procedure of a semiconductor manufacturing process. The invention is particularly useful for step-and-scan system and the CD of two features in each exposure field are measured in fields exposed at varying focus to form at least two Bossung curves. Exposure focus instructions are calculated based on the intersection point of the curves and the wafer is then scanned and imaged based on the calculated exposure focus instructions. In another aspect of the invention, when multiple wafers are being processed operational variances may cause a drift in the focus. The focus drift can be easily corrected by measuring the critical dimension of each of the features and comparing the difference to determine if any focus offset is needed to return the focus to the original calculated focus value.
摘要翻译：提供了一种用于在半导体制造工艺的光刻成像过程期间改善诸如晶片之类的衬底的聚焦的方法和装置。本发明对于步进扫描系统特别有用，并且每个曝光场中的两个特征的CD在以不同焦点曝光的场中测量以形成至少两个Bossung曲线。基于曲线的交点，然后基于计算出的曝光聚焦指令对晶片进行扫描和成像，计算曝光对焦指令。在本发明的另一方面，当正在处理多个晶片时，操作方差可能导致焦点漂移。可以通过测量每个特征的临界尺寸并比较差异来确定是否需要任何聚焦偏移以将焦点返回到原始计算的聚焦值，从而容易地校正聚焦漂移。

2. 发明授权

US08673165B2 Sidewall image transfer process with multiple critical dimensions 有权
标题翻译：具有多个关键尺寸的侧壁图像传输过程
公开(公告)号：US08673165B2
公开(公告)日：2014-03-18
申请号：US13267198
申请日：2011-10-06
申请人： Sudharshanan Raghunathan , Sivananda Kanakasabapathy , Ryan O. Jung , Allen H Gabor , Sean D. Burns , Erin Catherine McLellan
发明人： Sudharshanan Raghunathan , Sivananda Kanakasabapathy , Ryan O. Jung , Allen H Gabor , Sean D. Burns , Erin Catherine McLellan
IPC分类号： H01L21/311
CPC分类号： H01L21/0338 , H01L21/0337
摘要： Embodiment of the present invention provides a method of forming a semiconductor device in a sidewall image transfer process with multiple critical dimensions. The method includes forming a multi-level dielectric layer over a plurality of mandrels, the multi-level dielectric layer having a plurality of regions covering the plurality of mandrels, the plurality of regions of the multi-level dielectric layer having different thicknesses; etching the plurality of regions of the multi-level dielectric layer into spacers by applying a directional etching process, the spacers being formed next to sidewalls of the plurality of mandrels and having different widths corresponding to the different thicknesses of the plurality of regions of the multi-level dielectric layer; removing the plurality of mandrels in-between the spacers; and transferring bottom images of the spacers into one or more layers underneath the spacers.
摘要翻译：本发明的实施例提供了一种在具有多个关键尺寸的侧壁图像转印工艺中形成半导体器件的方法。该方法包括在多个心轴上形成多层介质层，多层介质层具有覆盖多个心轴的多个区域，多层介质层的多个区域具有不同的厚度; 通过施加定向蚀刻工艺将多层电介质层的多个区域蚀刻成间隔物，间隔物形成在多个心轴的侧壁旁边，并且具有对应于多个区域的多个区域的不同厚度的不同宽度电介质层; 去除间隔件之间的多个心轴; 并将间隔物的底部图像转移到间隔物下面的一个或多个层中。

3. 发明申请

US20120126294A1 WAFER FILL PATTERNS AND USES 有权
标题翻译： WAFER FILL PATTERNS和用途
公开(公告)号：US20120126294A1
公开(公告)日：2012-05-24
申请号：US12949148
申请日：2010-11-18
申请人： Martin Burkhardt , Matthew E. Colburn , Allen H. Gabor , Oleg Gluschenkov , Scott D. Halle , Howard S. Landis , Helen Wang
发明人： Martin Burkhardt , Matthew E. Colburn , Allen H. Gabor , Oleg Gluschenkov , Scott D. Halle , Howard S. Landis , Helen Wang
IPC分类号： H01L29/78 , H01L21/28 , H01L29/06 , H01L21/302
CPC分类号： H01L29/78 , H01L21/28123 , H01L21/32139 , H01L22/12 , H01L22/26
摘要： A method of forming a semiconductor device having a substrate, an active region and an inactive region includes: forming a hardmask layer over the substrate; transferring a first pattern into the hardmask layer in the active region of the semiconductor device; forming one or more fills in the inactive region; forming a cut-away hole within, covering, or partially covering, the one or more fills to expose a portion of the hardmask layer, the exposed portion being within the one or more fills; and exposing the hardmask layer to an etchant to divide the first pattern into a second pattern including at least two separate elements.
摘要翻译：一种形成具有衬底，有源区和非活性区的半导体器件的方法包括：在衬底上形成硬掩模层; 将第一图案转移到半导体器件的有源区中的硬掩模层中; 在非活性区域中形成一个或多个填充物; 在所述一个或多个填充物内部，覆盖或部分地覆盖所述硬掩模层的一部分以暴露所述硬掩模层的一部分内的切除孔，所述暴露部分在所述一个或多个填充物内; 以及将所述硬掩模层暴露于蚀刻剂以将所述第一图案划分成包括至少两个分离元件的第二图案。

4. 发明授权

US08158334B2 Methods for forming a composite pattern including printed resolution assist features 有权
标题翻译：用于形成包括印刷分辨率辅助特征的复合图案的方法
公开(公告)号：US08158334B2
公开(公告)日：2012-04-17
申请号：US12013627
申请日：2008-01-14
申请人： Allen H. Gabor , Scott D. Halle , Helen Wang
发明人： Allen H. Gabor , Scott D. Halle , Helen Wang
IPC分类号： G03F7/26
CPC分类号： H01L21/0337 , G03F7/70433 , G03F7/70466
摘要： An underlayer to be patterned with a composite pattern is formed on a substrate. The composite pattern is decomposed into a first pattern and a second pattern, each having reduced complexity than the composite pattern. A hard mask layer is formed directly on the underlying layer. A first photoresist is applied over the hard mask layer and lithographically patterned with the first pattern, which is transferred into the hard mask layer by a first etch. A second photoresist is applied over the hard mask layer. The second photoresist is patterned with the second pattern to expose portions of the underlying layer. The exposed portions of the underlying layer are etched employing the second photoresist and the hard mask layer, which contains the first pattern so that the composite pattern is transferred into the underlying layer.
摘要翻译：在基板上形成图案化复合图案的底层。复合图案被分解为第一图案和第二图案，每个图案具有比复合图案更低的复杂度。硬掩模层直接形成在下层上。将第一光致抗蚀剂施加在硬掩模层上并用第一图案进行光刻图案化，其通过第一蚀刻转移到硬掩模层中。在硬掩模层上施加第二光致抗蚀剂。用第二图案对第二光致抗蚀剂进行图案化以暴露下层的部分。使用包含第一图案的第二光致抗蚀剂和硬掩模层来蚀刻下层的暴露部分，使得复合图案被转移到下层中。

5. 发明授权

US08039203B2 Integrated circuits and methods of design and manufacture thereof 有权
标题翻译：集成电路及其设计和制造方法
公开(公告)号：US08039203B2
公开(公告)日：2011-10-18
申请号：US12126741
申请日：2008-05-23
申请人： Helen Wang , Scott D. Halle , Henning Haffner , Haoren Zhuang , Klaus Herold , Matthew E. Colburn , Allen H. Gabor , Zachary Baum , Scott M. Mansfield , Jason E. Meiring
发明人： Helen Wang , Scott D. Halle , Henning Haffner , Haoren Zhuang , Klaus Herold , Matthew E. Colburn , Allen H. Gabor , Zachary Baum , Scott M. Mansfield , Jason E. Meiring
IPC分类号： H01L21/027
CPC分类号： H01L21/32139 , G03F1/36 , G03F1/70 , H01L21/0274 , H01L21/28123 , H01L21/823437 , Y10S438/942
摘要： Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes depositing a gate material over a semiconductor substrate, and depositing a first resist layer over the gate material. A first mask is used to pattern the first resist layer to form first and second resist features. The first resist features include pattern for gate lines of the semiconductor device and the second resist features include printing assist features. A second mask is used to form a resist template; the second mask removes the second resist features.
摘要翻译：公开了集成电路及其制造和设计方法。例如，制造方法包括在半导体衬底上沉积栅极材料，并且在栅极材料上沉积第一抗蚀剂层。使用第一掩模来图案化第一抗蚀剂层以形成第一和第二抗蚀剂特征。第一抗蚀剂特征包括半导体器件的栅极线的图案，第二抗蚀剂特征包括印刷辅助特征。使用第二掩模形成抗蚀剂模板; 第二掩模移除第二抗蚀剂特征。

6. 发明授权

US07727825B2 Polyconductor line end formation and related mask 失效
标题翻译：多导体线端部形成和相关掩模
公开(公告)号：US07727825B2
公开(公告)日：2010-06-01
申请号：US12178072
申请日：2008-07-23
申请人： Shahid A. Butt , Allen H. Gabor , Donald J. Samuels
发明人： Shahid A. Butt , Allen H. Gabor , Donald J. Samuels
IPC分类号： H01L21/00
CPC分类号： G03F7/70441 , G03F1/36 , H01L21/0335 , H01L21/32139 , H01L21/76838
摘要： Methods of forming adjacent polyconductor line ends and a mask therefor are disclosed. In one embodiment, the method includes forming a polyconductor layer over an isolation region; forming a mask over the polyconductor layer, the mask including shapes to create the polyconductor line ends and a correction element to ensure a designed proximity of the polyconductor line ends; and etching the polyconductor layer using the patterned photoresist mask to create the adjacent polyconductor line ends, wherein the correction element is removed during the etching.
摘要翻译：公开了形成相邻多导体线端的方法及其掩模。在一个实施例中，该方法包括在隔离区域上形成多导体层; 在所述多导体层上形成掩模，所述掩模包括形成多导体线端的形状和校正元件，以确保多导体线的设计接近端; 以及使用图案化的光致抗蚀剂掩模蚀刻多导体层以产生相邻的多导体线端，其中在蚀刻期间去除校正元件。

7. 发明授权

US07541613B2 Methods for reducing within chip device parameter variations 有权
标题翻译：降低芯片内部器件参数变化的方法
公开(公告)号：US07541613B2
公开(公告)日：2009-06-02
申请号：US12117014
申请日：2008-05-08
申请人： Brent Alan Anderson , Shahid Ahmad Butt , Allen H. Gabor , Patrick Edward Lindo , Edward Joseph Nowak , Jed Hickory Rankin
发明人： Brent Alan Anderson , Shahid Ahmad Butt , Allen H. Gabor , Patrick Edward Lindo , Edward Joseph Nowak , Jed Hickory Rankin
IPC分类号： H01L23/58 , H01L21/66 , H01L21/00
CPC分类号： H01L22/20
摘要： A method of reducing parametric variation in an integrated circuit (IC) chip and an IC chip with reduced parametric variation. The method includes: on a first wafer having a first arrangement of chips, each IC chip divided into a second arrangement of regions, measuring a test device parameter of test devices distributed in different regions; and on a second wafer having the first arrangement of IC chips and the second arrangement of regions, adjusting a functional device parameter of identically designed field effect transistors within one or more regions of all IC chips of the second wafer based on a values of the test device parameter measured on test devices in regions of the IC chip of the first wafer by a non-uniform adjustment of physical or metallurgical polysilicon gate widths of the identically designed field effect transistors from region to region within each IC chip.
摘要翻译：一种降低参数变化减小的集成电路（IC）芯片和IC芯片的参数变化的方法。该方法包括：在具有第一芯片布置的第一晶片上，将每个IC芯片分成第二区域布置，测量分布在不同区域中的测试装置的测试装置参数; 并且在具有IC芯片的第一布置和第二区域布置的第二晶片上，基于测试值调整第二晶片的所有IC芯片的一个或多个区域内相同设计的场效应晶体管的功能器件参数在第一晶片的IC芯片的区域中的测试装置上测量的器件参数通过在每个IC芯片内的区域到区域的相同设计的场效应晶体管的物理或冶金多晶硅栅极宽度的不均匀调整而不均匀地调整。

8. 发明申请

US20090117737A1 POLYCONDUCTOR LINE END FORMATION AND RELATED MASK 失效
标题翻译：聚合物线形成和相关掩模
公开(公告)号：US20090117737A1
公开(公告)日：2009-05-07
申请号：US12178072
申请日：2008-07-23
申请人： Shahid A. Butt , Allen H. Gabor , Donald J. Samuels
发明人： Shahid A. Butt , Allen H. Gabor , Donald J. Samuels
IPC分类号： H01L21/44 , G03F1/00
CPC分类号： G03F7/70441 , G03F1/36 , H01L21/0335 , H01L21/32139 , H01L21/76838
摘要： Methods of forming adjacent polyconductor line ends and a mask therefor are disclosed. In one embodiment, the method includes forming a polyconductor layer over an isolation region; forming a mask over the polyconductor layer, the mask including shapes to create the polyconductor line ends and a correction element to ensure a designed proximity of the polyconductor line ends; and etching the polyconductor layer using the patterned photoresist mask to create the adjacent polyconductor line ends, wherein the correction element is removed during the etching.
摘要翻译：公开了形成相邻多导体线端的方法及其掩模。在一个实施例中，该方法包括在隔离区域上形成多导体层; 在所述多导体层上形成掩模，所述掩模包括形成多导体线端的形状和校正元件，以确保多导体线的设计接近端; 以及使用图案化的光致抗蚀剂掩模蚀刻多导体层以产生相邻的多导体线端，其中在蚀刻期间去除校正元件。

9. 发明申请

US20090065956A1 MEMORY CELL 审中-公开
标题翻译：记忆体
公开(公告)号：US20090065956A1
公开(公告)日：2009-03-12
申请号：US11853358
申请日：2007-09-11
申请人： Matthew E. Colburn , Allen H. Gabor , Scott D. Halle , Donald J. Samuels
发明人： Matthew E. Colburn , Allen H. Gabor , Scott D. Halle , Donald J. Samuels
IPC分类号： H01L23/48
CPC分类号： G11C5/063 , H01L27/0207 , H01L27/105 , H01L27/1052 , H01L27/11 , H01L27/115
摘要： Methods of forming line ends and a related memory cell including the line ends are disclosed. In one embodiment, the memory cell includes fa first device having a first conductive line extending over a first active region and having a first line end of the first conductive line positioned over an isolation region adjacent to the first active region; and a second device having a second conductive line extending over one of a second active region and a contact element and having a second line end of the second conductive line positioned over the isolation region adjacent to the one of the second active region and the contact element, wherein the first line end and the second line end each include a bulbous end that is distanced from a respective active region or contact element.
摘要翻译：公开了形成线端的方法和包括线端的相关存储单元。在一个实施例中，存储单元包括fa第一器件，其具有在第一有源区上延伸的第一导线，并且第一导线的第一线端位于与第一有源区相邻的隔离区上; 以及第二装置，具有延伸到第二有源区和接触元件之一上的第二导线，并且第二导线的第二线端位于与第二有源区和接触元件中的一个相邻的隔离区上方，其中所述第一线端和所述第二线端各自包括与相应的有源区域或接触元件间隔开的球状端。

10. 发明申请

US20080286683A1 COMPOSITE STRUCTURES TO PREVENT PATTERN COLLAPSE 失效
标题翻译：复合结构防止图案褶皱
公开(公告)号：US20080286683A1
公开(公告)日：2008-11-20
申请号：US11750026
申请日：2007-05-17
申请人： Colin J. Brodsky , Allen H. Gabor , Javier Perez
发明人： Colin J. Brodsky , Allen H. Gabor , Javier Perez
IPC分类号： G03C1/00 , G03C5/00
CPC分类号： G03F7/0035
摘要： A method and a structure. The structure includes: a solid core comprising a first photoresist material, the core having a bottom surface on a substrate, a top surface and opposite first and second side surfaces between the top surface and the bottom surface; and a shell comprising a second photoresist material, the shell on the top surface of the substrate, the shell containing a cavity open to the top surface of the substrate, the shell formed over the top surface and the first and second side surfaces walls of the core, the core completely filling the cavity. The core is stiffer than the shell. The method includes: forming the core from a first photoresist layer and forming the shell from a second photoresist layer applied over the core. The core may be cross-linked to increase its stiffness.
摘要翻译：一种方法和结构。该结构包括：固体芯，其包括第一光致抗蚀剂材料，所述芯在基底上具有底表面，顶表面以及在顶表面和底表面之间的相对的第一和第二侧表面; 以及壳体，其包括第二光致抗蚀剂材料，所述壳体在所述基板的顶表面上，所述外壳包含通向所述基板的顶表面的空腔，所述外壳形成在所述顶表面上以及所述第一和第二侧表面壁上核心，核心完全填充空腔。核心比壳更僵硬。该方法包括：从第一光致抗蚀剂层形成芯并从施加在芯上的第二光致抗蚀剂层形成壳。芯可以交联以增加其刚度。

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