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1. 发明授权

US07261981B2 System and method of smoothing mask shapes for improved placement of sub-resolution assist features 失效
标题翻译：平滑掩模形状的系统和方法，以改进子分辨率辅助特征的放置
公开(公告)号：US07261981B2
公开(公告)日：2007-08-28
申请号：US10707778
申请日：2004-01-12
申请人： Mark A. Lavin , Lars W. Liebmann , Scott M. Mansfield , Maharaj Mukherjee , Zengqin Zhao
发明人： Mark A. Lavin , Lars W. Liebmann , Scott M. Mansfield , Maharaj Mukherjee , Zengqin Zhao
IPC分类号： G03F1/00
CPC分类号： G03F1/36
摘要： A method is disclosed for providing associated shapes of an optical lithography mask in relation to predetermined main shapes of the mask. The method includes generating simplified layout patterns from the predetermined main shapes of the mask. Such layout patterns are generated by eliminating detail of the main shapes which leads to unmanufacturable associated shapes while preserving geometrically relevant shape information. The associated shapes are then generated relative to the simplified mask patterns.
摘要翻译：公开了一种相对于掩模的预定主要形状提供光刻掩模的相关形状的方法。该方法包括从掩模的预定主要形状生成简化的布局图案。通过消除导致不可制造的相关形状的主要形状的细节来产生这种布局图案，同时保留几何相关的形状信息。然后相对于简化的掩模图案生成相关联的形状。

2. 发明授权

US07765021B2 Method to check model accuracy during wafer patterning simulation 失效
标题翻译：在晶圆图案模拟期间检查模型精度的方法
公开(公告)号：US07765021B2
公开(公告)日：2010-07-27
申请号：US12015077
申请日：2008-01-16
申请人： Scott M. Mansfield , Lars W. Liebmann , Mohamed Talbi
发明人： Scott M. Mansfield , Lars W. Liebmann , Mohamed Talbi
IPC分类号： G06F19/00 , G06F17/50 , G06K9/00
CPC分类号： G03F7/70508 , G03F1/36 , G03F1/68 , G03F7/705
摘要： A method, and computer program product and system for performing the method, is provided for designing a mask used in the manufacture of semiconductor integrated circuits, in which a model of the lithographic process is used during the mask design process. More particularly, the on-wafer process model is a function of optical image parameters that are calibrated using measurements from a test pattern. An uncertainty metric for the predicted response simulated by the on-wafer process model is computed for a given evaluation point of interest as a function of a distance metric between the collective optical image parameters simulated at the given evaluation point and the collective optical image parameters at the calibration data points. The uncertainty metric preferably is also a function of the sensitivity of the on-wafer process model response to changes in the optical image parameters.
摘要翻译：提供了一种用于执行该方法的方法和计算机程序产品和系统，用于设计在半导体集成电路的制造中使用的掩模，其中在掩模设计过程中使用光刻处理的模型。更具体地，在晶片上的工艺模型是使用来自测试图案的测量校准的光学图像参数的函数。对于给定的感兴趣评估点，计算由晶片上过程模型模拟的预测响应的不确定性度量，作为在给定评估点处模拟的总体光学图像参数与集体光学图像参数之间的距离度量的函数校准数据点。不确定性度量优选地也是晶片上工艺模型响应对光学图像参数变化的灵敏度的函数。

3. 发明申请

US20080127029A1 CLOSED-LOOP DESIGN FOR MANUFACTURABILITY PROCESS 失效
标题翻译：闭环设计用于制造工艺
公开(公告)号：US20080127029A1
公开(公告)日：2008-05-29
申请号：US11554904
申请日：2006-10-31
申请人： Ioana Graur , Geng Han , Scott M. Mansfield , Lars W. Liebmann
发明人： Ioana Graur , Geng Han , Scott M. Mansfield , Lars W. Liebmann
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A method of designing an integrated circuit is provided in which the design layout is optimized using a process model until the design constraints are satisfied by the image contours simulated by the process model. The process model used in the design phase need not be as accurate as the lithographic model used in preparing the lithographic mask layout during data prep. The resulting image contours are then included with the modified, optimized design layout to the data prep process, in which the mask layout is optimized using the lithographic process model, for example, including RET and OPC. The mask layout optimization matches the images simulated by the lithographic process model with the image contours generated during the design phase, which ensures that the design and manufacturability constraints specified by the designer are satisfied by the optimized mask layout.
摘要翻译：提供一种设计集成电路的方法，其中使用过程模型优化设计布局，直到由过程模型模拟的图像轮廓满足设计约束。在设计阶段使用的过程模型不需要与在数据准备期间制备光刻掩模布局时使用的光刻模型一样精确。然后将所得到的图像轮廓与经修改的优化的设计布局一起包括在数据准备过程中，其中使用光刻过程模型（例如包括RET和OPC）优化掩模布局。掩模布局优化将由光刻过程模型模拟的图像与在设计阶段生成的图像轮廓相匹配，从而确保设计人员指定的设计和可制造性约束被优化的掩模布局所满足。

4. 发明授权

US07266798B2 Designer's intent tolerance bands for proximity correction and checking 失效
标题翻译：设计师的意图容差带用于近距离校正和检查
公开(公告)号：US07266798B2
公开(公告)日：2007-09-04
申请号：US11163264
申请日：2005-10-12
申请人： Scott M. Mansfield , Lars W. Liebmann , Azalia Krasnoperova , Ioana Graur
发明人： Scott M. Mansfield , Lars W. Liebmann , Azalia Krasnoperova , Ioana Graur
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5081 , G03F1/36 , G06F2217/12 , Y02P90/265
摘要： A method of conveying the designer's intended electrical characteristics for a semiconductor design is provided by forming tolerance bands for a design layer of interest that take into consideration constraints from design layers that interact with and influence the features on the design layer of interest. The method determines regions, i.e. tolerance bands, within which the printed edges of features of the layer of interest will print within a predetermined criterion, and satisfy a variety of constraints, including, but not limited to, electrical, overlay and manufacturability constraints arising from the influence of features on other layers. The method may be implemented in a computer program product for execution on a computer system. The resulting tolerance bands can be used to efficiently convey the designer's intent to a lithographer, an OPC engineer or a mask manufacturer or tool.
摘要翻译：通过为感兴趣的设计层形成公差带来提供设计者用于半导体设计的预期电气特性的方法，其考虑到与感兴趣的设计层上的特征相互作用并影响其特征的设计层的约束。该方法确定区域，即公差带，其中感兴趣层的特征的打印边缘将在预定标准内打印，并且满足各种约束，包括但不限于电气，重叠和可制造性约束特征对其他层的影响。该方法可以在用于在计算机系统上执行的计算机程序产品中实现。所得到的公差带可用于有效传达设计人员对平版印刷机，OPC工程师或掩模制造商或工具的意图。

5. 发明授权

US06421820B1 Semiconductor device fabrication using a photomask with assist features 失效
标题翻译：使用具有辅助功能的光掩模的半导体器件制造
公开(公告)号：US06421820B1
公开(公告)日：2002-07-16
申请号：US09460034
申请日：1999-12-13
申请人： Scott M. Mansfield , Lars W. Liebmann , Shahid Butt , Henning Haffner
发明人： Scott M. Mansfield , Lars W. Liebmann , Shahid Butt , Henning Haffner
IPC分类号： G06F1750
CPC分类号： G03F1/36 , G03F7/70441
摘要： A semiconductor device can be fabricated using a photomask that has been modified using an assist feature design method (see e.g., FIG. 4A) based on normalized feature spacing. Before the device can be fabricated, a layout of original shapes is designed (402). For at least some of the original shapes, the width of the shape and a distance to at least one neighboring shape are measured (404). A modified shape can then be generated by moving edges of the original shape based on the width and distance measurements (406). This modification can be performed on some or all of the original shapes (408). For each of the modified shapes, a normalized space and correct number of assist features can be computed (410). The layout is then modified by adding the correct number of assist features in a space between the modified shape and the neighboring shape (412). This modified layout can then be used in producing a photomask, which can in turn be used to produce a semiconductor device.
摘要翻译：可以使用已经基于归一化特征间隔使用辅助特征设计方法（参见例如图4A）修改的光掩模来制造半导体器件。在可以制造设备之前，设计原始形状的布局（402）。对于至少一些原始形状，测量形状的宽度和至少一个相邻形状的距离（404）。然后可以通过基于宽度和距离测量来移动原始形状的边缘来生成修改的形状（406）。可以对部分或全部原始形状执行该修改（408）。对于每个修改的形状，可以计算归一化空间和正确数量的辅助特征（410）。然后通过在修改的形状和相邻形状之间的空间中添加正确数量的辅助特征来修改布局（412）。然后，该修改后的布局可用于制造光掩模，光掩模又可用于制造半导体器件。

6. 发明授权

US06413683B1 Method for incorporating sub resolution assist features in a photomask layout 有权
标题翻译：在光掩模布局中引入子分辨率辅助功能的方法
公开(公告)号：US06413683B1
公开(公告)日：2002-07-02
申请号：US09602966
申请日：2000-06-23
申请人： Lars W. Liebmann , Scott M. Mansfield
发明人： Lars W. Liebmann , Scott M. Mansfield
IPC分类号： G03F900
CPC分类号： G03F1/36
摘要： A method for developing a photomask layout by which an electrical circuit is imaged that includes introducing sub resolution assist features into a photomask layout by (1) sorting selected details of the main electrical circuit undergoing enhancement according to a predetermined order of importance of enhancement of the selected details of the main electrical circuit to the overall performance of the main electrical circuit, (2) establishing a prioritization for sub resolution assist features associated with the selected details of the main electrical circuit based on the predetermined order of importance of the selected details of the main electrical circuit with which the sub resolution assist features are associated, and (3) incorporating sub resolution assist features in the photomask layout in accordance with the established prioritization of the sub resolution features.
摘要翻译：一种用于开发光掩模布局的方法，通过该方法，电路被成像，其包括通过以下方式将子分辨率辅助特征引入到光掩模布局中：（1）根据预先确定的增强重要性顺序对经历增强的主电路的选定细节进行排序选择主电路的细节到主电路的总体性能，（2）基于所选择的细节的预定重要性顺序，建立与主电路的选定细节相关联的子分辨率辅助特征的优先级与子分辨率辅助特征相关联的主电路，以及（3）根据子分辨率特征的确定的优先级，在光掩模布局中并入子分辨率辅助特征。

7. 发明授权

US07650587B2 Local coloring for hierarchical OPC 失效
标题翻译：分层OPC的局部着色
公开(公告)号：US07650587B2
公开(公告)日：2010-01-19
申请号：US11564957
申请日：2006-11-30
申请人： Zachary Baum , Ioana Graur , Lars W. Liebmann , Scott M. Mansfield
发明人： Zachary Baum , Ioana Graur , Lars W. Liebmann , Scott M. Mansfield
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A method for designing a mask for fabricating an integrated circuit is provided wherein a mask layout that requires coloring, such as for alternating phase shift, double-exposure and double-exposure-etch masks, is organized into uncolored hierarchical design units. Prior to modification by OPC, each hierarchical design unit is locally colored. OPC is then performed on the locally colored hierarchical design unit. The local coloring information for the hierarchically arranged OPC-modified design unit may be discarded. After OPC modification, the uncolored OPC-modified design units may be placed within the mask layout, and the flattened data may be colored. Thus, turnaround time for mask design is significantly improved since the numerically intensive OPC is performed on the hierarchical data, avoiding the need to perform OPC on flattened data, whereas the less intensive global coloring is performed on flattened data.
摘要翻译：提供了一种用于设计用于制造集成电路的掩模的方法，其中需要诸如用于交替相移，双曝光和双曝光蚀刻掩模的着色的掩模布局被组织成无色层级设计单元。在OPC修改之前，每个分层设计单元都是局部有色的。然后在本地着色的分层设计单元上执行OPC。可以丢弃用于分层布置的OPC修改的设计单元的局部着色信息。在OPC修改之后，未着色的OPC修改的设计单元可以放置在掩模布局内，并且扁平化的数据可能被着色。因此，掩模设计的周转时间显着提高，因为对分层数据执行数字密集的OPC，避免了对平坦化数据执行OPC的需要，而对扁平化数据执行的密集型全局着色较少。

8. 发明申请

US20090182448A1 METHOD TO CHECK MODEL ACCURACY DURING WAFER PATTERNING SIMULATION 失效
标题翻译：在WAFER模式中检查模型精度的方法
公开(公告)号：US20090182448A1
公开(公告)日：2009-07-16
申请号：US12015077
申请日：2008-01-16
申请人： Scott M. Mansfield , Lars W. Liebmann , Mohamed Talbi
发明人： Scott M. Mansfield , Lars W. Liebmann , Mohamed Talbi
IPC分类号： G06F17/00
CPC分类号： G03F7/70508 , G03F1/36 , G03F1/68 , G03F7/705
摘要： A method, and computer program product and system for performing the method, is provided for designing a mask used in the manufacture of semiconductor integrated circuits, in which a model of the lithographic process is used during the mask design process. More particularly, the on-wafer process model is a function of optical image parameters that are calibrated using measurements from a test pattern. An uncertainty metric for the predicted response simulated by the on-wafer process model is computed for a given evaluation point of interest as a function of a distance metric between the collective optical image parameters simulated at the given evaluation point and the collective optical image parameters at the calibration data points. The uncertainty metric preferably is also a function of the sensitivity of the on-wafer process model response to changes in the optical image parameters.
摘要翻译：提供了一种用于执行该方法的方法和计算机程序产品和系统，用于设计在半导体集成电路的制造中使用的掩模，其中在掩模设计过程中使用光刻处理的模型。更具体地，在晶片上的工艺模型是使用来自测试图案的测量校准的光学图像参数的函数。对于给定的感兴趣评估点，计算由晶片上过程模型模拟的预测响应的不确定性度量，作为在给定评估点处模拟的总体光学图像参数与集体光学图像参数之间的距离度量的函数校准数据点。不确定性度量优选地也是晶片上工艺模型响应对光学图像参数变化的灵敏度的函数。

9. 发明授权

US5932377A Exact transmission balanced alternating phase-shifting mask for photolithography 失效
标题翻译：用于光刻的精确传输平衡交替移相掩模
公开(公告)号：US5932377A
公开(公告)日：1999-08-03
申请号：US28833
申请日：1998-02-24
申请人： Richard A. Ferguson , Lars W. Liebmann , Scott M. Mansfield , David S. O'Grady , Alfred K. Wong
发明人： Richard A. Ferguson , Lars W. Liebmann , Scott M. Mansfield , David S. O'Grady , Alfred K. Wong
IPC分类号： G03F1/30 , G03F9/00
CPC分类号： G03F1/30
摘要： A two-step method for eliminating transmission errors in alternating phase-shifting masks is described. Initially, the design data is selectively biased to provide a coarse reduction in the inherent transmission error between features of different phase, size, shape, and/or location. During fabrication of the mask with the modified data, residual transmission errors are then eliminated via the positioning of the edges of the etched-quartz trenches which define the phase of a given feature to a set location beneath the opaque chrome film. Application of feedback, in which the aerial image of the mask is monitored during the positioning of the etched-quartz edges, provides additional and precise control of the residual transmission error.
摘要翻译：描述了用于消除交替移相掩模中的传输误差的两步法。最初，设计数据被选择性地偏置以提供不同相位，大小，形状和/或位置的特征之间的固有传输误差的粗略减小。在具有修改数据的掩模制造期间，通过将限定给定特征的相位的蚀刻石英沟槽的边缘定位到不透明铬膜下方的设定位置，残留透射误差被消除。在蚀刻石英边缘的定位期间监测掩模的空中图像的反馈的应用提供对残留传输误差的附加且精确的控制。

10. 发明授权

US07607114B2 Designer's intent tolerance bands for proximity correction and checking 失效
标题翻译：设计师的意图容差带用于近距离校正和检查
公开(公告)号：US07607114B2
公开(公告)日：2009-10-20
申请号：US11778302
申请日：2007-07-16
申请人： Scott M. Mansfield , Lars W. Liebmann , Azalia Krasnoperova , Ioana Graur
发明人： Scott M. Mansfield , Lars W. Liebmann , Azalia Krasnoperova , Ioana Graur
IPC分类号： G06F17/50 , G06F9/45 , G06F9/455
CPC分类号： G06F17/5081 , G03F1/36 , G06F2217/12 , Y02P90/265
摘要： A method of conveying the designer's intended electrical characteristics for a semiconductor design is provided by forming tolerance bands for a design layer of interest that take into consideration constraints from design layers that interact with and influence the features on the design layer of interest. The method determines regions, i.e. tolerance bands, within which the printed edges of features of the layer of interest will print within a predetermined criterion, and satisfy a variety of constraints, including, but not limited to, electrical, overlay and manufacturability constraints arising from the influence of features on other layers. The method may be implemented in a computer program product for execution on a computer system. The resulting tolerance bands can be used to efficiently convey the designer's intent to a lithographer, an OPC engineer or a mask manufacturer or tool.
摘要翻译：通过为感兴趣的设计层形成公差带来提供设计者用于半导体设计的预期电气特性的方法，其考虑到与感兴趣的设计层上的特征相互作用并影响其特征的设计层的约束。该方法确定区域，即公差带，其中感兴趣层的特征的打印边缘将在预定标准内打印，并且满足各种约束，包括但不限于电气，重叠和可制造性约束特征对其他层的影响。该方法可以在用于在计算机系统上执行的计算机程序产品中实现。所得到的公差带可用于有效传达设计人员对平版印刷机，OPC工程师或掩模制造商或工具的意图。

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