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1. 发明申请

US20120167029A1 PHYSICAL DESIGN SYSTEM AND METHOD 失效
标题翻译：物理设计系统与方法
公开(公告)号：US20120167029A1
公开(公告)日：2012-06-28
申请号：US13413759
申请日：2012-03-07
申请人： John M. Cohn , James A. Culp , Ulrich A. Finkler , Fook-Luen Heng , Mark A. Lavin , Jin Fuw Lee , Lars W. Liebmann , Gregory A. Northrop , Nakgeuon Seong , Rama N. Singh , Leon Stok , Pieter J. Woltgens
发明人： John M. Cohn , James A. Culp , Ulrich A. Finkler , Fook-Luen Heng , Mark A. Lavin , Jin Fuw Lee , Lars W. Liebmann , Gregory A. Northrop , Nakgeuon Seong , Rama N. Singh , Leon Stok , Pieter J. Woltgens
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5009 , G06F17/5072
摘要： A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.
摘要翻译：一种用于设计复杂集成电路（IC）的设计系统，一种IC设计方法和程序产品。布局单元接收表示网格和字形格式的部分的电路描述。检查单元检查设计的网格和字形部分。精心设计单元从检查的设计生成目标布局。数据准备单元准备掩模制作的目标布局。模式高速缓存单元用先前缓存的结果有选择地替换设计的部分，以提高设计效率。

2. 发明授权

US07536664B2 Physical design system and method 失效
标题翻译：物理设计系统及方法
公开(公告)号：US07536664B2
公开(公告)日：2009-05-19
申请号：US10917193
申请日：2004-08-12
申请人： John M. Cohn , James A. Culp , Ulrich A. Finkler , Fook-Luen Heng , Mark A. Lavin , Jin Fuw Lee , Lars W. Liebmann , Gregory A. Northrop , Nakgeuon Seong , Rama N. Singh , Leon Stok , Pieter J. Woltgens
发明人： John M. Cohn , James A. Culp , Ulrich A. Finkler , Fook-Luen Heng , Mark A. Lavin , Jin Fuw Lee , Lars W. Liebmann , Gregory A. Northrop , Nakgeuon Seong , Rama N. Singh , Leon Stok , Pieter J. Woltgens
IPC分类号： G06F17/50 , G06F19/00
CPC分类号： G06F17/5081 , G06F17/5009 , G06F17/5072
摘要： A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.
摘要翻译：一种用于设计复杂集成电路（IC）的设计系统，一种IC设计方法和程序产品。布局单元接收表示网格和字形格式的部分的电路描述。检查单元检查设计的网格和字形部分。精心设计单元从检查的设计生成目标布局。数据准备单元准备掩模制作的目标布局。模式高速缓存单元用先前缓存的结果有选择地替换设计的部分，以提高设计效率。

3. 发明申请

US20080077889A1 PARAMETERIZED SEMICONDUCTOR CHIP CELLS AND OPTIMIZATION OF THE SAME 审中-公开
标题翻译：参数化半导体芯片细胞及其优化
公开(公告)号：US20080077889A1
公开(公告)日：2008-03-27
申请号：US11533814
申请日：2006-09-21
申请人： Erwin Behnen , Gregory A. Northrop , James D. Warnock , Dieter Wendel , Pieter Joseph Woeltgens
发明人： Erwin Behnen , Gregory A. Northrop , James D. Warnock , Dieter Wendel , Pieter Joseph Woeltgens
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A method is provided for designing an integrated circuit utilizing an arrangement of at least one library cell having a plurality of parameterized input connection points disposed along a rod, a plurality of parameterized output connection points disposed along a wire and a cell structure to which the rod and wire are electrically connected; routing and making input and output connections to the library cells at the parameterized input connection points and the parameterized output connection points to satisfy design specifications of the integrated circuit. After determining which parameterized input connection points and parameterized output connection points are unused, the unused parameterized input connection points and parameterized output connection points are removed from each library cell of the integrated circuit design.
摘要翻译：提供了一种利用至少一个库单元的布置来设计集成电路的方法，所述库单元具有沿着杆布置的多个参数化的输入连接点，沿着导线设置的多个参数化的输出连接点以及单元结构，所述杆电线电连接; 在参数化的输入连接点和参数化的输出连接点上路由并输入到库单元的输入和输出连接，以满足集成电路的设计规范。在确定哪些参数化输入连接点和参数化输出连接点未使用之后，将从集成电路设计的每个库单元中删除未使用的参数化输入连接点和参数化输出连接点。

4. 发明授权

US07082595B1 Schematic driven placement method and program product for custom VLSI circuit design 失效
标题翻译：用于定制VLSI电路设计的示意图驱动放置方法和程序产品
公开(公告)号：US07082595B1
公开(公告)日：2006-07-25
申请号：US11055905
申请日：2005-02-11
申请人： Yiu-Hing Chan , Jonathan Chu , George D. Gristede , Gregory A. Northrop
发明人： Yiu-Hing Chan , Jonathan Chu , George D. Gristede , Gregory A. Northrop
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A physical device layout tool and method. The method and tool receive a user provided schematic with circuit data and placement parameters, including defaults. Further inputs include a definition of cell physical position in the horizontal direction, a definition of the cell's vertical stacking level, a definition of the cell orientation, a specification of vertical alignment of multiple cell instances, and a definition of vertical spacing between 2 adjacent cell instances. These input parameters are used to generate a layout with the placed circuit elements.
摘要翻译：物理设备布局工具和方法。该方法和工具接收用户提供的原理图，包括电路数据和放置参数，包括默认值。进一步的输入包括水平方向上的细胞物理位置的定义，细胞的垂直堆叠层的定义，细胞取向的定义，多个细胞实例的垂直对准的规范以及两个相邻细胞之间的垂直间距的定义实例。这些输入参数用于生成具有放置的电路元件的布局。

5. 发明授权

US06966046B2 CMOS tapered gate and synthesis method 失效
标题翻译： CMOS锥形栅极及其合成方法
公开(公告)号：US06966046B2
公开(公告)日：2005-11-15
申请号：US09841505
申请日：2001-04-24
申请人： Brian W. Curran , Lisa Bryant Lacey , Gregory A. Northrop , Ruchir Puri , Leon Stok
发明人： Brian W. Curran , Lisa Bryant Lacey , Gregory A. Northrop , Ruchir Puri , Leon Stok
IPC分类号： G06F17/50 , H01L21/82 , H03K19/096 , H03K19/20
CPC分类号： G06F17/505
摘要： A high-performance gate library is augmented with tapered gates. The widths of the stacked devices are varied to reduce the delay through some of the input pins. For example in a tapered NAND gate the bottom devices in the NFET stack are have longer widths than the top device to achieve smaller top input to output pin delay at the expense of larger bottom input to output pin delay. The method of using synthesis algorithms modifies the input net to gate pin connections and swaps traditional non-tapered gates with tapered gates to improve the delay of the timing critical paths. The latest arriving gate input net is swapped with the net connected to the top pin. The gate is then converted to a tapered gate provided the paths through the bottom gate input(s) that are not timing critical.
摘要翻译：高性能门库增加了锥形门。改变堆叠器件的宽度以减少通过一些输入引脚的延迟。例如在锥形NAND门中，NFET堆叠中的底部器件具有比顶部器件更宽的宽度，以牺牲较大的底部输入到输出引脚延迟为代价来实现较小的顶部输入以输出引脚延迟。使用合成算法的方法将输入网络修改为栅极引脚连接，并与锥形栅极交换传统的非锥形栅极，以改善时序关键路径的延迟。最新到达的门输入网络被互换，网络连接到顶针。然后将栅极转换成锥形栅极，提供通过底栅输入（不是时序关键）的路径。

6. 发明授权

US07093208B2 Method for tuning a digital design for synthesized random logic circuit macros in a continuous design space with optional insertion of multiple threshold voltage devices 失效
标题翻译：用于在连续设计空间中调整合成随机逻辑电路宏的数字设计的方法，并可选择插入多个阈值电压器件
公开(公告)号：US07093208B2
公开(公告)日：2006-08-15
申请号：US10842589
申请日：2004-05-10
申请人： Patrick M. Williams , Ee K. Cho , David J. Hathaway , Mei-Ting Hsu , Lawrence K. Lange , Gregory A. Northrop , Chandramouli Visweswariah , Cindy ShuiKing Washburn , Jun Zhou
发明人： Patrick M. Williams , Ee K. Cho , David J. Hathaway , Mei-Ting Hsu , Lawrence K. Lange , Gregory A. Northrop , Chandramouli Visweswariah , Cindy ShuiKing Washburn , Jun Zhou
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A Digital Design Method which may be automated is for obtaining timing closure in the design of large, complex, high-performance digital integrated circuits. The methodincludes the use of a tuner on random logic macros that adjusts transistor sizes in a continuous domain. To accommodate this tuning, logic gates are mapped to parameterized cells for the tuning and then back to fixed gates after the tuning. Tuning is constrained in such a way as to minimize “binning errors” when the design is mapped back to fixed cells. Further, the critical sections of the circuit are marked in order to make the optimization more effective and to fit within the problem-size constraints of the tuner. A specially formulated objective function is employed during the tuning to promote faster global timing convergence, despite possibly incorrect initial timing budgets. The specially formulated objective function targets all paths that are failing timing, with appropriate weighting, rather than just targeting the most critical path. Finally, the addition of multiple threshold voltage gates allows for increased performance while limiting leakage power.
摘要翻译：可以自动化的数字设计方法是在大型，复杂，高性能数字集成电路的设计中获得定时关闭。该方法包括在随机逻辑宏中使用调谐器来调整连续域中的晶体管尺寸。为了适应这种调谐，逻辑门被映射到用于调谐的参数化单元，然后在调谐之后返回到固定门。调整受限于将设计映射回固定单元格时最小化“合并错误”。此外，电路的关键部分被标记以便使优化更有效并且适应调谐器的问题尺寸约束。在调整期间采用了特别制定的目标函数，以促进更快的全局时序收敛，尽管可能不正确的初始时间预算。特别制定的目标函数针对所有失败时机的路径，以适当的权重，而不是仅针对最关键的路径。最后，添加多个阈值电压门允许提高性能，同时限制漏电功率。

7. 发明授权

US08473885B2 Physical design system and method 失效
公开(公告)号：US08473885B2
公开(公告)日：2013-06-25
申请号：US13413759
申请日：2012-03-07
申请人： John M. Cohn , James A. Culp , Ulrich A. Finkler , Fook-Luen Heng , Mark A. Lavin , Jin Fuw Lee , Lars W. Liebmann , Gregory A. Northrop , Nakgeuon Seong , Rama N. Singh , Leon Stok , Pieter J. Woeltgens
发明人： John M. Cohn , James A. Culp , Ulrich A. Finkler , Fook-Luen Heng , Mark A. Lavin , Jin Fuw Lee , Lars W. Liebmann , Gregory A. Northrop , Nakgeuon Seong , Rama N. Singh , Leon Stok , Pieter J. Woeltgens
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5009 , G06F17/5072
摘要： A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.

8. 发明授权

US08219943B2 Physical design system and method 有权
标题翻译：物理设计系统及方法
公开(公告)号：US08219943B2
公开(公告)日：2012-07-10
申请号：US12425603
申请日：2009-04-17
申请人： John M Cohn , James A. Culp , Ulrich A. Finkler , Fook-Luen Heng , Mark A. Lavin , Jin Fuw Lee , Lars W. Liebmann , Gregory A. Northrop , Nakgeuon Seong , Rama N. Singh , Leon Stok , Pieter J. Woeltgens
发明人： John M Cohn , James A. Culp , Ulrich A. Finkler , Fook-Luen Heng , Mark A. Lavin , Jin Fuw Lee , Lars W. Liebmann , Gregory A. Northrop , Nakgeuon Seong , Rama N. Singh , Leon Stok , Pieter J. Woeltgens
IPC分类号： G06F17/50 , G06F19/00 , G03F1/00 , G21K5/00
CPC分类号： G06F17/5081 , G06F17/5009 , G06F17/5072
摘要： A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.
摘要翻译：一种用于设计复杂集成电路（IC）的设计系统，一种IC设计方法和程序产品。布局单元接收表示网格和字形格式的部分的电路描述。检查单元检查设计的网格和字形部分。精心设计单元从检查的设计生成目标布局。数据准备单元准备掩模制作的目标布局。模式高速缓存单元用先前缓存的结果有选择地替换设计的部分，以提高设计效率。

9. 发明授权

US07900178B2 Integrated circuit (IC) design method, system and program product 有权
标题翻译：集成电路（IC）设计方法，系统和程序产品
公开(公告)号：US07900178B2
公开(公告)日：2011-03-01
申请号：US12039109
申请日：2008-02-28
申请人： James A. Culp , Gregory A. Northrop , Ming Yin
发明人： James A. Culp , Gregory A. Northrop , Ming Yin
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method of integrated circuit (IC) design, an IC design system and computer program product therefore, e.g., for L3GO designs. Special case cells are cells that represent specialized, process dependent components and are provided as dual representation cells with an internal view and external view. The external view is high level abstract representation that includes access pins, boundary and possible blocking shapes/layers and optionally, parameterizations. Each external view includes cell to cell spacing rules and connecting and blocking/keepout rules for placement and routing. The internal representation or, internal view includes regular shapes forming cell components and defining cell construction details and are ground rule clean by construction or verified by simulation or hardware.
摘要翻译：因此，集成电路（IC）设计的方法，IC设计系统和计算机程序产品，例如用于L3GO设计。特殊情况单元是表示专门的，与过程相关的组件的单元，并且作为具有内部视图和外部视图的双重表示单元提供。外部视图是高级抽象表示，包括访问引脚，边界和可能的阻塞形状/层以及可选的参数化。每个外部视图包括单元格到单元格间距规则以及用于布局和布线的连接和阻止/保留规则。内部表示或内部视图包括形成细胞组分的规则形状，并定义细胞结构细节，并通过构造进行基础规则清洁或通过模拟或硬件验证。

10. 发明申请

US20090204930A1 IPHYSICAL DESIGN SYSTEM AND METHOD 有权
标题翻译：物理设计系统与方法
公开(公告)号：US20090204930A1
公开(公告)日：2009-08-13
申请号：US12425603
申请日：2009-04-17
申请人： John M. Cohn , James A. Culp , Ulrich A. Finkler , Fook-Luen Heng , Mark A. Lavin , Jin Fuw Lee , Lars W. Liebmann , Gregory A. Northrop , Nakgeuon Seong , Rama N. Singh , Leon Stok , Pieter J. Woltgens
发明人： John M. Cohn , James A. Culp , Ulrich A. Finkler , Fook-Luen Heng , Mark A. Lavin , Jin Fuw Lee , Lars W. Liebmann , Gregory A. Northrop , Nakgeuon Seong , Rama N. Singh , Leon Stok , Pieter J. Woltgens
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5009 , G06F17/5072
摘要： A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.
摘要翻译：一种用于设计复杂集成电路（IC）的设计系统，一种IC设计方法和程序产品。布局单元接收表示网格和字形格式的部分的电路描述。检查单元检查设计的网格和字形部分。精心设计单元从检查的设计生成目标布局。数据准备单元准备掩模制作的目标布局。模式高速缓存单元用先前缓存的结果有选择地替换设计的部分，以提高设计效率。

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