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    • 1. 发明授权
    • Data processing apparatus with indirect register file access
    • 具有间接寄存器文件访问的数据处理设备
    • US06754809B1
    • 2004-06-22
    • US09713442
    • 2000-11-15
    • Karl M. GuttagDavid HoyleKeith Balmer
    • Karl M. GuttagDavid HoyleKeith Balmer
    • G06F934
    • G06F9/3012G06F9/3004G06F9/30098G06F9/35G06F9/383
    • A data processing apparatus which uses a register file to provide a faster alternative to indirect memory addressing. A functional unit is connected to a data register file (76) which comprises a plurality of registers, each of which is accessed by a corresponding register number. The functional unit (e.g., A-unit 78) can execute at least one indirect register access instruction that comprises an operand register number field. Instruction decode circuitry, connected to the register file and the functional unit, is responsive to the indirect register access instruction to recall data stored in an operand register (190) specified by the operand register number in the instruction, identify the recalled data as a register access number, and recall operand data from a data register corresponding to the register access number for use as an operand by the functional unit. Indirect register addressing permits the apparatus to more quickly execute table look up intensive algorithms, such as variable length decoding, than an apparatus employing only indirect memory addressing.
    • 一种使用寄存器文件来提供间接存储器寻址的更快替代的数据处理装置。 功能单元连接到数据寄存器文件(76),数据寄存器文件(76)包括多个寄存器,每个寄存器都由对应的寄存器号码访问。 功能单元(例如,A单元78)可以执行包括操作数寄存器号字段的至少一个间接寄存器访问指令。 连接到寄存器文件和功能单元的指令解码电路响应于间接寄存器访问指令来调用存储在指令中由操作数寄存器号指定的操作数寄存器(190)中的数据,将调用的数据标识为寄存器 访问号码,并且从与寄存器访问号相对应的数据寄存器中调用操作数数据,以用作功能单元的操作数。 间接寄存器寻址允许装置比仅使用间接存储器寻址的装置更快速地执行表查找密集型算法,例如可变长度解码。
    • 2. 发明授权
    • Data processor with flexible multiply unit
    • 数据处理器具有灵活的乘法单元
    • US06711602B1
    • 2004-03-23
    • US09703093
    • 2000-10-31
    • Amarjit Singh BhandalKeith BalmerDavid HoyleKarl M. GuttagZahid Hussain
    • Amarjit Singh BhandalKeith BalmerDavid HoyleKarl M. GuttagZahid Hussain
    • G06F752
    • G06F9/30014G06F9/3853
    • An embodiment of the invention includes a pair of parallel 16×16 multipliers each with two 32-bit inputs and one 32-bit output. There are options to allow input halfword and byte selection for four independent 8×8 or two independent 16×16 multiplications, real and imaginary parts of comple×multiplication, pairs of partial sums for 32×32 multiplication, and partial sums for 16×32 multiplication. There are options to allow internal hardwired routing of each multiplier unit results to achieve partial-sum shifting as required to support above options. There is a redundant digit arithmetic adder before final outputs to support additions for partial sum accumulation, complex multiplication vector accumulation and general accumulation for FIRs/IIRs—giving MAC unit functionality. There are options controlled using bit fields in a control register passed to the multiplier unit as an operand. There are also options to generate all of the products needed for complex multiplication.
    • 本发明的实施例包括一对并行的16×16乘法器,每个乘法器具有两个32位输入和一个32位输出。 有四种独立的8x8或两个独立的16x16乘法输入半字和字节选择的选项,复乘的实部和虚部,32x32乘法的部分和对,以及16x32乘法的部分和。 有一些选项允许每个乘法器单元的内部连线布线结果实现部分和位移动,以支持上述选项。 在最终输出之前有一个冗余数字运算加法器,以支持部分和累加的加法,复数乘法向量累加和FIR / IIR的一般累加 - 提供MAC单元功能。 使用控制寄存器中的位域作为操作数传递给乘法器单元进行控制的选项。 还可以选择生成复杂乘法所需的所有产品。
    • 6. 发明申请
    • TRANSMISSION
    • 传输
    • US20070111838A1
    • 2007-05-17
    • US11551163
    • 2006-10-19
    • Simon EvansDavid Hoyle
    • Simon EvansDavid Hoyle
    • F16H3/72
    • F16H3/725B60K1/02B60K6/365B60K6/405B60K6/442B60K6/445Y02T10/6234Y02T10/6239
    • A transmission including a first input member which in use is rotatably driven by a first prime mover, a second input member which in use is rotatably driven by a second prime mover, a rotatable output member from which drive is provided to a driven structure, the first input member driving a driven member and there being a drivable member drivable by the second input member, the driven member and the drivable member being coupled though an intermediate structure which carries the output member, drive being transmitted from the first input member to the output member when torque is input to the second input member from the second prime mover, and wherein the second prime mover is an electrically driven switched reluctance motor.
    • 一种变速器,包括在使用中由第一原动机旋转地驱动的第一输入构件,在使用中的第二输入构件由第二原动机可旋转地驱动,可旋转的输出构件,驱动装置从驱动结构提供, 第一输入构件驱动从动构件,并且存在可由第二输入构件驱动的可驱动构件,从动构件和可驱动构件通过承载输出构件的中间结构联接,驱动从第一输入构件传递到输出 当所述第二原动机的扭矩从所述第二输入构件输入时,所述第二原动机是电驱动的开关磁阻电动机。
    • 8. 发明授权
    • Dipole logging tool
    • 偶极测井工具
    • US06474439B1
    • 2002-11-05
    • US09537836
    • 2000-03-29
    • David HoyleHitoshi TashiroBenoit FroelichAlain BrieHiroshi HoriHitoshi SugiyamaJahir PabonFrank Morris
    • David HoyleHitoshi TashiroBenoit FroelichAlain BrieHiroshi HoriHitoshi SugiyamaJahir PabonFrank Morris
    • G01V140
    • G01V1/52
    • A logging tool having a tool body, which can be positioned in a fluid-filled borehole, including a receiver section and a dipole transmitter; wherein the dipole transmitter includes a transducer with a shell having a reaction mass and a motor located therein, the motor operatively connecting the shell and the reaction mass such that only an outer surface of the shell is in contact with the fluid in the borehole. This new type of dipole source for well logging involves shaking all or part (axially) of a dipole tool body to produce a pure, broadband acoustic dipole signal while at the same time coupling as little energy as possible into the tool body. Important variations on this idea include a linear phased array of shaker sources, and active cancellation of tool borne noise.
    • 一种具有工具主体的测井工具,该工具主体可定位在充满流体的钻孔中,包括接收器部分和偶极发射器; 其中所述偶极发射器包括具有壳体的换能器,所述壳体具有反作用物质和位于其中的马达,所述马达可操作地连接所述壳体和所述反作用物质,使得只有所述壳体的外表面与所述钻孔中的流体接触。 这种用于测井的新型偶极子源涉及摇动偶极工具体的全部或部分(轴向),以产生纯的宽带声偶极子信号,同时将尽可能少的能量耦合到工具主体中。 这个想法的重要变化包括振荡器源的线性相控阵列,以及主动消除工具噪声。
    • 10. 发明授权
    • Microprocessor with non-aligned scaled and unscaled addressing
    • 具有非对齐缩放和非缩放寻址的微处理器
    • US06574724B1
    • 2003-06-03
    • US09702474
    • 2000-10-31
    • David HoyleJoseph R. ZbiciakJeremiah E. Golston
    • David HoyleJoseph R. ZbiciakJeremiah E. Golston
    • G06F1200
    • G06F9/3828G06F9/30181G06F9/3555
    • A data processing system having a central processing (CPU) unit and a method of operation is provided. The CPU has an instruction set architecture that is optimized for intensive numeric algorithm processing. The CPU has dual load/store units connected to dual memory target ports of a memory controller. The CPU can execute two aligned data transfers each having a length of one byte, two bytes, four bytes, or eight bytes in parallel by executing two load/store instructions. The CPU can also execute a single non-aligned data transfer having a length of four bytes or eight bytes by executing a non-aligned load/store instruction that utilizes both memory target ports. A data transfer address for each load/store instruction is formed by fetching the instruction, decoding the instruction to determine instruction type, transfer data size, and scaling selection, selectively scaling an offset provided by the instruction and combining the selectively scaled offset with a base address value. The resultant address is then provided to the memory system to initiate a data transfer.
    • 提供具有中央处理(CPU)单元和操作方法的数据处理系统。 CPU具有针对密集数值算法处理进行了优化的指令集体系结构。 CPU具有连接到存储器控制器的双存储器目标端口的双重加载/存储单元。 CPU可以通过执行两个加载/存储指令来并行执行两个对齐的数据传输,每个数据传输具有一个字节,两个字节,四个字节或八个字节的长度。 CPU还可以通过执行利用两个存储器目标端口的不对齐的加载/存储指令来执行长度为四字节或八字节的单个非对齐数据传输。 每个加载/存储指令的数据传输地址通过取指令,解码指令来确定指令类型,传输数据大小和缩放选择来形成,选择性地缩放由指令提供的偏移量,并将选择性缩放的偏移量与基数 地址值。 然后将结果地址提供给存储器系统以发起数据传送。