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1. 发明授权

US06948050B1 Single integrated circuit embodying a dual heterogenous processors with separate instruction handling hardware 失效
标题翻译：单一集成电路体现了具有单独指令处理硬件的双异质处理器
公开(公告)号：US06948050B1
公开(公告)日：2005-09-20
申请号：US09875136
申请日：2001-06-06
申请人： Robert J. Gove , Keith Balmer , Nicholas Kerin Ing-Simmons , Karl Marion Guttag
发明人： Robert J. Gove , Keith Balmer , Nicholas Kerin Ing-Simmons , Karl Marion Guttag
IPC分类号： G06F9/38 , G06F15/16 , G06F15/173
CPC分类号： G06F9/3885 , G06F9/3851 , G06F15/17375
摘要： A single integrated circuit includes first and second data processors operating on different instruction sets independently operating on disjoint programs and data. The single integrated circuit preferably includes an external interface, a shared data transfer controller and shared memory divided into plural independently accessible memory banks. The two data processors are preferably a digital signal processor (DSP) and a reduced instruction set computer (RISC) processor. The DSP and RISC processors are suitably programmed to perform differing aspects of computer image processing.
摘要翻译：单个集成电路包括在不相交的程序和数据上独立操作的不同指令集上操作的第一和第二数据处理器。单个集成电路优选地包括外部接口，共享数据传输控制器和被分成多个可独立存取的存储体的共享存储器。两个数据处理器优选地是数字信号处理器（DSP）和精简指令集计算机（RISC）处理器。 DSP和RISC处理器被适当地编程以执行计算机图像处理的不同方面。

2. 发明授权

US06173394B2 Instruction having bit field designating status bits protected from modification corresponding to arithmetic logic unit result 有权
标题翻译：具有位字段指定状态位的指令不受与算术逻辑单元结果相对应的修改
公开(公告)号：US06173394B2
公开(公告)日：2001-01-09
申请号：US09372470
申请日：1999-08-11
申请人： Karl M. Guttag , Sydney W. Poland , Keith Balmer
发明人： Karl M. Guttag , Sydney W. Poland , Keith Balmer
IPC分类号： G06F9308
CPC分类号： G06F9/30101 , G06F9/30014 , G06F9/30036 , G06F9/30043 , G06F9/30094 , G06F9/30167 , G06F9/30189 , G06F9/30192 , G06F9/34 , G06F9/3842
摘要： A data processing apparatus includes plural data registers, an arithmetic logic unit and a status register. The status register stores a plurality of different types of status bits. These status bits could be a negative status bit, a carry status bit, an overflow status bit and a zero status bit. These status bits are normally set dependent upon the condition of the result generated by the current arithmetic logic unit operation. A status bit protect instruction type permits selection of status bits protected from modification corresponding to the current arithmetic logic unit result. This status bit protect instruction preferably includes individual protect bit corresponding to each status bit. If a protect bit has a first digital state, then the corresponding status bit may be modified corresponding to the current arithmetic logic unit result. If the protect bit has a second opposite digital state, then the corresponding status bit is protected from modification according to the arithmetic logic unit results.
摘要翻译：数据处理装置包括多个数据寄存器，算术逻辑单元和状态寄存器。状态寄存器存储多种不同类型的状态位。这些状态位可以是负状态位，进位状态位，溢出状态位和零状态位。这些状态位通常依赖于当前算术逻辑单元操作产生的结果的条件。状态位保护指令类型允许选择与当前算术逻辑单元结果相对应的保护而不进行修改的状态位。该状态位保护指令优选地包括对应于每个状态位的单独保护位。如果保护位具有第一数字状态，则可以根据当前的算术逻辑单元结果对相应的状态位进行修改。如果保护位具有第二相对数字状态，则根据算术逻辑单元结果保护对应的状态位不被修改。

3. 发明授权

US6098163A Three input arithmetic logic unit with shifter 失效
标题翻译：三输入算术逻辑单元带移位器
公开(公告)号：US6098163A
公开(公告)日：2000-08-01
申请号：US160573
申请日：1993-11-30
申请人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Phillip Moyse
发明人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Phillip Moyse
IPC分类号： G06F5/01 , G06F15/00
CPC分类号： G06F9/30167 , G06F5/015
摘要： A data processing apparatus includes a three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. Data registers (200) store the three data inputs and the arithmetic logic unit output. The second input signal comes from a controllable shifter (235). The shift amount is a default shift amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the shifter (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the shift amount. The output of the shifter (235) may be stored independently of the arithmetic logic unit (230) result. The third input signal comes from a multiplexer (233) that selects between an instruction specified immediate field, data recalled from a data register or a mask input from a mask generator (239). One preferred form of the mask has a number of right justified 1's corresponding to a mask input signal. This mask input signal may be the default shift amount or a predetermined number of the least significant bits of a third input signal as selected by a multiplexer. A second preferred form of the mask is selected one of the left most 1, the right most 1, the left most bit change or the right most bit change of a predetermined set of the least significant bits of data recalled from a data register. In the preferred embodiment of this invention, the three input arithmetic logic unit (230) is embodied in a data processor circuits as a part of a multiprocessor integrated circuit (100) used in image processing.
摘要翻译：数据处理装置包括产生由功能信号选择的三个输入的组合的三输入算术逻辑单元（230）。数据寄存器（200）存储三个数据输入和算术逻辑单元输出。第二输入信号来自可控移位器（235）。移位量是存储在特殊数据寄存器中的默认偏移量，是从数据寄存器或零调用的预定数据位组。一个恒定源（236）连接到移位器（235）以提供“1”的多位数字信号。这允许产生形式2N的第二输入信号，其中N是移位量。移位器（235）的输出可以独立于算术逻辑单元（230）的结果存储。第三输入信号来自多路复用器（233），其在指定的指令字段，从数据寄存器调用的数据或从掩码生成器输入的掩码（239）之间进行选择。掩模的一个优选形式具有对应于掩模输入信号的许多右对齐1。该掩模输入信号可以是由多路复用器选择的第三输入信号的默认偏移量或预定数量的最低有效位。选择掩模的第二优选形式是从数据寄存器回调的数据的最低有效位的预定集合的最左1，最右1，最左位变化或最右位变化中的一个。在本发明的优选实施例中，三输入算术逻辑单元（230）被实现为作为在图像处理中使用的多处理器集成电路（100）的一部分的数据处理器电路。

4. 发明授权

US6067613A Rotation register for orthogonal data transformation 失效
标题翻译：旋转寄存器进行正交数据转换
公开(公告)号：US6067613A
公开(公告)日：2000-05-23
申请号：US159346
申请日：1993-11-30
申请人： Keith Balmer
发明人： Keith Balmer
IPC分类号： G09G5/39 , G06F3/153 , G06F9/30 , G06F9/315 , G06F17/14 , G11C19/00 , G06F15/00
CPC分类号： G06F9/30032 , G06F17/147 , G06F9/30036 , G06F9/30098 , G06F9/30141 , G11C19/00
摘要： A data processing apparatus (71) includes a data processor bus (103), the rotation register (208) and a register selection circuit. The rotation register (208) is embodied by a plurality of data registers (200) each having a plurality of equal bit groups. The number of bits within each bit group of each data register preferably equals the number N of data registers. The register selection circuit permits normal register reads and writes via the data processor bus. The register selection circuit permits special rotational data accesses. In a rotation read mode the register selection circuit selects noncontiguous bits from a predetermined position within each sections for each of the data registers for read access. In a rotation write mode the register selection circuit selects noncontiguous bits from a predetermined position within each sections for each of the data registers for write access. The data registers (200) are connected together in a loop (208). The most significant bit of each data register connected to the least significant bit of a sequential data register, with the last data register is connected to the first data register. In a register rotation mode the register selection circuit rotates bits in each data register in around the loop. This rotation is preferably by one bit upon each execution of a register rotation instruction.
摘要翻译：数据处理装置（71）包括数据处理器总线（103），旋转寄存器（208）和寄存器选择电路。旋转寄存器（208）由多个数据寄存器（200）实现，每个数据寄存器（200）具有多个相等的位组。每个数据寄存器的每个位组内的位数优选等于数据寄存器的数量N. 寄存器选择电路允许通过数据处理器总线进行正常寄存器读和写操作。寄存器选择电路允许特殊的旋转数据访问。在旋转读取模式中，寄存器选择电路从每个部分中的预定位置选择用于读取访问的每个数据寄存器的不连续位。在旋转写入模式中，寄存器选择电路为每个用于写入的数据寄存器的每个部分中的预定位置选择非连续位。数据寄存器（200）以循环（208）连接在一起。连接到顺序数据寄存器的最低有效位的每个数据寄存器的最高有效位与最后一个数据寄存器连接到第一个数据寄存器。在寄存器旋转模式下，寄存器选择电路在循环周围旋转每个数据寄存器中的位。每次执行寄存器旋转指令时，该旋转优选为一位。

5. 发明授权

US6058473A Memory store from a register pair conditional upon a selected status bit 失效
标题翻译：来自寄存器对的存储器根据所选择的状态位进行存储
公开(公告)号：US6058473A
公开(公告)日：2000-05-02
申请号：US160118
申请日：1993-11-30
申请人： Karl M. Guttag , Sydney W. Poland , Keith Balmer
发明人： Karl M. Guttag , Sydney W. Poland , Keith Balmer
IPC分类号： G06T1/60 , G06F9/302 , G06F9/312 , G06F9/318 , G06F9/32 , G06F9/34 , G06F9/38 , G06F12/08
CPC分类号： G06F9/30101 , G06F9/30014 , G06F9/30036 , G06F9/30043 , G06F9/30094 , G06F9/30167 , G06F9/30189 , G06F9/30192 , G06F9/34 , G06F9/3842
摘要： A memory store operation comes from one of a pair of registers selected by an arithmetic logic unit condition. An instruction logic circuit (250, 660) controls an addressing circuit (120) to store data in a first register into memory if a selected status bit has a first state and to store data in a second register associated with the first register into memory if the selected status bit has a second state in response to a register pair conditional store instruction. The bits may indicate a negative output of the arithmetic logic unit (230), a carry out signal, an overflow, or a zero output. The register pair conditional store instruction designates a particular one of the status bits to control the conditional store. The instruction logic circuit (250, 660) substitutes the selected status bit for a least significant bit of the register number. Thus memory store is from the first register if the status bit is "1" and is from the second register if the status bit is "0". In a further embodiment the register pair conditional write instruction is conditional. The write operation aborts if the designated condition is true. In the preferred embodiment of this invention, the arithmetic logic unit (230), the status register (210), the data registers (200) and the instruction decode logic (250, 660) are embodied in at least one digital image/graphics processor (71) as a part of a multiprocessor formed in a single integrated circuit (100) used in image processing.
摘要翻译：存储器存储操作来自由算术逻辑单元条件选择的一对寄存器之一。如果选择的状态位具有第一状态并且将与第一寄存器相关联的第二寄存器中的数据存储到存储器中，则指令逻辑电路（250,660）控制寻址电路（120）将第一寄存器中的数据存储到存储器中，如果所选状态位响应于寄存器对条件存储指令具有第二状态。这些位可以指示算术逻辑单元（230）的负输出，进位信号，溢出或零输出。寄存器对条件存储指令指定用于控制条件存储的特定一个状态位。指令逻辑电路（250,660）将选择的状态位替换为寄存器编号的最低有效位。因此，如果状态位为“1”，则存储器来自第一寄存器，如果状态位为“0”，则来自第二寄存器。在另一实施例中，寄存器对条件写指令是有条件的。如果指定的条件为真，则写入操作中止。在本发明的优选实施例中，算术逻辑单元（230），状态寄存器（210），数据寄存器（200）和指令解码逻辑（250,660）被体现在至少一个数字图像/图形处理器（71）作为在图像处理中使用的单个集成电路（100）中形成的多处理器的一部分。

6. 发明授权

US5995748A Three input arithmetic logic unit with shifter and/or mask generator 失效
标题翻译：具有移位器和/或掩码发生器的三输入算术逻辑单元
公开(公告)号：US5995748A
公开(公告)日：1999-11-30
申请号：US99727
申请日：1998-06-19
申请人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Philip Moyse
发明人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Philip Moyse
IPC分类号： G06F5/01 , G06F9/302 , G06F9/305 , G06F9/308 , G06F9/315 , G06F9/32 , G06F12/02
CPC分类号： G06F9/30014 , G06F12/0284 , G06F5/015 , G06F9/30018 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/30094 , G06F9/30167 , G06F9/325
摘要： A data processing apparatus includes a three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. Data registers (200) store the three data inputs and the arithmetic logic unit output. The second input signal optionally comes from a controllable shifter (235). The shift amount is a default shift amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the shifter (235) to supply an N bit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the shift amount. The output of the shifter (235) may be stored independently of the arithmetic logic unit (230) result. The third input signal optionally comes from a multiplexer (233) that selects between an instruction specified immediate field, data recalled from a data register or a mask input from a mask generator (239). This mask input signal may be the default shift amount or a predetermined number of the least significant bits of a third input signal as selected by a multiplexer. In the preferred embodiment of this invention, the three input arithmetic logic unit (230) is embodied in a data processor circuits as a part of a multiprocessor integrated circuit (100) used in image processing.
摘要翻译：数据处理装置包括产生由功能信号选择的三个输入的组合的三输入算术逻辑单元（230）。数据寄存器（200）存储三个数据输入和算术逻辑单元输出。第二输入信号可选地来自可控移位器（235）。移位量是存储在特殊数据寄存器中的默认偏移量，是从数据寄存器或零调用的预定数据位组。一个恒定源（236）连接到移位器（235）以提供“1”的N位数字信号。这允许产生形式2N的第二输入信号，其中N是移位量。移位器（235）的输出可以独立于算术逻辑单元（230）的结果存储。第三输入信号可选地来自多路复用器（233），其在指令指定的立即字段，从数据寄存器调用的数据或从掩码生成器输入的掩码（239）之间进行选择。该掩模输入信号可以是由多路复用器选择的第三输入信号的默认偏移量或预定数量的最低有效位。在本发明的优选实施例中，三输入算术逻辑单元（230）被实现为作为在图像处理中使用的多处理器集成电路（100）的一部分的数据处理器电路。

7. 发明授权

US5995747A Three input arithmetic logic unit capable of performing all possible three operand boolean operations with shifter and/or mask generator 失效
标题翻译：三输入算术逻辑单元能够用移位器和/或掩码发生器执行所有可能的三个操作数布尔运算
公开(公告)号：US5995747A
公开(公告)日：1999-11-30
申请号：US794962
申请日：1997-02-04
申请人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Philip Moyse
发明人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Philip Moyse
IPC分类号： G06F5/01 , G06F9/302 , G06F9/305 , G06F9/308 , G06F9/315 , G06F9/32 , G06F12/02 , G06F7/52
CPC分类号： G06F9/30014 , G06F12/0284 , G06F5/015 , G06F9/30018 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/30094 , G06F9/30167 , G06F9/325
摘要： A data processing apparatus includes a three input arithmetic logic unit (230) that generates a Boolean combination of the three inputs that is selected by a function signal. The arithmetic logic unit is capable of forming all possible Boolean combinations of the three inputs. Data registers (200) store the three data inputs and the arithmetic logic unit output. The second input signal comes from a controllable shifter (235). The shift amount is a default shift amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the shifter (235) to supply an N bit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the shift amount. The output of the shifter (235) may be stored independently of the arithmetic logic unit (230) result. The third input signal comes from a multiplexer (233) that selects between an instruction specified immediate field, data recalled from a data register or a mask input from a mask generator (239). This mask input signal may be the default shift amount or a predetermined number of the least significant bits of a third input signal as selected by a multiplexer. In the preferred embodiment of this invention, the three input arithmetic logic unit (230) is embodied in a data processor circuits as a part of a multiprocessor integrated circuit (100) used in image processing.
摘要翻译：数据处理装置包括三输入算术逻辑单元（230），其生成由功能信号选择的三个输入的布尔组合。算术逻辑单元能够形成三个输入的所有可能的布尔组合。数据寄存器（200）存储三个数据输入和算术逻辑单元输出。第二输入信号来自可控移位器（235）。移位量是存储在特殊数据寄存器中的默认偏移量，是从数据寄存器或零调用的预定数据位组。一个恒定源（236）连接到移位器（235）以提供“1”的N位数字信号。这允许产生形式2N的第二输入信号，其中N是移位量。移位器（235）的输出可以独立于算术逻辑单元（230）的结果存储。第三输入信号来自多路复用器（233），其在指定的指令字段，从数据寄存器调用的数据或从掩码生成器输入的掩码（239）之间进行选择。该掩模输入信号可以是由多路复用器选择的第三输入信号的默认偏移量或预定数量的最低有效位。在本发明的优选实施例中，三输入算术逻辑单元（230）被实现为作为在图像处理中使用的多处理器集成电路（100）的一部分的数据处理器电路。

8. 发明授权

US5922070A Pipelined data processing including program counter recycling 失效
标题翻译：流水线数据处理，包括程序计数器回收
公开(公告)号：US5922070A
公开(公告)日：1999-07-13
申请号：US350640
申请日：1994-12-07
申请人： Gary L. Swoboda , Mark R. Hammes , Douglas Deao , Keith Balmer , Nick Ing-Simmons
发明人： Gary L. Swoboda , Mark R. Hammes , Douglas Deao , Keith Balmer , Nick Ing-Simmons
IPC分类号： G06F9/38 , G06F11/36 , G06F9/00
CPC分类号： G06F11/3636 , G06F9/3842 , G06F9/3863 , G06F9/3867
摘要： In a pipeline data processor (11), an address pipeline (39, 41) id provided to hold the addresses of the instructions presently in the instruction pipeline (23, 25). The address pipeline facilitates tracing only executed instructions, and permits stopping the data processor during a branch delay slot without losing the branch information.
摘要翻译：在流水线数据处理器（11）中，提供用于保持当前在指令流水线（23,25）中的指令的地址的地址流水线（39,41）id。地址管线便于跟踪执行的指令，并且允许在分支延迟时隙期间停止数据处理器而不丢失分支信息。

9. 发明授权

US5881272A Synchronized MIMD multi-processing system and method inhibiting instruction fetch at other processors on write to program counter of one processor 失效
标题翻译：同步MIMD多处理系统和方法禁止在其他处理器上的指令读取到一个处理器的程序计数器
公开(公告)号：US5881272A
公开(公告)日：1999-03-09
申请号：US922152
申请日：1997-09-02
申请人： Keith Balmer
发明人： Keith Balmer
IPC分类号： G06F9/30 , G06F9/312 , G06F9/315 , G06F9/318 , G06F9/355 , G06F9/38 , G06F15/16
CPC分类号： G06F9/30043 , G06F9/30032 , G06F9/30036 , G06F9/30087 , G06F9/30112 , G06F9/3013 , G06F9/30145 , G06F9/3016 , G06F9/30167 , G06F9/30192 , G06F9/321 , G06F9/325 , G06F9/355 , G06F9/3832 , G06F9/3885
摘要： A multi-processor system arranged, in one embodiment, as an image and graphics processor. The processor is structured with several individual processors all having communication links to several memories. The individual processors can, on a cycle by cycle basis, be grouped in any configuration to run in synchronism (but from different instruction streams) with the other processors in that group. More than one such synchronized group can be formed concurrently. A crossbar switch serves to establish the processor memory links and the entire image processor, including the individual processors, the crossbar switch and the memories are contained on a single silicon chip.
摘要翻译：在一个实施例中，多处理器系统被布置为图像和图形处理器。处理器的结构与几个单独的处理器都具有到几个存储器的通信链接。各个处理器可以逐周期地分组在任何配置中，与该组中的其他处理器同步（但是来自不同的指令流）运行。可以同时形成多个这样的同步组。交叉开关用于建立处理器存储器链路，并且整个图像处理器，包括各个处理器，交叉开关和存储器都包含在单个硅芯片上。

10. 发明授权

US5805913A Arithmetic logic unit with conditional register source selection 失效
标题翻译：具有条件寄存器源选择的算术逻辑单元
公开(公告)号：US5805913A
公开(公告)日：1998-09-08
申请号：US159344
申请日：1993-11-30
申请人： Karl M. Guttag , Keith Balmer
发明人： Karl M. Guttag , Keith Balmer
IPC分类号： G06F9/30 , G06F9/302 , G06F9/32 , G06F13/00
CPC分类号： G06F9/30014 , G06F9/30094 , G06F9/30101
摘要： A data processing apparatus having an arithmetic logic unit (230) with conditional register source selection includes a plurality of data registers (200), a status register (210) storing at least one status bit, an arithmetic logic unit (230) and an instruction decode logic (245, 246, 250). The instruction decode logic (245, 246, 250) responds to a received register pair conditional source instruction to supply data from either a first register or a second register to the first input of said arithmetic logic unit (230) depending on the digital state of a status bit. Preferably an instruction field indicates whether the instruction involves conditional register pair source selection. There are preferably a plurality of status bits and the register pair conditional source instruction determines which status bit controls the source selection. A prior output of the arithmetic logic unit (230) sets the plural status bits. These may include negative, carry, overflow and zero. The instruction word may designate one or more of these status bits not changed by the current instruction. The data registers (200) are preferably accessed via consecutive register numbers, the first register having an odd register number and the second register having an even register number one less.
摘要翻译：具有条件寄存器源选择的算术逻辑单元（230）的数据处理装置包括多个数据寄存器（200），存储至少一个状态位的状态寄存器（210），运算逻辑单元（230）和指令解码逻辑（245,246,250）。指令解码逻辑（245,246,250）响应接收到的寄存器对条件源指令，以将数据从第一寄存器或第二寄存器提供给所述算术逻辑单元（230）的第一输入，这取决于数字状态状态位。优选地，指令字段指示该指令是否涉及条件寄存器对源选择。优选地有多个状态位，并且寄存器对条件源指令确定哪个状态位控制源选择。算术逻辑单元（230）的先前输出设置多个状态位。这些可能包括负，进位，溢出和零。指令字可以指定当前指令不改变的这些状态位中的一个或多个。数据寄存器（200）优选经由连续的寄存器编号进行访问，第一寄存器具有奇数寄存器编号，第二寄存器具有偶数寄存器编号。

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