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1. 发明申请

US20120039089A1 OPTICAL CONSTRUCTION AND DISPLAY SYSTEM INCORPORATING SAME 审中-公开
标题翻译：光学结构和显示系统
公开(公告)号：US20120039089A1
公开(公告)日：2012-02-16
申请号：US13264281
申请日：2010-04-15
申请人： Encai Hao , Fei Lu , William Blake Kolb , Brian W. Ostlie , Adam D. Haag , Michael Benton Free , William D. Coggio , Michael L. Steiner , Soemantri Widagdo , Kui Chen-Ho , Lan H. Liu , Robert F. Kamrath , Scott M Tapio , John A. Wheatiey , Charles David Hoyle , Michael F Weber
发明人： Encai Hao , Fei Lu , William Blake Kolb , Brian W. Ostlie , Adam D. Haag , Michael Benton Free , William D. Coggio , Michael L. Steiner , Soemantri Widagdo , Kui Chen-Ho , Lan H. Liu , Robert F. Kamrath , Scott M Tapio , John A. Wheatiey , Charles David Hoyle , Michael F Weber
IPC分类号： F21V7/04 , G02B5/30 , F21V1/00
CPC分类号： G02F1/133606 , G02B5/02 , G02B5/3041 , G02B5/3058 , G02B5/3083 , G02B6/0056 , G02F1/133536
摘要： Optical constructions are disclosed. A disclosed optical construction includes a reflective polarizer layer, and an optical film that is disposed on the reflective polarizer layer. The optical film has an optical haze that is not less than about 50%. Substantial portions of each two neighboring major surfaces in the optical construction are in physical contact with each other. The optical construction has an axial luminance gain that is not less than about 1.2.
摘要翻译：公开了光学结构。所公开的光学结构包括反射偏振器层和设置在反射偏振器层上的光学膜。光学膜具有不小于约50％的光学雾度。光学结构中每两个相邻主表面的实质部分彼此物理接触。光学结构具有不小于约1.2的轴向亮度增益。

2. 发明授权

US06834338B1 Microprocessor with branch-decrement instruction that provides a target and conditionally modifies a test register if the register meets a condition 有权
标题翻译：具有分支递减指令的微处理器，如果寄存器满足条件，则提供目标并有条件地修改测试寄存器
公开(公告)号：US06834338B1
公开(公告)日：2004-12-21
申请号：US09703144
申请日：2000-10-31
申请人： David Hoyle , Timothy D. Anderson
发明人： David Hoyle , Timothy D. Anderson
IPC分类号： G06F932
CPC分类号： G06F9/30145 , G06F9/30072 , G06F9/3012 , G06F9/30167 , G06F9/322 , G06F9/325
摘要： A data processing system is provided with a digital signal processor which has an instruction for conditionally branching based on the contents of a specified test register. Each time a branch is taken, the register is decremented as a side effect of executing the branch instruction. In addition, a predicate register is specified by the instruction. A branch occurs only if both registers meet specified conditions.
摘要翻译：数据处理系统具有数字信号处理器，该数字信号处理器具有基于指定测试寄存器的内容进行有条件分支的指令。每次采取分支时，寄存器作为执行分支指令的副作用而递减。另外，指令指定谓词寄存器。只有当两个寄存器满足指定条件时才会发生分支。

3. 发明授权

US06754809B1 Data processing apparatus with indirect register file access 有权
标题翻译：具有间接寄存器文件访问的数据处理设备
公开(公告)号：US06754809B1
公开(公告)日：2004-06-22
申请号：US09713442
申请日：2000-11-15
申请人： Karl M. Guttag , David Hoyle , Keith Balmer
发明人： Karl M. Guttag , David Hoyle , Keith Balmer
IPC分类号： G06F934
CPC分类号： G06F9/3012 , G06F9/3004 , G06F9/30098 , G06F9/35 , G06F9/383
摘要： A data processing apparatus which uses a register file to provide a faster alternative to indirect memory addressing. A functional unit is connected to a data register file (76) which comprises a plurality of registers, each of which is accessed by a corresponding register number. The functional unit (e.g., A-unit 78) can execute at least one indirect register access instruction that comprises an operand register number field. Instruction decode circuitry, connected to the register file and the functional unit, is responsive to the indirect register access instruction to recall data stored in an operand register (190) specified by the operand register number in the instruction, identify the recalled data as a register access number, and recall operand data from a data register corresponding to the register access number for use as an operand by the functional unit. Indirect register addressing permits the apparatus to more quickly execute table look up intensive algorithms, such as variable length decoding, than an apparatus employing only indirect memory addressing.
摘要翻译：一种使用寄存器文件来提供间接存储器寻址的更快替代的数据处理装置。功能单元连接到数据寄存器文件（76），数据寄存器文件（76）包括多个寄存器，每个寄存器都由对应的寄存器号码访问。功能单元（例如，A单元78）可以执行包括操作数寄存器号字段的至少一个间接寄存器访问指令。连接到寄存器文件和功能单元的指令解码电路响应于间接寄存器访问指令来调用存储在指令中由操作数寄存器号指定的操作数寄存器（190）中的数据，将调用的数据标识为寄存器访问号码，并且从与寄存器访问号相对应的数据寄存器中调用操作数数据，以用作功能单元的操作数。间接寄存器寻址允许装置比仅使用间接存储器寻址的装置更快速地执行表查找密集型算法，例如可变长度解码。

4. 发明授权

US06574724B1 Microprocessor with non-aligned scaled and unscaled addressing 有权
标题翻译：具有非对齐缩放和非缩放寻址的微处理器
公开(公告)号：US06574724B1
公开(公告)日：2003-06-03
申请号：US09702474
申请日：2000-10-31
申请人： David Hoyle , Joseph R. Zbiciak , Jeremiah E. Golston
发明人： David Hoyle , Joseph R. Zbiciak , Jeremiah E. Golston
IPC分类号： G06F1200
CPC分类号： G06F9/3828 , G06F9/30181 , G06F9/3555
摘要： A data processing system having a central processing (CPU) unit and a method of operation is provided. The CPU has an instruction set architecture that is optimized for intensive numeric algorithm processing. The CPU has dual load/store units connected to dual memory target ports of a memory controller. The CPU can execute two aligned data transfers each having a length of one byte, two bytes, four bytes, or eight bytes in parallel by executing two load/store instructions. The CPU can also execute a single non-aligned data transfer having a length of four bytes or eight bytes by executing a non-aligned load/store instruction that utilizes both memory target ports. A data transfer address for each load/store instruction is formed by fetching the instruction, decoding the instruction to determine instruction type, transfer data size, and scaling selection, selectively scaling an offset provided by the instruction and combining the selectively scaled offset with a base address value. The resultant address is then provided to the memory system to initiate a data transfer.
摘要翻译：提供具有中央处理（CPU）单元和操作方法的数据处理系统。 CPU具有针对密集数值算法处理进行了优化的指令集体系结构。 CPU具有连接到存储器控制器的双存储器目标端口的双重加载/存储单元。 CPU可以通过执行两个加载/存储指令来并行执行两个对齐的数据传输，每个数据传输具有一个字节，两个字节，四个字节或八个字节的长度。 CPU还可以通过执行利用两个存储器目标端口的不对齐的加载/存储指令来执行长度为四字节或八字节的单个非对齐数据传输。每个加载/存储指令的数据传输地址通过取指令，解码指令来确定指令类型，传输数据大小和缩放选择来形成，选择性地缩放由指令提供的偏移量，并将选择性缩放的偏移量与基数地址值。然后将结果地址提供给存储器系统以发起数据传送。

5. 发明授权

US06496740B1 Transfer controller with hub and ports architecture 有权
标题翻译：具有集线器和端口架构的传输控制器
公开(公告)号：US06496740B1
公开(公告)日：2002-12-17
申请号：US09543870
申请日：2000-04-06
申请人： Iain Robertson , David Hoyle
发明人： Iain Robertson , David Hoyle
IPC分类号： G05B1101
CPC分类号： G06F15/17
摘要： The transfer controller with hub and ports (TCHP) performs the task of communication throughout an entire system in a centralized function. A single hub (435) tied to multiple ports (440, 447, 450, 452) by a central pipeline is the medium for all data communications among DSP clusters (455), external devices, and external memory. A transfer request queue manager (420) receives, prioritizes and queues data transfer requests. Each data port includes an identically configured interior interface (901) connected to the hub (435) and an exterior interface (902) configured for a target external memory/device connected to the port. The interior interfaces of all ports are clocked at a common internal frequency, while the exterior interfaces are clocked at the frequency of the external memory/device connected to the port.
摘要翻译：具有集线器和端口（TCHP）的传输控制器以集中的功能在整个系统中执行通信任务。通过中央管线连接到多个端口（440,447,450,452）的单个集线器（435）是用于DSP集群（455），外部设备和外部存储器之间的所有数据通信的介质。传送请求队列管理器（420）接收数据传输请求的优先次序和队列。每个数据端口包括连接到集线器（435）的相同配置的内部接口（901）和被配置用于连接到端口的目标外部存储器/设备的外部接口（902）。所有端口的内部接口以公共内部频率计时，而外部接口按照连接到端口的外部存储器/设备的频率进行计时。

6. 发明授权

US6141010A Computer interface method and apparatus with targeted advertising 失效
公开(公告)号：US6141010A
公开(公告)日：2000-10-31
申请号：US118351
申请日：1998-07-17
申请人： Martin David Hoyle
发明人： Martin David Hoyle
IPC分类号： G06F9/445 , G06Q30/02 , G06F3/00
CPC分类号： G06Q30/0269 , G06F8/60 , G06F8/65 , G06F9/00 , G06F9/30 , G06Q30/02 , G06Q30/0251 , G06Q30/0254 , G06Q30/0256 , G06Q30/0267
摘要： A method and apparatus for providing an automatically upgradeable software application that includes targeted advertising based upon demographics and user interaction with the computer. The software application is a graphical user interface that includes a display region used for banner advertising that is downloaded from time to time over a network such as the Internet. The software application is accessible from a server via the Internet and demographic information on the user is acquired by the server and used for determining what banner advertising will be sent to the user. The software application further targets the advertisements in response to normal user interaction, or use, of the computer. Associated with each banner advertisement is a set of data that is used by the software application in determining when a particular banner is to be displayed. This includes the specification of certain programs that the user may have so that, when the user runs the program (such as a spreadsheet program), an advertisement will be displayed that is relevant to that program (such as an advertisement for a stock brokerage). This provides two-tiered, real-time targeting of advertising--both demographically and reactively. The software application includes programming that accesses the server on occasion to determine if one or more components of the application need upgrading to a newer version. If so, the components are downloaded and installed without requiring any input or action by the user.

7. 发明授权

US08392789B2 Method and system for decoding low density parity check codes 有权
标题翻译：解码低密度奇偶校验码的方法和系统
公开(公告)号：US08392789B2
公开(公告)日：2013-03-05
申请号：US12510899
申请日：2009-07-28
申请人： Eric Biscondi , David Hoyle , Tod David Wolf
发明人： Eric Biscondi , David Hoyle , Tod David Wolf
IPC分类号： H03M13/00
CPC分类号： H03M13/116 , H03M13/1114 , H03M13/1117 , H03M13/112 , H03M13/1165 , H03M13/1188 , H03M13/3715 , H03M13/3723 , H03M13/3753 , H03M13/47 , H03M13/616 , H03M13/6544 , H03M13/658 , H03M13/6583
摘要： A method for decoding a codeword in a data stream encoded according to a low density parity check (LDPC) code having an m×j parity check matrix H by initializing variable nodes with soft values based on symbols in the codeword, wherein a graph representation of H includes m check nodes and j variable nodes, and wherein a check node m provides a row value estimate to a variable node j and a variable node j provides a column value estimate to a check node m if H(m,j) contains a 1, computing row value estimates for each check node, wherein amplitudes of only a subset of column value estimates provided to the check node are computed, computing soft values for each variable node based on the computed row value estimates, determining whether the codeword is decoded based on the soft values, and terminating decoding when the codeword is decoded.
摘要翻译：一种用于根据具有m×j个奇偶校验矩阵H的低密度奇偶校验（LDPC）码编码的数据流中的码字进行解码的方法，通过基于码字中的符号来初始化具有软值的可变节点，其中，图形表示 H包括m个校验节点和j个变量节点，并且其中校验节点m向变量节点j提供行值估计，并且如果H（m，j）包含校验节点j，变量节点j向校验节点m提供列值估计 1，计算每个校验节点的行值估计，其中仅计算提供给校验节点的列值估计的子集的幅度，基于所计算的行值估计来计算每个变量节点的软值，确定码字是否被解码基于软值，并且当码字被解码时终止解码。

8. 发明授权

US07685537B2 Computer interface method and apparatus with portable network organization system and targeted advertising 有权
标题翻译：具有便携式网络组织系统和针对性广告的计算机接口方法和装置
公开(公告)号：US07685537B2
公开(公告)日：2010-03-23
申请号：US12110818
申请日：2008-04-28
申请人： Martin David Hoyle
发明人： Martin David Hoyle
IPC分类号： G06F15/00 , G06F13/00
CPC分类号： G06Q30/0269 , G06F8/60 , G06F8/65 , G06F9/00 , G06F9/30 , G06Q30/02 , G06Q30/0251 , G06Q30/0254 , G06Q30/0256 , G06Q30/0267
摘要： A method and apparatus for providing an automatically upgradeable software application includes targeted advertising based upon demographics and user interaction with the computer. The software application is accessible from a server via the network and demographic information on the user is acquired by the server and used for determining what advertising will be sent to the user. The software application includes programming that accesses the sewer to determine if one or more components of the application need upgrading. If so, the components can be downloaded and installed without further action by the user. A distribution tool is provided for software distribution and upgrading over the network. Also provided is a user profile that is accessible to any computer on the network. Furthermore, multiple users of the same computer can possess Internet web resources and files that are personalized, maintained and organized.
摘要翻译：用于提供可自动升级的软件应用的方法和装置包括基于人口统计学和与计算机的用户交互的有针对性的广告。软件应用程序可以通过网络从服务器访问，用户的人口统计信息由服务器获取，并用于确定将向用户发送哪些广告。软件应用程序包括访问下水道的程序，以确定应用程序的一个或多个组件是否需要升级。如果是这样，可以下载和安装组件，而无需用户进一步的操作。提供分发工具，用于通过网络进行软件分发和升级。还提供了可由网络上的任何计算机访问的用户配置文件。此外，同一台计算机的多个用户可以拥有个性化，维护和组织的互联网网络资源和文件。

9. 发明申请

US20050188182A1 Microprocessor having a set of byte intermingling instructions 审中-公开
标题翻译：微处理器具有一组字节混合指令
公开(公告)号：US20050188182A1
公开(公告)日：2005-08-25
申请号：US11114549
申请日：2005-04-26
申请人： David Hoyle , Vishal Markandey , Lewis Nardini
发明人： David Hoyle , Vishal Markandey , Lewis Nardini
IPC分类号： G06F15/00
CPC分类号： G06F9/30032 , G06F9/30036 , G06F9/3828 , G06F9/3853 , G06F9/3891
摘要： A data processing system is provided with a digital signal processor that has a set of instructions for intermingling byte fields selected from a selected pair of source operands and storing the ordered result in a selected destination register. A first 32-bit operand is treated as four 8-bit fields while a second 32-bit operand is treated as four 8-bit fields. Intermingling circuitry is operable to form an ordered result in accordance with each one of the set of byte intermingling instructions. An instruction is provided that performs a shift right and byte merge operation. Another instruction is provided that performs a shift left and byte merge operation. Another instruction is provided that perform a byte swap operation. A set of instructions are provided that perform various byte packing and unpacking operations.
摘要翻译：数据处理系统具有数字信号处理器，该数字信号处理器具有一组指令，用于混合从所选择的一对源操作数中选择的字节字段，并将所选择的结果存储在所选择的目标寄存器中。第一个32位操作数被视为四个8位字段，而第二个32位操作数被视为四个8位字段。混合电路可操作以根据该组字节混合指令中的每一个形成有序结果。提供执行右移和字节合并操作的指令。另外提供了执行左移和字节合并操作的指令。提供另一个执行字节交换操作的指令。提供了一组执行各种字节打包和解包操作的指令。

10. 发明授权

US06766440B1 Microprocessor with conditional cross path stall to minimize CPU cycle time length 有权
标题翻译：具有条件交叉路径失速的微处理器，以最小化CPU周期时间长度
公开(公告)号：US06766440B1
公开(公告)日：2004-07-20
申请号：US09702453
申请日：2000-10-31
申请人： Donald E. Steiss , David Hoyle
发明人： Donald E. Steiss , David Hoyle
IPC分类号： G06F930
CPC分类号： G06F9/3885 , G06F9/3824 , G06F9/3828 , G06F9/3891
摘要： A digital system is provided that includes a central processing unit (CPU) that has an instruction execution pipeline with a plurality of functional units for executing instructions in a sequence of CPU cycles. The execution units are clustered into two or more groups. Cross-path circuitry is provided such that results from any execution unit in one execution unit cluster can be supplied to execution units in another cluster. A cross-path stall is conditionally inserted to stall all of the functional groups when one execution unit cluster requires an operand from another cluster on a given CPU cycle and the execution unit that is producing that operand completes the computation of that operand on an immediately preceding CPU cycle.
摘要翻译：提供了一种数字系统，其包括具有指令执行流水线的中央处理单元（CPU），所述指令执行流水线具有用于以CPU周期的顺序执行指令的多个功能单元。执行单元被分组成两个或更多个组。提供交叉路径电路，使得可以将一个执行单元集群中的任何执行单元的结果提供给另一个集群中的执行单元。当一个执行单元集群在给定的CPU周期中需要来自另一个集群的操作数时，有条件地插入一个跨路径停顿来停止所有的功能组，并且正在产生该操作数的执行单元完成该操作数的计算。 CPU周期。

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