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1. 发明授权

US06754809B1 Data processing apparatus with indirect register file access 有权
标题翻译：具有间接寄存器文件访问的数据处理设备
公开(公告)号：US06754809B1
公开(公告)日：2004-06-22
申请号：US09713442
申请日：2000-11-15
申请人： Karl M. Guttag , David Hoyle , Keith Balmer
发明人： Karl M. Guttag , David Hoyle , Keith Balmer
IPC分类号： G06F934
CPC分类号： G06F9/3012 , G06F9/3004 , G06F9/30098 , G06F9/35 , G06F9/383
摘要： A data processing apparatus which uses a register file to provide a faster alternative to indirect memory addressing. A functional unit is connected to a data register file (76) which comprises a plurality of registers, each of which is accessed by a corresponding register number. The functional unit (e.g., A-unit 78) can execute at least one indirect register access instruction that comprises an operand register number field. Instruction decode circuitry, connected to the register file and the functional unit, is responsive to the indirect register access instruction to recall data stored in an operand register (190) specified by the operand register number in the instruction, identify the recalled data as a register access number, and recall operand data from a data register corresponding to the register access number for use as an operand by the functional unit. Indirect register addressing permits the apparatus to more quickly execute table look up intensive algorithms, such as variable length decoding, than an apparatus employing only indirect memory addressing.
摘要翻译：一种使用寄存器文件来提供间接存储器寻址的更快替代的数据处理装置。功能单元连接到数据寄存器文件（76），数据寄存器文件（76）包括多个寄存器，每个寄存器都由对应的寄存器号码访问。功能单元（例如，A单元78）可以执行包括操作数寄存器号字段的至少一个间接寄存器访问指令。连接到寄存器文件和功能单元的指令解码电路响应于间接寄存器访问指令来调用存储在指令中由操作数寄存器号指定的操作数寄存器（190）中的数据，将调用的数据标识为寄存器访问号码，并且从与寄存器访问号相对应的数据寄存器中调用操作数数据，以用作功能单元的操作数。间接寄存器寻址允许装置比仅使用间接存储器寻址的装置更快速地执行表查找密集型算法，例如可变长度解码。

2. 发明授权

US06711602B1 Data processor with flexible multiply unit 有权
标题翻译：数据处理器具有灵活的乘法单元
公开(公告)号：US06711602B1
公开(公告)日：2004-03-23
申请号：US09703093
申请日：2000-10-31
申请人： Amarjit Singh Bhandal , Keith Balmer , David Hoyle , Karl M. Guttag , Zahid Hussain
发明人： Amarjit Singh Bhandal , Keith Balmer , David Hoyle , Karl M. Guttag , Zahid Hussain
IPC分类号： G06F752
CPC分类号： G06F9/30014 , G06F9/3853
摘要： An embodiment of the invention includes a pair of parallel 16×16 multipliers each with two 32-bit inputs and one 32-bit output. There are options to allow input halfword and byte selection for four independent 8×8 or two independent 16×16 multiplications, real and imaginary parts of comple×multiplication, pairs of partial sums for 32×32 multiplication, and partial sums for 16×32 multiplication. There are options to allow internal hardwired routing of each multiplier unit results to achieve partial-sum shifting as required to support above options. There is a redundant digit arithmetic adder before final outputs to support additions for partial sum accumulation, complex multiplication vector accumulation and general accumulation for FIRs/IIRs—giving MAC unit functionality. There are options controlled using bit fields in a control register passed to the multiplier unit as an operand. There are also options to generate all of the products needed for complex multiplication.
摘要翻译：本发明的实施例包括一对并行的16×16乘法器，每个乘法器具有两个32位输入和一个32位输出。有四种独立的8x8或两个独立的16x16乘法输入半字和字节选择的选项，复乘的实部和虚部，32x32乘法的部分和对，以及16x32乘法的部分和。有一些选项允许每个乘法器单元的内部连线布线结果实现部分和位移动，以支持上述选项。在最终输出之前有一个冗余数字运算加法器，以支持部分和累加的加法，复数乘法向量累加和FIR / IIR的一般累加 - 提供MAC单元功能。使用控制寄存器中的位域作为操作数传递给乘法器单元进行控制的选项。还可以选择生成复杂乘法所需的所有产品。

3. 发明授权

US07039795B2 System and method for using a two-stage multiplexing architecture for performing combinations of passing, rearranging, and duplicating operations on data 有权
标题翻译：用于使用两级复用架构来执行对数据的传递，重新排列和复制操作的组合的系统和方法
公开(公告)号：US07039795B2
公开(公告)日：2006-05-02
申请号：US10172221
申请日：2002-06-14
申请人： Keith Balmer , Karl M. Guttag , Amarjit Singh Bhandal
发明人： Keith Balmer , Karl M. Guttag , Amarjit Singh Bhandal
IPC分类号： G06F9/315
CPC分类号： G06F9/30032
摘要： A method for processing data using a multiplexing architecture includes performing a selected one of a plurality of first multiplexer operations on the data and then a selected one of a plurality of second multiplexer operations. The first multiplexer operations include a pass operation and a plurality of bit rearrangement operations. The second multiplexer operations include a pass operation and a plurality of bit duplication operations which duplicates a selected bit or bits to a corresponding block of contiguous bits in the output. A result is then generated that reflects the outputs produced by first and second multiplexers respectively.
摘要翻译：使用复用架构来处理数据的方法包括：对数据执行多个第一复用器操作中的所选择的一个，然后执行多个第二复用器操作中的所选择的一个。第一复用器操作包括通过操作和多个位重排操作。第二多路复用器操作包括将所选择的比特复制到输出中相应的连续比特块的通过操作和多个比特复制操作。然后产生分别反映由第一和第二多路复用器产生的输出的结果。

4. 发明授权

US06829696B1 Data processing system with register store/load utilizing data packing/unpacking 有权
标题翻译：数据处理系统，具有使用数据打包/打包的寄存器存储/负载
公开(公告)号：US06829696B1
公开(公告)日：2004-12-07
申请号：US09687540
申请日：2000-10-13
申请人： Keith Balmer , Karl M. Guttag , Lewis Nardini
发明人： Keith Balmer , Karl M. Guttag , Lewis Nardini
IPC分类号： G06F9312
CPC分类号： G06F9/30043 , G06F9/30032 , G06F9/30036 , G06F9/345 , G06F9/3824 , G06F9/3828 , G06F9/3853
摘要： A data processing system (e.g., microprocessor 30) for packing register data while storing it to memory and unpacking data read from memory while loading it into registers using single processor instructions. The system comprises a memory (42) and a central processing unit core (44) with at least one register file (76). The core is responsive to a load instruction (e.g., LDW_BH[U] instruction 184) to retrieve at least one data word from memory and parse the data word over selected parts of at least two data registers in the register file. The core is responsive to a store instruction (e.g., STBH_W instruction 198) to concatenate data from selected parts of at least two data registers into at least one data word and save the data word to memory. The number of data registers is greater than the number of data words parsed into or concatenated from the data registers. Both memory storage space and central processor unit resources are utilized efficiently when working with packed data. A single store or load instruction can perform all of the tasks that used to take several instructions, while at the same time conserving memory space.
摘要翻译：数据处理系统（例如，微处理器30），用于打包寄存器数据，同时将其存储到存储器并且解包从存储器读取的数据，同时使用单个处理器指令将其加载到寄存器中。该系统包括具有至少一个寄存器文件（76）的存储器（42）和中央处理单元核心（44）。核心响应于加载指令（例如LDW_BH [U]指令184））从存储器检索至少一个数据字，并且通过寄存器文件中的至少两个数据寄存器的选定部分解析数据字。核心响应于存储指令（例如，STBH_W指令198）将从至少两个数据寄存器的所选部分的数据连接到至少一个数据字中并将数据字保存到存储器。数据寄存器的数量大于从数据寄存器解析或级联的数据字数。当处理打包数据时，存储器存储空间和中央处理器单元资源都被有效利用。单个存储或加载指令可以执行用于执行多个指令的所有任务，同时节省内存空间。

5. 发明授权

US06314047B1 Low cost alternative to large dual port RAM 有权
标题翻译：低成本替代大型双端口RAM
公开(公告)号：US06314047B1
公开(公告)日：2001-11-06
申请号：US09713560
申请日：2000-11-15
申请人： John Keay , Iain Robertson , Karl M. Guttag , Keith Balmer
发明人： John Keay , Iain Robertson , Karl M. Guttag , Keith Balmer
IPC分类号： G11C800
CPC分类号： G11C11/412 , G11C8/16
摘要： Data transfer between multiple processor nodes and multiple static memory storage nodes is made more efficient using a wrapper of logic surrounding a conventional single port static memory function. The wrapper logic comprises FIFO devices which provide buffering between a given processor node and its associated memory function. The added buffering allows the design to trade allowable added read and write latency for a significant reduction in memory complexity. A single port random access memory structure enclosed within the wrapper provides the functional throughput advantage that only a dual port memory device would otherwise make possible.
摘要翻译：使用围绕常规单端口静态存储器功能的逻辑封装件，使多个处理器节点和多个静态存储器存储节点之间的数据传输变得更有效。封装逻辑包括提供给定处理器节点与其相关联的存储器功能之间的缓冲的FIFO设备。添加的缓冲允许设计交易允许的增加的读和写延迟，显着降低内存复杂性。包装在封装件中的单端口随机存取存储器结构提供了功能吞吐量优点，即只有双端口存储器件将成为可能。

6. 发明授权

US5651127A Guided transfers with variable stepping 失效
标题翻译：引导传输与可变步进
公开(公告)号：US5651127A
公开(公告)日：1997-07-22
申请号：US209123
申请日：1994-03-08
申请人： Robert J. Gove , Karl M. Guttag , Keith Balmer , Christopher J. Read , Iain Robertson , Nicholas Ing Simmons
发明人： Robert J. Gove , Karl M. Guttag , Keith Balmer , Christopher J. Read , Iain Robertson , Nicholas Ing Simmons
IPC分类号： G06F9/345 , G06F9/38 , G06F13/28 , G09G5/393 , G06F91/26 , G06F9/34 , G06F12/00 , G06F12/14
CPC分类号： G09G5/393 , G06F13/28 , G06F9/345 , G06F9/3879
摘要： This invention is a manner of control of the addresses of memory accesses. The data processing device of this invention includes a memory, a control circuit, a guide table and an address generating circuit. The control circuit receives a packet transfer request and packet transfer parameters. The packet transfer parameters include a start address, a number of guide table entries and a table pointer. The guide table includes guide table entries, each guide table entry having an address value and dimension values defining a block of addresses. The table pointer initially points to a first guide table entry in the guide table. The address generating circuit forms a set of block of addresses for memory access corresponding to each guide table entry, having a start address from a predetermined combination of the start address and the address value of the guide table entry. The block of addresses are formed from the dimension values. Following the memory accesses, the address generating circuit updates the table pointer to point to a next entry in the guide table. The address generating circuit may optionally form the predetermined combination of starting address and address value of guide table entry by adding the address value to the prior block starting address or by adding the guide table value to the starting address. The memory access may be a memory read from the block of addresses or a memory write to the block of addresses. In the preferred embodiment, memory, a data processor and a data transfer controller performing the above memory accesses is constructed in a single semiconductor chip. The data transfer controller may access external memory in the same manner as on-chip memory.
摘要翻译：本发明是对存储器存取地址的控制方式。本发明的数据处理装置包括存储器，控制电路，引导表和地址产生电路。控制电路接收分组传送请求和分组传送参数。分组传送参数包括起始地址，指导表条目的数目和表指针。指南表包括指南表条目，每个指南表条目具有定义地址块的地址值和维度值。表指针最初指向指南表中的第一个指南表项。地址生成电路形成与每个引导表条目相对应的用于存储器访问的地址块集合，具有来自引导表条目的起始地址和地址值的预定组合的起始地址。地址块由维度值形成。在存储器访问之后，地址产生电路更新表指针以指向指南表中的下一条目。地址产生电路可以通过将地址值添加到先前块开始地址或通过将引导表值添加到起始地址来可选地形成指南表入口的起始地址和地址值的预定组合。存储器访问可以是从地址块读取的存储器或写入地址块的存储器。在优选实施例中，执行上述存储器访问的存储器，数据处理器和数据传输控制器被构造在单个半导体芯片中。数据传输控制器可以以与片上存储器相同的方式访问外部存储器。

7. 再颁专利

USRE44190E1 Long instruction word controlling plural independent processor operations 有权
公开(公告)号：USRE44190E1
公开(公告)日：2013-04-30
申请号：US12580466
申请日：2009-10-16
申请人： Karl M. Guttag , Christopher Read , Keith Balmer
发明人： Karl M. Guttag , Christopher Read , Keith Balmer
IPC分类号： G06F7/52
CPC分类号： G06F7/53 , G06F7/57 , G06F9/30014 , G06F9/30032 , G06F9/30036 , G06F9/30145 , G06F9/30167 , G06F9/3851 , G06F9/3853 , G06F9/3867 , G06F9/3885 , G06F2207/382
摘要： A data processing apparatus including a multiplier unit forming a product from L bits of each two data buses of N bits each N is greater than L. The multiplier forms a N bit output having a first portion which is the L most significant bits of the of product and a second portion which is M other bits not including the L least significant bits of the product, where N is the sum of M and L. In the preferred embodiment the M other bits are derived from other bits of the two input data busses, such as the M other bits of the first input data bus. An arithmetic logic unit performs parallel operations (addition, subtraction, Boolean functions) controlled by the same instructions. This arithmetic logic unit is divisible into a selected number of sections for performing identical operations on independent sections of its inputs. The multiplier unit may form dual products from separate parts of the input data. A single instruction controlling both the multiplier unit and the arithmetic logic unit permits addition of dual products. The dual products are temporarily stored in a data register permitting the multiply and add operations to be pipelined. The dual products are formed in one data word and added by a rotate/mask and add operation in a three input arithmetic unit.

8. 发明授权

US5974539A Three input arithmetic logic unit with shifter and mask generator 失效
标题翻译：三输入算术逻辑单元，带移位器和掩码发生器
公开(公告)号：US5974539A
公开(公告)日：1999-10-26
申请号：US160298
申请日：1993-11-30
申请人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Phillip Moyse
发明人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Phillip Moyse
IPC分类号： G06F5/01 , G06F9/302 , G06F9/315
CPC分类号： G06F9/30167 , G06F5/015
摘要： A three input arithmetic logic unit (230) generates a combination of the three inputs that is selected by a function signal. The second input signal comes from a controllable shifter (235). The shift amount is a default shift amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the shifter (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the shift amount. The output of the shift (235) may be stored independently of the arithmetic logic unit (230) result. The third input signal comes from a multiplexer (233) that selects between an instruction specified immediate field, data recalled from a data register or a mask input from a mask generator (239). One preferred form of the mask has a number of right justified 1's corresponding to a mask input signal. This mask input signal may be the default shift amount or a predetermined number of the least significant bits of the third input signal as selected by a multiplexer. A second preferred form of the mask is selected one of the left most 1, the right most 1, the left most bit change or the right most bit change of a predetermined set of the least significant bits of data recalled from a data register.
摘要翻译：三输入算术逻辑单元（230）产生由功能信号选择的三个输入的组合。第二输入信号来自可控移位器（235）。移位量是存储在特殊数据寄存器中的默认偏移量，是从数据寄存器或零调用的预定数据位组。一个恒定源（236）连接到移位器（235）以提供“1”的多位数字信号。这允许产生形式2N的第二输入信号，其中N是移位量。移位（235）的输出可以独立于算术逻辑单元（230）结果存储。第三输入信号来自多路复用器（233），其在指定的指令字段，从数据寄存器调用的数据或从掩码生成器输入的掩码（239）之间进行选择。掩模的一个优选形式具有对应于掩模输入信号的许多右对齐1。该掩模输入信号可以是由多路复用器选择的第三输入信号的默认偏移量或预定数量的最低有效位。选择掩模的第二优选形式是从数据寄存器回调的数据的最低有效位的预定集合的最左1，最右1，最左位变化或最右位变化中的一个。

9. 发明授权

US5742538A Long instruction word controlling plural independent processor operations 失效
公开(公告)号：US5742538A
公开(公告)日：1998-04-21
申请号：US632785
申请日：1996-04-15
申请人： Karl M. Guttag , Christopher J. Read , Keith Balmer
发明人： Karl M. Guttag , Christopher J. Read , Keith Balmer
IPC分类号： G06F7/52 , G06F7/57 , G06F9/30 , G06F9/302 , G06F9/315 , G06F9/38
CPC分类号： G06F7/53 , G06F7/57 , G06F9/30014 , G06F9/30032 , G06F9/30036 , G06F9/30145 , G06F9/30167 , G06F9/3851 , G06F9/3853 , G06F9/3867 , G06F9/3885 , G06F2207/382
摘要： A data processing apparatus including a multiplier unit forming a product from L bits of each two data buses of N bits each N is greater than L. The multiplier forms a N bit output having a first portion which is the L most significant bits of the of product and a second portion which is M other bits not including the L least significant bits of the product, where N is the sum of M and L. In the preferred embodiment the M other bits are derived from other bits of the two input data busses, such as the M other bits of the first input data bus. An arithmetic logic unit performs parallel operations (addition, subtraction, Boolean functions) controlled by the same instructions. This arithmetic logic unit is divisible into a selected number of sections for performing identical operations on independent sections of its inputs. The multiplier unit may form dual products from separate parts of the input data. A single instruction controlling both the multiplier unit and the arithmetic logic unit permits addition of dual products. The dual products are temporarily stored in a data register permitting the multiply and add operations to be pipelined. The dual products are formed in one data word and added by a rotate/mask and add operation in a three input arithmetic unit.

10. 发明授权

US5724599A Message passing and blast interrupt from processor 失效
标题翻译：来自处理器的消息传递和爆炸中断
公开(公告)号：US5724599A
公开(公告)日：1998-03-03
申请号：US208171
申请日：1994-03-08
申请人： Keith Balmer , Karl M. Guttag , Robert J. Gove , Nicholas Ing-Simmons , Iain Robertson
发明人： Keith Balmer , Karl M. Guttag , Robert J. Gove , Nicholas Ing-Simmons , Iain Robertson
IPC分类号： G06F15/00 , G06F15/16
CPC分类号： G06F15/16
摘要： The invention involves communication within a multiprocessor system. The multiprocessor system includes a command word bus and a plurality of data processors. Each data processor is connected to the command word bus and includes a command circuit, a decoder and a reset control circuit. The command circuit may generate a command word on the command word bus including at least one reset command word for resetting a data processor. The decoder decodes command words received via the command word bus and includes at least a reset command decoder for decoding a reset command word. The reset control circuit resets the data processor into a state corresponding to initial application of electrical power upon receiving a reset command word. Each command word circuit generates command words indicating a particular data processor to which it is directed. Only a predetermined subset of the data processors may send the reset command word directed to other data processors. Additional actions such as interrupts, halt and cache memory flush may be controlled via the command word. In the preferred embodiment, a single command word may be directed to plural data processors. In the preferred embodiment, the command word bus and each of the data processors are disposed on a single semiconductor chip.
摘要翻译：本发明涉及多处理器系统内的通信。多处理器系统包括命令字总线和多个数据处理器。每个数据处理器连接到命令字总线，并包括命令电路，解码器和复位控制电路。命令电路可以在命令字总线上生成包括用于复位数据处理器的至少一个复位命令字的命令字。解码器解码通过命令字总线接收的命令字，并且至少包括用于对复位命令字进行解码的复位命令解码器。复位控制电路在接收到复位命令字时将数据处理器复位为与初始施加电力相对应的状态。每个命令字电路产生指示其所针对的特定数据处理器的命令字。只有数据处理器的预定子集可以发送定向到其他数据处理器的复位命令字。可以通过命令字来控制诸如中断，停止和高速缓冲存储器刷新等附加动作。在优选实施例中，单个命令字可以被引导到多个数据处理器。在优选实施例中，命令字总线和每个数据处理器设置在单个半导体芯片上。

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