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1. 发明授权

US07047284B1 Transfer request bus node for transfer controller with hub and ports 有权
标题翻译：用于具有集线器和端口的传输控制器的传输请求总线节点
公开(公告)号：US07047284B1
公开(公告)日：2006-05-16
申请号：US09713440
申请日：2000-11-15
申请人： Sanjive Agarwala , David A. Comisky , Charles L. Fuoco , Iain Robertson , David Hoyle , John Keay , Keith Balmer , Amarjit S. Bhandal , Christopher L. Mobley
发明人： Sanjive Agarwala , David A. Comisky , Charles L. Fuoco , Iain Robertson , David Hoyle , John Keay , Keith Balmer , Amarjit S. Bhandal , Christopher L. Mobley
IPC分类号： G06F15/177
CPC分类号： G06F13/37
摘要： A transfer request bus and transfer request bus node is described which is suitable for use in a data transfer controller processing multiple concurrent transfer requests despite the attendant collisions which result when conflicting transfer requests occur. Transfer requests are passed from an upstream transfer request node to downstream transfer request node and then to a transfer request controller with queue. At each node a local transfer request can also be inserted to be passed on to the transfer controller queue. Collisions at each transfer request node are resolved using a token passing scheme wherein a transfer request node possessing the token allows a local request to be inserted in preference to the upstream request.
摘要翻译：描述了转移请求总线和传送请求总线节点，其适用于处理多个并发转移请求的数据传输控制器，尽管在发生冲突的转移请求时产生了伴随的冲突。传输请求从上游传输请求节点传递到下游传输请求节点，然后传送到具有队列的传输请求控制器。在每个节点处，也可以插入本地传输请求以传递到传输控制器队列。使用令牌传递方案来解决每个传送请求节点处的冲突，其中拥有令牌的传送请求节点允许优先于上游请求插入本地请求。

2. 发明授权

US06868087B1 Request queue manager in transfer controller with hub and ports 有权
标题翻译：在具有集线器和端口的传输控制器中请求队列管理器
公开(公告)号：US06868087B1
公开(公告)日：2005-03-15
申请号：US09713609
申请日：2000-11-15
申请人： Sanjive Agarwala , Iain Robertson , David A. Comisky , Charles L. Fuoco , Christopher L. Mobley
发明人： Sanjive Agarwala , Iain Robertson , David A. Comisky , Charles L. Fuoco , Christopher L. Mobley
IPC分类号： H04B7/212 , H04L12/28 , H04L12/56
CPC分类号： H04L47/6215 , H04L47/50
摘要： A transfer controller with hub and ports is viewed as a communication hub between the various locations of a global memory map. A request queue manager serves as a crucial part of the transfer controller. The request queue manager receives these data transfer request packets from plural transfer requests nodes. The request queue manager sorts transfer request packets by their priority level and stores them in the queue manager memory. The request queue manager processes dispatches transfer request packets to a free data channel based upon priority level and first-in-first-out within priority level.
摘要翻译：具有集线器和端口的传输控制器被视为全局存储器映射的各个位置之间的通信集线器。请求队列管理器作为传输控制器的关键部分。请求队列管理器从多个传输请求节点接收这些数据传输请求分组。请求队列管理器按照优先级排序传输请求数据包，并将其存储在队列管理器内存中。请求队列管理器根据优先级和优先级别先进先出，处理将传送请求分组分派到空闲数据信道。

3. 发明授权

US06954468B1 Write allocation counter for transfer controller with hub and ports 有权
标题翻译：为集线器和端口传输控制器写入分配计数器
公开(公告)号：US06954468B1
公开(公告)日：2005-10-11
申请号：US09713423
申请日：2000-11-15
申请人： Sanjive Agarwala , Iain Robertson , David A. Comisky , Charles L. Fuoco
发明人： Sanjive Agarwala , Iain Robertson , David A. Comisky , Charles L. Fuoco
IPC分类号： G06F15/17 , H04J3/16
CPC分类号： G06F15/17
摘要： The transfer controller with hub and ports uses a write allocation counter and algorithm to control data reads from a source port. The write allocation count is the amount of data that can be consumed immediately by the write reservation station of a slow destination port and the channel data router buffers. This is used to throttle fast source port read operations to whole read bursts until space to adsorb the read data is available. This ensures that the source port response queue is not blocked with data that cannot be consumed by the channel data router and the slow destination port. This condition would otherwise block a fast source port from providing data to the other destination ports.
摘要翻译：具有集线器和端口的传输控制器使用写入分配计数器和算法来控制源端口的数据读取。写分配计数是缓慢目的地端口的写保留站和信道数据路由器缓冲器可以立即消耗的数据量。这用于将快速源端口读取操作限制为整个读取脉冲串，直到吸收读取数据的空间可用。这样可确保源端口响应队列不被通道数据路由器和缓慢目标端口不能使用的数据阻塞。否则，此条件将阻止快速源端口向其他目标端口提供数据。

4. 发明授权

US06654834B1 Method and apparatus for data transfer employing closed loop of memory nodes 有权
标题翻译：采用闭环存储器节点进行数据传输的方法和装置
公开(公告)号：US06654834B1
公开(公告)日：2003-11-25
申请号：US09615645
申请日：2000-07-13
申请人： Iain Robertson , John Keay , Amarjit S. Bhandal , Keith Balmer
发明人： Iain Robertson , John Keay , Amarjit S. Bhandal , Keith Balmer
IPC分类号： G06F100
CPC分类号： G06F15/173
摘要： Data transfer between a master node (300) and plural memory nodes (301-308) follows a synchronous fixed latency loop bus (255). Each memory node includes bus interface (311-318) which passes command, write data, address and read data to a next memory node in the loop. Each memory node performs a read from its memory at the specified address if a read command is directed to it. Each memory node performs a write to its memory at the specified address if a write command is directed to it. This configuration provides a fixed latency between the issue of a read command and the return of the read data no matter which memory node is accessed. This configuration prevents collision of returning read data. This configuration retains the issued read and write order preserving proper function for read/write and write/read command pairs. This configuration provides fixed loading to each stage regardless of the number of memory nodes. Thus the design of large systems operating at high speeds is simplified.
摘要翻译：主节点（300）和多个存储节点（301-308）之间的数据传输遵循同步固定等待时间环路总线（255）。每个存储器节点包括总线接口（311-318），其将命令，写入数据，地址和读取数据传递给循环中的下一个存储器节点。如果读取命令被指向，则每个存储器节点在指定的地址处从其存储器执行读取。如果写入命令被指向，则每个存储器节点对指定地址的存储器执行写操作。无论访问哪个存储器节点，此配置都会在发出读命令和读取数据的返回之间提供固定的等待时间。该配置可以防止返回的读取数据发生冲突。该配置保留发出的读写顺序保持读/写和写/读命令对的正确功能。该配置为每个阶段提供固定加载，而不管存储器节点的数量。因此，简化了以高速运行的大型系统的设计。

5. 发明授权

US06658503B1 Parallel transfer size calculation and annulment determination in transfer controller with hub and ports 有权
标题翻译：具有集线器和端口的传输控制器的并行传输大小计算和废止确定
公开(公告)号：US06658503B1
公开(公告)日：2003-12-02
申请号：US09713611
申请日：2000-11-15
申请人： Sanjive Agarwala , Iain Robertson , David A. Comisky
发明人： Sanjive Agarwala , Iain Robertson , David A. Comisky
IPC分类号： G06F1314
CPC分类号： G06F13/28
摘要： The transfer controller with hub and ports originally developed as a communication hub between the various locations of a global memory map within the DSP is described. Using the technique of this invention, parallel size calculation/write annulment decision capability is employed. This technique facilitates the process of setting up complex transfers without risking brute force inefficient processor cycles. Annulment determination allows detection of cases when a set of data cannot be output immediately and the destination pipeline postpones execution of the write command.
摘要翻译：描述了最初开发为DSP内的全局存储器映射的各个位置之间的通信集线器的端口和端口的传送控制器。使用本发明的技术，采用并行大小计算/写入废止决定能力。这种技术有助于建立复杂传输的过程，而不会产生强力的低效处理器周期。当一组数据不能立即输出并且目标流水线推迟写入命令的执行时，废止确定允许检测情况。

6. 发明授权

US06651083B1 Distributed service request system for providing fair arbitration using token passing scheme to resolve collisions 有权
标题翻译：分布式服务请求系统，通过令牌通过方案提供公平仲裁，以解决冲突
公开(公告)号：US06651083B1
公开(公告)日：2003-11-18
申请号：US09615172
申请日：2000-07-13
申请人： Iain Robertson , Amarjit S. Bhandal , John Keay
发明人： Iain Robertson , Amarjit S. Bhandal , John Keay
IPC分类号： G06F1336
CPC分类号： H04L12/417 , G06F13/37
摘要： A transfer request bus (25) is described which is suitable for use in a data transfer controller processing, multiple concurrent transfer requests despite the attendant collisions which result when conflicting transfer requests occur. Transfer requests are passed from an upstream transfer request node (318) to downstream transfer request node (300) and thence to a transfer request controller with queue (320). At each node a local transfer request can also be inserted to be passed on to the transfer controller queue. Collisions at each transfer request node are resolved using a token passing scheme wherein a transfer request node possessing the token allows a local request to be inserted in preference to the upstream request.
摘要翻译：描述了适用于数据传输控制器处理的传送请求总线（25），尽管在发生冲突的转移请求时导致伴随的冲突，但是多个并发传输请求。传输请求从上游传送请求节点（318）传递到下游传送请求节点（300），然后传送到具有队列（320）的传送请求控制器。在每个节点处，也可以插入本地传输请求以传递到传输控制器队列。使用令牌传递方案来解决每个传送请求节点处的冲突，其中拥有令牌的传送请求节点允许优先于上游请求插入本地请求。

7. 发明授权

US06681270B1 Effective channel priority processing for transfer controller with hub and ports 有权
标题翻译：具有集线器和端口的传输控制器的有效信道优先级处理
公开(公告)号：US06681270B1
公开(公告)日：2004-01-20
申请号：US09713563
申请日：2000-11-15
申请人： Sanjive Agarwala , Iain Robertson , David A. Comisky
发明人： Sanjive Agarwala , Iain Robertson , David A. Comisky
IPC分类号： G06F300
CPC分类号： G06F13/387
摘要： A data transfer controller with hub and ports uses an effective channel priority processing technique and algorithm. Data transfer requests are queued in a first-in-first-out fashion at the data source ports. Each data transfer request has a priority level for execution. In effective channel priority processing the priority level assigned to a source port is the greatest priority level of any data transfer request in the corresponding first-in-first-out queue. This techniques prevents a low priority data transfer request at the output of a source port queue from blocking a higher priority data transfer request further back in the queue. Raising the priority of all data transfer requests within a source port queue enables the low priority data transfer request to complete enabling the high priority data transfer request to be reached. Thus both the low priority data transfer request and the high priority data transfer request in the queue of a single port are serviced before intermediate priority data transfer requests at the output of other source port queues.
摘要翻译：具有集线器和端口的数据传输控制器使用有效的信道优先级处理技术和算法。数据传输请求在数据源端口以先进先出的方式排队。每个数据传输请求具有执行的优先级。在有效的信道优先级处理中，分配给源端口的优先级是相应的先进先出队列中任何数据传输请求的最高优先级。该技术防止在源端口队列的输出端的低优先级数据传输请求阻塞更高优先级的数据传输请求进一步返回到队列中。提高源端口队列内所有数据传输请求的优先级使得能够实现低优先级数据传输请求，从而能够实现高优先级的数据传输请求。因此，在其他源端口队列的输出处的中间优先级数据传输请求之前，对单个端口的队列中的低优先级数据传输请求和高优先级数据传输请求进行服务。

8. 发明授权

US06654819B1 External direct memory access processor interface to centralized transaction processor 有权
标题翻译：外部直接存储器访问处理器接口集中在事务处理器
公开(公告)号：US06654819B1
公开(公告)日：2003-11-25
申请号：US09603332
申请日：2000-06-26
申请人： David A. Comisky , Iain Robertson , Sanjive Agarwala
发明人： David A. Comisky , Iain Robertson , Sanjive Agarwala
IPC分类号： G06F300
CPC分类号： G06F13/30
摘要： An external direct memory access unit includes an event recognizer recognizing plural event types, a priority encoder selecting for service one recognized external event, a parameter memory storing service request parameters corresponding to each event type and an external direct memory access controller recalling service request parameters from the parameter memory corresponding to recognized events and submitting them to a centralized transaction processor. The service request parameters include a priority for centralized transaction processor independent of the event recognition priority. The service request parameters may be stored in the form of a linked list. The service requests are preferably direct memory accesses which may include writes to the parameter memory for self modification. The centralized transaction processor may signal an event to event recognizer upon completion of a requested data transfer.
摘要翻译：外部直接存储器访问单元包括识别多个事件类型的事件识别器，选择服务一个识别的外部事件的优先级编码器，存储与每个事件类型相对应的服务请求参数的参数存储器以及从外部直接存储器访问控制器召回服务请求参数参数存储器对应于识别的事件并将其提交给集中式事务处理器。服务请求参数包括独立于事件识别优先级的集中式事务处理器的优先级。服务请求参数可以以链表的形式存储。服务请求优选地是直接存储器访问，其可以包括对参数存储器的写入以进行自修改。在完成所请求的数据传输之后，集中式事务处理器可以向事件识别器通知事件。

9. 发明授权

US06314047B1 Low cost alternative to large dual port RAM 有权
标题翻译：低成本替代大型双端口RAM
公开(公告)号：US06314047B1
公开(公告)日：2001-11-06
申请号：US09713560
申请日：2000-11-15
申请人： John Keay , Iain Robertson , Karl M. Guttag , Keith Balmer
发明人： John Keay , Iain Robertson , Karl M. Guttag , Keith Balmer
IPC分类号： G11C800
CPC分类号： G11C11/412 , G11C8/16
摘要： Data transfer between multiple processor nodes and multiple static memory storage nodes is made more efficient using a wrapper of logic surrounding a conventional single port static memory function. The wrapper logic comprises FIFO devices which provide buffering between a given processor node and its associated memory function. The added buffering allows the design to trade allowable added read and write latency for a significant reduction in memory complexity. A single port random access memory structure enclosed within the wrapper provides the functional throughput advantage that only a dual port memory device would otherwise make possible.
摘要翻译：使用围绕常规单端口静态存储器功能的逻辑封装件，使多个处理器节点和多个静态存储器存储节点之间的数据传输变得更有效。封装逻辑包括提供给定处理器节点与其相关联的存储器功能之间的缓冲的FIFO设备。添加的缓冲允许设计交易允许的增加的读和写延迟，显着降低内存复杂性。包装在封装件中的单端口随机存取存储器结构提供了功能吞吐量优点，即只有双端口存储器件将成为可能。

10. 发明授权

US06839831B2 Data processing apparatus with register file bypass 有权
标题翻译：具有寄存器文件旁路的数据处理设备
公开(公告)号：US06839831B2
公开(公告)日：2005-01-04
申请号：US09733597
申请日：2000-12-08
申请人： Keith Balmer , Richard D. Simpson , Iain Robertson , John Keay
发明人： Keith Balmer , Richard D. Simpson , Iain Robertson , John Keay
IPC分类号： G06F9/30 , G06F9/302 , G06F9/355 , G06F9/38 , G06F9/28
CPC分类号： G06F9/3885 , G06F9/3001 , G06F9/3012 , G06F9/355 , G06F9/3824 , G06F9/3828 , G06F9/3891
摘要： A data processing apparatus includes first (78) and second (80) functional unit groups, each includes a plurality of functional units and a register file (76) comprising a plurality of registers. A comparator (181) receives the operand register number of a current instruction for a functional unit in the first functional unit group, and the destination register number of an immediately preceding instruction for the second functional unit group. A register file bypass multiplexer (174) selects the data from the register corresponding to the operand number of the current instruction on no match and selects the output of the second functional unit group (hotpath 172) if the comparator indicates a match. The first functional unit utilizes the output of the second functional unit group without waiting for the result to be stored in the register file.
摘要翻译：数据处理装置包括第一（78）和第二（80）个功能单元组，每个功能单元组包括多个功能单元和包括多个寄存器的寄存器文件（76）。比较器（181）接收第一功能单元组中的功能单元的当前指令的操作数寄存器号和第二功能单元组的紧接在前的指令的目的地寄存器号。寄存器文件旁路多路复用器（174）在不匹配的情况下从当前指令的操作数编号对应的寄存器中选择数据，如果比较器指示匹配，则选择第二功能单元组（热路径172）的输出。第一功能单元利用第二功能单元组的输出，而不等待结果存储在寄存器文件中。

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