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1. 发明授权

US06711602B1 Data processor with flexible multiply unit 有权
标题翻译：数据处理器具有灵活的乘法单元
公开(公告)号：US06711602B1
公开(公告)日：2004-03-23
申请号：US09703093
申请日：2000-10-31
申请人： Amarjit Singh Bhandal , Keith Balmer , David Hoyle , Karl M. Guttag , Zahid Hussain
发明人： Amarjit Singh Bhandal , Keith Balmer , David Hoyle , Karl M. Guttag , Zahid Hussain
IPC分类号： G06F752
CPC分类号： G06F9/30014 , G06F9/3853
摘要： An embodiment of the invention includes a pair of parallel 16×16 multipliers each with two 32-bit inputs and one 32-bit output. There are options to allow input halfword and byte selection for four independent 8×8 or two independent 16×16 multiplications, real and imaginary parts of comple×multiplication, pairs of partial sums for 32×32 multiplication, and partial sums for 16×32 multiplication. There are options to allow internal hardwired routing of each multiplier unit results to achieve partial-sum shifting as required to support above options. There is a redundant digit arithmetic adder before final outputs to support additions for partial sum accumulation, complex multiplication vector accumulation and general accumulation for FIRs/IIRs—giving MAC unit functionality. There are options controlled using bit fields in a control register passed to the multiplier unit as an operand. There are also options to generate all of the products needed for complex multiplication.
摘要翻译：本发明的实施例包括一对并行的16×16乘法器，每个乘法器具有两个32位输入和一个32位输出。有四种独立的8x8或两个独立的16x16乘法输入半字和字节选择的选项，复乘的实部和虚部，32x32乘法的部分和对，以及16x32乘法的部分和。有一些选项允许每个乘法器单元的内部连线布线结果实现部分和位移动，以支持上述选项。在最终输出之前有一个冗余数字运算加法器，以支持部分和累加的加法，复数乘法向量累加和FIR / IIR的一般累加 - 提供MAC单元功能。使用控制寄存器中的位域作为操作数传递给乘法器单元进行控制的选项。还可以选择生成复杂乘法所需的所有产品。

2. 发明授权

US06754809B1 Data processing apparatus with indirect register file access 有权
标题翻译：具有间接寄存器文件访问的数据处理设备
公开(公告)号：US06754809B1
公开(公告)日：2004-06-22
申请号：US09713442
申请日：2000-11-15
申请人： Karl M. Guttag , David Hoyle , Keith Balmer
发明人： Karl M. Guttag , David Hoyle , Keith Balmer
IPC分类号： G06F934
CPC分类号： G06F9/3012 , G06F9/3004 , G06F9/30098 , G06F9/35 , G06F9/383
摘要： A data processing apparatus which uses a register file to provide a faster alternative to indirect memory addressing. A functional unit is connected to a data register file (76) which comprises a plurality of registers, each of which is accessed by a corresponding register number. The functional unit (e.g., A-unit 78) can execute at least one indirect register access instruction that comprises an operand register number field. Instruction decode circuitry, connected to the register file and the functional unit, is responsive to the indirect register access instruction to recall data stored in an operand register (190) specified by the operand register number in the instruction, identify the recalled data as a register access number, and recall operand data from a data register corresponding to the register access number for use as an operand by the functional unit. Indirect register addressing permits the apparatus to more quickly execute table look up intensive algorithms, such as variable length decoding, than an apparatus employing only indirect memory addressing.
摘要翻译：一种使用寄存器文件来提供间接存储器寻址的更快替代的数据处理装置。功能单元连接到数据寄存器文件（76），数据寄存器文件（76）包括多个寄存器，每个寄存器都由对应的寄存器号码访问。功能单元（例如，A单元78）可以执行包括操作数寄存器号字段的至少一个间接寄存器访问指令。连接到寄存器文件和功能单元的指令解码电路响应于间接寄存器访问指令来调用存储在指令中由操作数寄存器号指定的操作数寄存器（190）中的数据，将调用的数据标识为寄存器访问号码，并且从与寄存器访问号相对应的数据寄存器中调用操作数数据，以用作功能单元的操作数。间接寄存器寻址允许装置比仅使用间接存储器寻址的装置更快速地执行表查找密集型算法，例如可变长度解码。

3. 发明授权

US06745319B1 Microprocessor with instructions for shuffling and dealing data 有权
标题翻译：具有混洗和交易数据指令的微处理器
公开(公告)号：US06745319B1
公开(公告)日：2004-06-01
申请号：US09702452
申请日：2000-10-31
申请人： Keith Balmer , David Hoyle , Lewis Nardini
发明人： Keith Balmer , David Hoyle , Lewis Nardini
IPC分类号： G06F9305
CPC分类号： G06F9/3891 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30072 , G06F9/30109 , G06F9/30112 , G06F9/3012 , G06F9/3828 , G06F9/3885
摘要： A data processing system is provided with a digital signal processor (DSP) which has a shuffle instruction for shuffling a source operand (600) and storing the shuffled result in a selected destination register (610). A shuffled result is formed by interleaving bits from a first source operand portion with bits from a second operand portion. A de-interleave and pack (DEAL) instruction is provided for de-interleaving a source operand. The shuffle instruction and the DEAL instruction have an exactly inverse effect. The DSP includes swizzle circuitry that performs interleaving or de-interleaving in a single execution phase.
摘要翻译：数据处理系统具有数字信号处理器（DSP），数字信号处理器（DSP）具有用于混洗源操作数（600）并将洗牌结果存储在所选目的地寄存器（610）中的混洗指令。通过从来自第二操作数部分的位与第一源操作数部分交织比特来形成混洗结果。提供去交错和包（DEAL）指令用于解交织源操作数。随机播放指令和DEAL指令具有完全相反的效果。 DSP包括在单个执行阶段执行交织或解交织的交换电路。

4. 发明授权

US07047284B1 Transfer request bus node for transfer controller with hub and ports 有权
标题翻译：用于具有集线器和端口的传输控制器的传输请求总线节点
公开(公告)号：US07047284B1
公开(公告)日：2006-05-16
申请号：US09713440
申请日：2000-11-15
申请人： Sanjive Agarwala , David A. Comisky , Charles L. Fuoco , Iain Robertson , David Hoyle , John Keay , Keith Balmer , Amarjit S. Bhandal , Christopher L. Mobley
发明人： Sanjive Agarwala , David A. Comisky , Charles L. Fuoco , Iain Robertson , David Hoyle , John Keay , Keith Balmer , Amarjit S. Bhandal , Christopher L. Mobley
IPC分类号： G06F15/177
CPC分类号： G06F13/37
摘要： A transfer request bus and transfer request bus node is described which is suitable for use in a data transfer controller processing multiple concurrent transfer requests despite the attendant collisions which result when conflicting transfer requests occur. Transfer requests are passed from an upstream transfer request node to downstream transfer request node and then to a transfer request controller with queue. At each node a local transfer request can also be inserted to be passed on to the transfer controller queue. Collisions at each transfer request node are resolved using a token passing scheme wherein a transfer request node possessing the token allows a local request to be inserted in preference to the upstream request.
摘要翻译：描述了转移请求总线和传送请求总线节点，其适用于处理多个并发转移请求的数据传输控制器，尽管在发生冲突的转移请求时产生了伴随的冲突。传输请求从上游传输请求节点传递到下游传输请求节点，然后传送到具有队列的传输请求控制器。在每个节点处，也可以插入本地传输请求以传递到传输控制器队列。使用令牌传递方案来解决每个传送请求节点处的冲突，其中拥有令牌的传送请求节点允许优先于上游请求插入本地请求。

5. 发明申请

US20110029756A1 Method and System for Decoding Low Density Parity Check Codes 有权
标题翻译：解密低密度奇偶校验码的方法和系统
公开(公告)号：US20110029756A1
公开(公告)日：2011-02-03
申请号：US12510899
申请日：2009-07-28
申请人： Eric Biscondi , David Hoyle , Tod David Wolf
发明人： Eric Biscondi , David Hoyle , Tod David Wolf
IPC分类号： H03M13/05 , G06F15/80 , G06F9/02 , G06F11/10
CPC分类号： H03M13/116 , H03M13/1114 , H03M13/1117 , H03M13/112 , H03M13/1165 , H03M13/1188 , H03M13/3715 , H03M13/3723 , H03M13/3753 , H03M13/47 , H03M13/616 , H03M13/6544 , H03M13/658 , H03M13/6583
摘要： A method for decoding a codeword in a data stream encoded according to a low density parity check (LDPC) code having an m×j parity check matrix H by initializing variable nodes with soft values based on symbols in the codeword, wherein a graph representation of H includes m check nodes and j variable nodes, and wherein a check node m provides a row value estimate to a variable node j and a variable node j provides a column value estimate to a check node m if H(m,j) contains a 1, computing row value estimates for each check node, wherein amplitudes of only a subset of column value estimates provided to the check node are computed, computing soft values for each variable node based on the computed row value estimates, determining whether the codeword is decoded based on the soft values, and terminating decoding when the codeword is decoded.
摘要翻译：一种用于根据具有m×j个奇偶校验矩阵H的低密度奇偶校验（LDPC）码编码的数据流中的码字进行解码的方法，通过基于码字中的符号来初始化具有软值的可变节点，其中，图形表示 H包括m个校验节点和j个变量节点，并且其中校验节点m向变量节点j提供行值估计，并且如果H（m，j）包含校验节点j，变量节点j向校验节点m提供列值估计 1，计算每个校验节点的行值估计，其中仅计算提供给校验节点的列值估计的子集的幅度，基于所计算的行值估计来计算每个变量节点的软值，确定码字是否被解码基于软值，并且当码字被解码时终止解码。

6. 发明申请

US20070111838A1 TRANSMISSION 审中-公开
标题翻译：传输
公开(公告)号：US20070111838A1
公开(公告)日：2007-05-17
申请号：US11551163
申请日：2006-10-19
申请人： Simon Evans , David Hoyle
发明人： Simon Evans , David Hoyle
IPC分类号： F16H3/72
CPC分类号： F16H3/725 , B60K1/02 , B60K6/365 , B60K6/405 , B60K6/442 , B60K6/445 , Y02T10/6234 , Y02T10/6239
摘要： A transmission including a first input member which in use is rotatably driven by a first prime mover, a second input member which in use is rotatably driven by a second prime mover, a rotatable output member from which drive is provided to a driven structure, the first input member driving a driven member and there being a drivable member drivable by the second input member, the driven member and the drivable member being coupled though an intermediate structure which carries the output member, drive being transmitted from the first input member to the output member when torque is input to the second input member from the second prime mover, and wherein the second prime mover is an electrically driven switched reluctance motor.
摘要翻译：一种变速器，包括在使用中由第一原动机旋转地驱动的第一输入构件，在使用中的第二输入构件由第二原动机可旋转地驱动，可旋转的输出构件，驱动装置从驱动结构提供，第一输入构件驱动从动构件，并且存在可由第二输入构件驱动的可驱动构件，从动构件和可驱动构件通过承载输出构件的中间结构联接，驱动从第一输入构件传递到输出当所述第二原动机的扭矩从所述第二输入构件输入时，所述第二原动机是电驱动的开关磁阻电动机。

7. 发明授权

US06691240B1 System and method of implementing variabe length delay instructions, which prevents overlapping lifetime information or values in efficient way 有权
标题翻译：实现可变长度延迟指令的系统和方法，以有效的方式防止重叠的生命周期信息或值
公开(公告)号：US06691240B1
公开(公告)日：2004-02-10
申请号：US09702518
申请日：2000-10-31
申请人： Eric J. Stotzer , David Hoyle , Joseph Zbiciak
发明人： Eric J. Stotzer , David Hoyle , Joseph Zbiciak
IPC分类号： H04L500
CPC分类号： G06F9/3875 , G06F9/30014 , G06F9/3555 , G06F9/3824 , G06F9/3828 , G06F9/3853 , G06F9/3867 , G06F9/3885 , G06F9/3891
摘要： A method for implementing a variable length delay instruction includes the steps of designating a source register for holding information and designating a destination register for retrieving the information. A first number of cycles before retrieval of the information to the destination register then is determined, and the information is transferred from the source register to delaying device, such as queuing device, for the first number of cycles. Finally, the information is written from the delaying device to the destination register. An apparatus for implementing variable length delay instructions includes an input line for reading information from a source register; delaying device for receiving said information read from the source register; a multiplexer; and a select line. A trigger signal is transmitted to the multiplexer, thereby instructing the multiplexer to write the information to a destination register.
摘要翻译：一种用于实现可变长度延迟指令的方法包括以下步骤：指定用于保存信息的源寄存器，并指定用于检索信息的目的地寄存器。确定在将信息检索到目的地寄存器之前的第一个周期数，并且将信息从源寄存器传送到诸如排队设备的延迟设备，用于第一个周期数。最后，将信息从延迟装置写入目的寄存器。用于实现可变长度延迟指令的装置包括用于从源寄存器读取信息的输入线; 用于接收从所述源寄存器读取的所述信息的延迟装置; 多路复用器和选择行。触发信号被发送到多路复用器，从而指示多路复用器将信息写入目的寄存器。

8. 发明授权

US06474439B1 Dipole logging tool 有权
标题翻译：偶极测井工具
公开(公告)号：US06474439B1
公开(公告)日：2002-11-05
申请号：US09537836
申请日：2000-03-29
申请人： David Hoyle , Hitoshi Tashiro , Benoit Froelich , Alain Brie , Hiroshi Hori , Hitoshi Sugiyama , Jahir Pabon , Frank Morris
发明人： David Hoyle , Hitoshi Tashiro , Benoit Froelich , Alain Brie , Hiroshi Hori , Hitoshi Sugiyama , Jahir Pabon , Frank Morris
IPC分类号： G01V140
CPC分类号： G01V1/52
摘要： A logging tool having a tool body, which can be positioned in a fluid-filled borehole, including a receiver section and a dipole transmitter; wherein the dipole transmitter includes a transducer with a shell having a reaction mass and a motor located therein, the motor operatively connecting the shell and the reaction mass such that only an outer surface of the shell is in contact with the fluid in the borehole. This new type of dipole source for well logging involves shaking all or part (axially) of a dipole tool body to produce a pure, broadband acoustic dipole signal while at the same time coupling as little energy as possible into the tool body. Important variations on this idea include a linear phased array of shaker sources, and active cancellation of tool borne noise.
摘要翻译：一种具有工具主体的测井工具，该工具主体可定位在充满流体的钻孔中，包括接收器部分和偶极发射器; 其中所述偶极发射器包括具有壳体的换能器，所述壳体具有反作用物质和位于其中的马达，所述马达可操作地连接所述壳体和所述反作用物质，使得只有所述壳体的外表面与所述钻孔中的流体接触。这种用于测井的新型偶极子源涉及摇动偶极工具体的全部或部分（轴向），以产生纯的宽带声偶极子信号，同时将尽可能少的能量耦合到工具主体中。这个想法的重要变化包括振荡器源的线性相控阵列，以及主动消除工具噪声。

9. 发明授权

US06834338B1 Microprocessor with branch-decrement instruction that provides a target and conditionally modifies a test register if the register meets a condition 有权
标题翻译：具有分支递减指令的微处理器，如果寄存器满足条件，则提供目标并有条件地修改测试寄存器
公开(公告)号：US06834338B1
公开(公告)日：2004-12-21
申请号：US09703144
申请日：2000-10-31
申请人： David Hoyle , Timothy D. Anderson
发明人： David Hoyle , Timothy D. Anderson
IPC分类号： G06F932
CPC分类号： G06F9/30145 , G06F9/30072 , G06F9/3012 , G06F9/30167 , G06F9/322 , G06F9/325
摘要： A data processing system is provided with a digital signal processor which has an instruction for conditionally branching based on the contents of a specified test register. Each time a branch is taken, the register is decremented as a side effect of executing the branch instruction. In addition, a predicate register is specified by the instruction. A branch occurs only if both registers meet specified conditions.
摘要翻译：数据处理系统具有数字信号处理器，该数字信号处理器具有基于指定测试寄存器的内容进行有条件分支的指令。每次采取分支时，寄存器作为执行分支指令的副作用而递减。另外，指令指定谓词寄存器。只有当两个寄存器满足指定条件时才会发生分支。

10. 发明授权

US06574724B1 Microprocessor with non-aligned scaled and unscaled addressing 有权
标题翻译：具有非对齐缩放和非缩放寻址的微处理器
公开(公告)号：US06574724B1
公开(公告)日：2003-06-03
申请号：US09702474
申请日：2000-10-31
申请人： David Hoyle , Joseph R. Zbiciak , Jeremiah E. Golston
发明人： David Hoyle , Joseph R. Zbiciak , Jeremiah E. Golston
IPC分类号： G06F1200
CPC分类号： G06F9/3828 , G06F9/30181 , G06F9/3555
摘要： A data processing system having a central processing (CPU) unit and a method of operation is provided. The CPU has an instruction set architecture that is optimized for intensive numeric algorithm processing. The CPU has dual load/store units connected to dual memory target ports of a memory controller. The CPU can execute two aligned data transfers each having a length of one byte, two bytes, four bytes, or eight bytes in parallel by executing two load/store instructions. The CPU can also execute a single non-aligned data transfer having a length of four bytes or eight bytes by executing a non-aligned load/store instruction that utilizes both memory target ports. A data transfer address for each load/store instruction is formed by fetching the instruction, decoding the instruction to determine instruction type, transfer data size, and scaling selection, selectively scaling an offset provided by the instruction and combining the selectively scaled offset with a base address value. The resultant address is then provided to the memory system to initiate a data transfer.
摘要翻译：提供具有中央处理（CPU）单元和操作方法的数据处理系统。 CPU具有针对密集数值算法处理进行了优化的指令集体系结构。 CPU具有连接到存储器控制器的双存储器目标端口的双重加载/存储单元。 CPU可以通过执行两个加载/存储指令来并行执行两个对齐的数据传输，每个数据传输具有一个字节，两个字节，四个字节或八个字节的长度。 CPU还可以通过执行利用两个存储器目标端口的不对齐的加载/存储指令来执行长度为四字节或八字节的单个非对齐数据传输。每个加载/存储指令的数据传输地址通过取指令，解码指令来确定指令类型，传输数据大小和缩放选择来形成，选择性地缩放由指令提供的偏移量，并将选择性缩放的偏移量与基数地址值。然后将结果地址提供给存储器系统以发起数据传送。

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