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    • 3. 发明授权
    • Method and apparatus for source synchronous data transfer
    • 源同步数据传输的方法和装置
    • US06178206B1
    • 2001-01-23
    • US09013479
    • 1998-01-26
    • Timothy W. KellyStephen S. PawlowskiKeith M. SelfJeffrey E. Smith
    • Timothy W. KellyStephen S. PawlowskiKeith M. SelfJeffrey E. Smith
    • H04L2500
    • H04L7/0331H04L7/0008
    • A method and apparatus is presented where for transmitting data between two or more components. Data signals are sent in parallel with a clocking signal (e.g., on a bus) so that the data signal can be latched in relation to the clocking signal. For example, two clocking signals, out of phase from each other by 180 degrees, can be sent on bidirectional clocking signal lines and data signals can be sent on a data signal line, the component receiving the clocking and data signals can latch the data signals on each high-to-low transition of either of the two clocking signals. Using the method and apparatus of the present invention, skew problems seen with other bus systems can be reduced which leads to an increase in data transfer rates.
    • 提出了一种用于在两个或更多个组件之间传输数据的方法和装置。 数据信号与时钟信号(例如,总线)并行地发送,使得可以相对于时钟信号锁存数据信号。 例如,可以在双向时钟信号线上发送彼此异相180度的两个时钟信号,并且数据信号可以在数据信号线上发送,接收时钟和数据信号的组件可以锁存数据信号 在两个时钟信号中的任一个的每个从高到低的转换。 使用本发明的方法和装置,可以减少其他总线系统所看到的偏斜问题,这导致数据传输速率的增加。
    • 4. 发明授权
    • Multiple internal phase-locked loops for synchronization of chipset
components and subsystems operating at different frequencies
    • 用于同步芯片组件和不同频率工作的子系统的多个内部锁相环
    • US6047383A
    • 2000-04-04
    • US12479
    • 1998-01-23
    • Keith M. SelfJeffrey E. SmithKeng L. Wong
    • Keith M. SelfJeffrey E. SmithKeng L. Wong
    • G06F1/12
    • G06F1/12
    • Methods and apparatus for easing design constraints with respect to placement of computer system components and subsystems requiring relative synchronicity at different frequencies is described. In one embodiment the apparatus includes a first phase-locked loop (PLL) formed on an integrated circuit die. A reference clock signal pin is coupled to the first PLL by a path of electrical length L1 for propagating a reference clock signal to the first PLL. A first PLL feedback pin is coupled to the first PLL by a path of electrical length L2, wherein L1.apprxeq.L2. The apparatus includes a programmable counter coupled to the reference clock signal pin, the programmable counter providing a divided reference clock signal to the first PLL. In one embodiment, the method includes the step of providing a reference clock signal to a plurality of PLLs residing within a same integrated circuit. The outputs of at least some of the PLLs are coupled to corresponding output pins of the integrated circuit. The following steps are performed for each selected output pin coupled to provide a synchronized clock signal at the end of a propagation trace: a) determining an electrical length of the propagation trace; and b) providing a feedback trace from the output pin to a feedback pin of the corresponding PLL, wherein the feedback trace is a same electrical length as the propagation trace. A divided-by-n reference clock signal is then provided to at least one of the PLLs, wherein n is not equal to 1.
    • 描述了关于在不同频率下需要相对同步性的计算机系统组件和子系统的放置的宽松设计约束的方法和装置。 在一个实施例中,该装置包括形成在集成电路管芯上的第一锁相环(PLL)。 参考时钟信号引脚通过电长度L1的路径耦合到第一PLL,以将参考时钟信号传播到第一PLL。 第一PLL反馈引脚通过电长度L2的路径耦合到第一PLL,其中L1 APPROX L2。 该装置包括耦合到参考时钟信号引脚的可编程计数器,该可编程计数器向第一PLL提供划分的基准时钟信号。 在一个实施例中,该方法包括向驻留在同一集成电路中的多个PLL提供参考时钟信号的步骤。 至少一些PLL的输出耦合到集成电路的相应输出引脚。 对于耦合以在传播轨迹结束时提供同步时钟信号的每个选择的输出引脚执行以下步骤:a)确定传播轨迹的电长度; 以及b)提供从所述输出引脚到相应PLL的反馈引脚的反馈迹线,其中所述反馈迹线与所述传播迹线具有相同的电长度。 然后,将一个分频参考时钟信号提供给至少一个PLL,其中n不等于1。
    • 5. 发明授权
    • Analog compensation circuitry for integrated circuit input/output
circuitry
    • 用于集成电路输入/输出电路的模拟补偿电路
    • US06025792A
    • 2000-02-15
    • US12478
    • 1998-01-23
    • Jeffrey E. Smith
    • Jeffrey E. Smith
    • G05F3/24H03K19/003H03M1/12
    • G05F3/247G05F3/245H03K19/00384
    • An analog compensation circuit for providing process/voltage/temperature (PVT) bias compensation signals for input/output (I/O) circuitry within an integrated circuit includes a first current source coupled to a first node. A first load coupled to the first current source and a second node provides a first reference voltage. A voltage divider coupled between the first and second nodes provides a current source bias voltage to the first current source. A differential amplifier generates a first bias compensation signal as feedback for the first current source in accordance with the difference between the first reference voltage and a second reference voltage. With the addition of logic level bias converters, the compensation circuitry is capable of providing bias compensation signals to multiple logic families. The bias compensation signals can be applied to current sources used to control the functioning of integrated circuit I/O circuitry so that the I/O circuitry operates substantially independently of PVT variations.
    • 用于为集成电路内的输入/输出(I / O)电路提供过程/电压/温度(PVT)偏置补偿信号的模拟补偿电路包括耦合到第一节点的第一电流源。 耦合到第一电流源和第二节点的第一负载提供第一参考电压。 耦合在第一和第二节点之间的分压器为第一电流源提供电流源偏置电压。 差分放大器根据第一参考电压和第二参考电压之间的差产生作为第一电流源的反馈的第一偏置补偿信号。 通过增加逻辑电平偏置转换器,补偿电路能够向多个逻辑系列提供偏置补偿信号。 偏置补偿信号可以应用于用于控制集成电路I / O电路的功能的电流源,使得I / O电路基本上独立于PVT变化操作。
    • 7. 发明授权
    • Downspout drain connection and filter
    • 下水道排水连接和过滤器
    • US08715495B1
    • 2014-05-06
    • US13909334
    • 2013-06-04
    • Jeffrey E. Smith
    • Jeffrey E. Smith
    • E04D13/076E04D13/08B01D35/02B01D29/44
    • E04D13/0645B01D35/02E04D13/0641E04D13/068E04D13/076E04D13/0767E04D13/08E04D2013/0806E04D2013/086F16L25/14
    • Included in this disclosure is a downspout drain filter for rain gutter downspouts. The downspout drain filer comprises elongated housing having an axis, a top portion, and a bottom portion. A transition portion connects the top portion to the bottom portion. The top portion includes an intake opening, a top portion perimeter, a debris opening, a filter attachment location, and a downspout attachment location. The downspout attachment location includes a flexible collar that defines a downspout attachment location perimeter that is less than the top portion perimeter. The bottom portion includes a flexible collapsible body that extends from the transition portion. A connection end is positioned opposite the transition portion as a part of the bottom portion. A filter is positioned in the top portion to direct debris out the debris opening and to permit liquid to pass to the bottom portion.
    • 本公开中包括用于雨沟下水道的降压排水过滤器。 下水口漏斗管包括具有轴线,顶部和底部的细长壳体。 过渡部分将顶部连接到底部。 顶部包括进气口,顶部周边,碎屑开口,过滤器附接位置和下水口附接位置。 下水口附接位置包括柔性环,其限定小于顶部部分周界的下水口附着位置周边。 底部包括从过渡部分延伸的柔性可折叠主体。 连接端与过渡部分相对地定位为底部的一部分。 过滤器定位在顶部部分中以将碎屑引导出碎屑开口并允许液体通过到底部。
    • 9. 发明授权
    • Thrust bearing and use of same with apparatus for reducing repetitive
stress injury
    • 推力轴承及其与减少重复应力损伤的装置的使用
    • US5863132A
    • 1999-01-26
    • US879174
    • 1997-06-20
    • Jeffrey E. SmithRobert J. Crosson
    • Jeffrey E. SmithRobert J. Crosson
    • A47B21/03F16C19/10F16C29/00F16M11/10F16M11/24F16C29/04
    • F16C19/50A47B21/0314F16C19/10F16C29/046F16C33/38F16M11/10F16M11/18F16M11/24A47B2021/0321
    • A thrust bearing for bearing a load along a force vector includes at least two roller elements in rolling contact with one another and arranged along the force vector such that the load is borne through the roller elements. The roller elements are retained within a retainer such that they remain aligned along the force vector while subjected to loads. The retainer used to house the roller elements may be designed to abut the roller elements at minimum points of contact, or alternatively to distribute the load borne by one or both of the roller elements across a greater surface area. One application of the preferred thrust bearings is in an apparatus such as a keyboard support for reducing repetitive stress injuries. A main disk is rotatably coupled to a base and supports a support member on a plurality of the thrust bearings. Rotation of the main disk varies the tilt of the support member relative to the base, thereby adjusting the position of a keyboard supported on the support member relative to an operator.
    • 用于沿着力向量承载载荷的止推轴承包括彼此滚动接触并沿力向量布置的至少两个滚子元件,使得载荷通过滚子元件承载。 滚子元件保持在保持器内,使得它们在受到载荷时沿力向量保持对准。 用于容纳辊元件的保持器可以设计成在最小接触点处邻接滚子元件,或者替代地将滚子元件中的一个或两个承载的载荷分布在更大的表面积上。 优选推力轴承的一个应用在诸如用于减少重复应力损伤的键盘支架的装置中。 主盘可旋转地联接到基座并且在多个推力轴承上支撑支撑构件。 主盘的旋转改变支撑构件相对于底座的倾斜度,从而相对于操作者调节支撑在支撑构件上的键盘的位置。
    • 10. 发明授权
    • Method and apparatus supplying synchronous clock signals to circuit
components
    • 向电路部件提供同步时钟信号的方法和装置
    • US5586307A
    • 1996-12-17
    • US86044
    • 1993-06-30
    • Keng L. WongKelly J. FitzpatrickJeffrey E. Smith
    • Keng L. WongKelly J. FitzpatrickJeffrey E. Smith
    • G06F1/10G06F1/32H01L21/82H01L21/822H01L27/04H03K5/15G06F1/12
    • G06F1/3237G06F1/10G06F1/3203G06F1/3287Y02B60/1221Y02B60/1282
    • A clock distribution system and clock interrupt system for an integrated circuit device. Ignoring effects associated with the matched stages, the present invention includes a clock distribution and interrupt system for providing clock signals with less than 100 picoseconds of skew to various components of an integrated circuit device. The present invention utilizes several stages of drivers to evenly supply the distributed clock signals and each stage has RC matched input lines. The present invention advantageously locates the matched stages and clock drivers within the power supply ring of the integrated circuit located on the periphery of the microprocessor topology. This is done in order to better predict the topology surrounding these lines to match the capacitance of these lines. Further, this metal level offers a larger width dimension line (since as a top layer it may be thicker) having less resistance per unit area and also generally avoids spatial competition with other IC components and circuitry. The present invention additionally offers the capability of selectively powering down various components within the integrated device with a power management unit and enable network that is included as a component of the clock distribution system.
    • 用于集成电路设备的时钟分配系统和时钟中断系统。 忽略与匹配级相关的效应,本发明包括时钟分配和中断系统,用于向集成电路器件的各种部件提供小于100皮秒的偏移的时钟信号。 本发明利用几级驱动器均匀地提供分布式时钟信号,每级具有RC匹配输入线。 本发明有利地位于位于微处理器拓扑周边的集成电路的电源环内的匹配级和时钟驱动器。 这样做是为了更好地预测这些线路周围的拓扑,以匹配这些线路的电容。 此外,该金属层提供更大的宽度尺寸线(因为顶层可以更厚),每单位面积的电阻较小,并且还通常避免与其它IC组件和电路的空间竞争。 本发明另外提供了利用功率管理单元选择性地降低集成设备内的各种组件并使能作为时钟分配系统的组件被包括的网络的能力。