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1. 发明授权

US06178206B1 Method and apparatus for source synchronous data transfer 失效
标题翻译：源同步数据传输的方法和装置
公开(公告)号：US06178206B1
公开(公告)日：2001-01-23
申请号：US09013479
申请日：1998-01-26
申请人： Timothy W. Kelly , Stephen S. Pawlowski , Keith M. Self , Jeffrey E. Smith
发明人： Timothy W. Kelly , Stephen S. Pawlowski , Keith M. Self , Jeffrey E. Smith
IPC分类号： H04L2500
CPC分类号： H04L7/0331 , H04L7/0008
摘要： A method and apparatus is presented where for transmitting data between two or more components. Data signals are sent in parallel with a clocking signal (e.g., on a bus) so that the data signal can be latched in relation to the clocking signal. For example, two clocking signals, out of phase from each other by 180 degrees, can be sent on bidirectional clocking signal lines and data signals can be sent on a data signal line, the component receiving the clocking and data signals can latch the data signals on each high-to-low transition of either of the two clocking signals. Using the method and apparatus of the present invention, skew problems seen with other bus systems can be reduced which leads to an increase in data transfer rates.
摘要翻译：提出了一种用于在两个或更多个组件之间传输数据的方法和装置。数据信号与时钟信号（例如，总线）并行地发送，使得可以相对于时钟信号锁存数据信号。例如，可以在双向时钟信号线上发送彼此异相180度的两个时钟信号，并且数据信号可以在数据信号线上发送，接收时钟和数据信号的组件可以锁存数据信号在两个时钟信号中的任一个的每个从高到低的转换。使用本发明的方法和装置，可以减少其他总线系统所看到的偏斜问题，这导致数据传输速率的增加。

2. 发明授权

US6151257A Apparatus for receiving/transmitting signals in an input/output pad buffer cell 失效
标题翻译：用于在输入/输出缓冲单元中接收/发送信号的装置
公开(公告)号：US6151257A
公开(公告)日：2000-11-21
申请号：US13482
申请日：1998-01-26
申请人： Smith E. Jeffrey , Timothy W. Kelly , Stephen W. Kiss , Keith M. Self
发明人： Smith E. Jeffrey , Timothy W. Kelly , Stephen W. Kiss , Keith M. Self
IPC分类号： G11C7/10 , H03K19/003 , G11C7/00
CPC分类号： G11C7/1093 , G11C7/1051 , G11C7/1078 , G11C7/1087 , H03K19/00323
摘要： An electronic circuit die is presented including a plurality of first and second input/output (I/O) pad buffer cells. The first I/O pad buffer cells include at least a latch for latching data signals received at a pad in the cell. Adjacent ones of these first I/O pad buffer cells are conductively coupled together using conductive trace pins. The second I/O pad buffer cells include a pad that receives clocking signal which are supplied to the latches of the first I/O pad buffer cells. Accordingly, data signals received at the pads of the die are latched in the pad as opposed to the core logic of the die. One benefit of providing the latching of data signals in the pad is that conductive traces between the latches and the core logic need not be precisely matched, thus reducing cost. Also, the first I/O pad buffer cells can be similarly constructed, thus reducing the complexity and cost of manufacture for the die.
摘要翻译：呈现包括多个第一和第二输入/输出（I / O）缓冲区单元的电子电路管芯。第一I / O缓冲单元至少包括用于锁存在单元中的垫处接收的数据信号的锁存器。这些第一I / O焊盘缓冲单元中的相邻的一个使用导电迹线引脚导电耦合在一起。第二I / O焊盘缓冲单元包括接收提供给第一I / O缓冲单元的锁存器的时钟信号的焊盘。因此，与芯片的核心逻辑相反，在芯片的焊盘处接收的数据信号被锁存在焊盘中。在焊盘中提供数据信号锁存的一个好处是锁存器和核心逻辑之间的导电迹线不需要精确匹配，从而降低了成本。此外，可以类似地构造第一I / O缓冲电池，从而降低了芯片制造的复杂性和成本。

3. 发明授权

US6009532A Multiple internal phase-locked loops for synchronization of chipset components and subsystems 失效
标题翻译：多个内部锁相环，用于芯片组件和子系统的同步
公开(公告)号：US6009532A
公开(公告)日：1999-12-28
申请号：US12202
申请日：1998-01-23
申请人： Keith M. Self , Jeffrey E. Smith
发明人： Keith M. Self , Jeffrey E. Smith
IPC分类号： G06F1/10 , G06F1/12 , G06F19/00
CPC分类号： G06F1/10
摘要： An apparatus and a method for easing design constraints with respect to placement of computer system components and subsystems requiring relative synchronicity are described. In one embodiment, the apparatus includes a first phase-locked loop (PLL) coupled to a reference clock pin by a path of length L1 and a first PLL feedback pin by a path of length L2 such that L1.apprxeq.L2. In another embodiment, the apparatus includes a second PLL coupled to the reference clock pin by a path of length L3. The second PLL is coupled to an internal core of the integrated circuit by a path of length L4 such that L3.apprxeq.L4. In one embodiment, a computer system incorporating the apparatus includes a first propagation path of length L5 coupled to the first PLL output pin. The first PLL output pin is coupled to the first PLL feedback pin by a path of length L6 such that L5.apprxeq.L6. The choice of electrical lengths allows relative synchronicity between the clock signals propagated to the internal core and the end of the first propagation path.
摘要翻译：描述了相对于需要相对同步性的计算机系统部件和子系统的放置来减轻设计约束的装置和方法。在一个实施例中，该装置包括通过长度为L1的路径耦合到参考时钟引脚的第一锁相环（PLL）和通过长度为L2的路径的第一PLL反馈引脚，使得L1 APPROX L2。在另一实施例中，该装置包括通过长度为L3的路径耦合到参考时钟引脚的第二PLL。第二PLL通过长度为L4的路径耦合到集成电路的内部核心，使得L3 APPROX L4。在一个实施例中，结合该装置的计算机系统包括长度为L5的耦合到第一PLL输出引脚的第一传播路径。第一个PLL输出引脚通过长度为L6的路径耦合到第一个PLL反馈引脚，使得L5 APPROX L6。电长度的选择允许传播到内部核心的时钟信号和第一个传播路径的末端之间的相对同步性。

4. 发明授权

US6112308A Cascaded multiple internal phase-locked loops for synchronization of hierarchically distinct chipset components and subsystems 失效
标题翻译：层叠多个内部锁相环，用于层次分明的不同芯片组件和子系统的同步
公开(公告)号：US6112308A
公开(公告)日：2000-08-29
申请号：US126937
申请日：1998-07-30
申请人： Keith M. Self , Jeffrey E. Smith
发明人： Keith M. Self , Jeffrey E. Smith
IPC分类号： G06F1/12
CPC分类号： G06F1/12
摘要： Methods and apparatus for easing design constraints with respect to placement of computer system components and subsystems requiring relative synchronicity is described. In one embodiment the apparatus includes a first and a second integrated circuit wherein each integrated circuit includes a first phase-locked loop (PLL) formed on an integrated circuit die. A reference clock signal pin is coupled to the first PLL by a path of electrical length L1 for propagating a reference clock signal to the first PLL. A first PLL driver is coupled to the first PLL. A first PLL feedback pin is coupled to the first PLL by a path of electrical length L2, wherein L1.apprxeq.L2. The first and second integrated circuits are cascade-coupled by coupling the first PLL driver of the first integrated circuit to the reference clock signal pin of the second integrated circuit using a propagation path of electrical length L3. In one embodiment a feedback path of electrical length L4 couples the first PLL driver and feedback pin of the first integrated circuit such that L3.apprxeq.L4. In one embodiment L1, L2, L3, and L4 have corresponding physical lengths D1, D2, D3, and D4, wherein D1.apprxeq.D2 and D3.apprxeq.D4. The cascaded integrated circuits enable providing synchronicity between components of a same tier as well as between multiple tiers of a hierarchical computer system architecture.
摘要翻译：描述了相对于需要相对同步的计算机系统部件和子系统的放置来减轻设计约束的方法和装置。在一个实施例中，该装置包括第一和第二集成电路，其中每个集成电路包括形成在集成电路管芯上的第一锁相环（PLL）。参考时钟信号引脚通过电长度L1的路径耦合到第一PLL，以将参考时钟信号传播到第一PLL。第一PLL驱动器耦合到第一PLL。第一PLL反馈引脚通过电长度L2的路径耦合到第一PLL，其中L1 APPROX L2。第一和第二集成电路通过使用电长度L3的传播路径将第一集成电路的第一PLL驱动器耦合到第二集成电路的参考时钟信号引脚来级联耦合。在一个实施例中，电长度为L4的反馈路径耦合第一集成电路的第一PLL驱动器和反馈引脚，使得L3 APPROX L4。在一个实施例中，L1，L2，L3和L4具有对应的物理长度D1，D2，D3和D4，其中D1 APPROX D2和D3 APPROX D4。级联的集成电路能够提供同一层的组件之间以及分级计算机系统架构的多层之间的同步性。

5. 发明授权

US6047383A Multiple internal phase-locked loops for synchronization of chipset components and subsystems operating at different frequencies 失效
标题翻译：用于同步芯片组件和不同频率工作的子系统的多个内部锁相环
公开(公告)号：US6047383A
公开(公告)日：2000-04-04
申请号：US12479
申请日：1998-01-23
申请人： Keith M. Self , Jeffrey E. Smith , Keng L. Wong
发明人： Keith M. Self , Jeffrey E. Smith , Keng L. Wong
IPC分类号： G06F1/12
CPC分类号： G06F1/12
摘要： Methods and apparatus for easing design constraints with respect to placement of computer system components and subsystems requiring relative synchronicity at different frequencies is described. In one embodiment the apparatus includes a first phase-locked loop (PLL) formed on an integrated circuit die. A reference clock signal pin is coupled to the first PLL by a path of electrical length L1 for propagating a reference clock signal to the first PLL. A first PLL feedback pin is coupled to the first PLL by a path of electrical length L2, wherein L1.apprxeq.L2. The apparatus includes a programmable counter coupled to the reference clock signal pin, the programmable counter providing a divided reference clock signal to the first PLL. In one embodiment, the method includes the step of providing a reference clock signal to a plurality of PLLs residing within a same integrated circuit. The outputs of at least some of the PLLs are coupled to corresponding output pins of the integrated circuit. The following steps are performed for each selected output pin coupled to provide a synchronized clock signal at the end of a propagation trace: a) determining an electrical length of the propagation trace; and b) providing a feedback trace from the output pin to a feedback pin of the corresponding PLL, wherein the feedback trace is a same electrical length as the propagation trace. A divided-by-n reference clock signal is then provided to at least one of the PLLs, wherein n is not equal to 1.
摘要翻译：描述了关于在不同频率下需要相对同步性的计算机系统组件和子系统的放置的宽松设计约束的方法和装置。在一个实施例中，该装置包括形成在集成电路管芯上的第一锁相环（PLL）。参考时钟信号引脚通过电长度L1的路径耦合到第一PLL，以将参考时钟信号传播到第一PLL。第一PLL反馈引脚通过电长度L2的路径耦合到第一PLL，其中L1 APPROX L2。该装置包括耦合到参考时钟信号引脚的可编程计数器，该可编程计数器向第一PLL提供划分的基准时钟信号。在一个实施例中，该方法包括向驻留在同一集成电路中的多个PLL提供参考时钟信号的步骤。至少一些PLL的输出耦合到集成电路的相应输出引脚。对于耦合以在传播轨迹结束时提供同步时钟信号的每个选择的输出引脚执行以下步骤：a）确定传播轨迹的电长度; 以及b）提供从所述输出引脚到相应PLL的反馈引脚的反馈迹线，其中所述反馈迹线与所述传播迹线具有相同的电长度。然后，将一个分频参考时钟信号提供给至少一个PLL，其中n不等于1。

6. 发明授权

US07224739B2 Controlled frequency signals 有权
标题翻译：受控频率信号
公开(公告)号：US07224739B2
公开(公告)日：2007-05-29
申请号：US10226074
申请日：2002-08-21
申请人： Jed D. Griffin , Jerry G. Jex , Brett A. Prince , Keith M. Self
发明人： Jed D. Griffin , Jerry G. Jex , Brett A. Prince , Keith M. Self
IPC分类号： H04L27/00 , H04L7/00 , H04L5/14 , H04B1/00
CPC分类号： H04L25/08 , H04L25/085 , H04L25/4908
摘要： In some embodiments, a transmitter includes first encoding controlled frequency output circuitry to creates a magnitude encoded controlled frequency signal (CFS) and second encoding controlled frequency output circuitry to create a complementary a magnitude encoded controlled frequency signal (CCFS). Other embodiments are described and claimed.
摘要翻译：在一些实施例中，发射机包括第一编码受控频率输出电路，以创建幅度编码的受控频率信号（CFS）和第二编码受控频率输出电路以产生互补的幅度编码的受控频率信号（CCFS）。描述和要求保护其他实施例。

7. 发明授权

US06718416B1 Method and apparatus for removing and installing a computer system bus agent without powering down the computer system 有权
标题翻译：用于移除和安装计算机系统总线代理而不关闭计算机系统的方法和装置
公开(公告)号：US06718416B1
公开(公告)日：2004-04-06
申请号：US09643379
申请日：2000-08-21
申请人： Keith M. Self , Matthew B. Haycock
发明人： Keith M. Self , Matthew B. Haycock
IPC分类号： G06F1300
CPC分类号： G06F13/4081
摘要： An example embodiment of a computer system that includes a removable agent that can be removed or installed without powering down the system includes a fixed bus agent and the replaceable bus agent. The fixed bus agent and the replaceable bus agent are electrically coupled together by a presence detect signal, a synchronization signal, and a data bus. A deassertion of the presence detect signal indicates to the fixed bus agent that the removable bus agent has been disconnected and is no longer electrically coupled to the fixed bus agent. The fixed bus agent then tri-states its outputs and also prevents potentially invalid data from being delivered to the core circuitry of the fixed bus agent. An assertion of the presence detect signal indicates to the fixed bus agent that the replaceable bus agent is electrically connected to the fixed bus agent. In response to the assertion of the presence detect signal, the fixed bus agent and the replaceable bus agent enter reset periods. Following the reset periods and when each bus agent is ready to communicate to the other agent, the fixed bus agent and the replaceable bus agent signal to each other over the synchronization signal that each is ready to begin communication over the data bus.
摘要翻译：包括可以在不关闭系统的情况下被移除或安装的可移除代理的计算机系统的示例性实施例包括固定总线代理和可更换总线代理。固定总线代理和可更换总线代理通过存在检测信号，同步信号和数据总线电耦合在一起。存在检测信号的取消表示向固定总线代理指示可移除总线代理已经断开并且不再电耦合到固定总线代理。然后，固定总线代理器对其输出进行三态，并且还防止潜在的无效数据被传递到固定总线代理的核心电路。存在检测信号的断言向固定总线代理指示可更换总线代理电连接到固定总线代理。响应于存在检测信号的确认，固定总线代理和可更换总线代理进入复位周期。在复位周期之后，当每个总线代理准备好与其他代理通信时，固定总线代理和可更换总线代理器通过同步信号相互信号，每个同步信号准备好通过数据总线开始通信。

8. 发明授权

US07158594B2 Receivers for controlled frequency signals 失效
标题翻译：受控频率信号接收机
公开(公告)号：US07158594B2
公开(公告)日：2007-01-02
申请号：US10225691
申请日：2002-08-21
申请人： Jed D. Griffin , Jerry G. Jex , Brett A. Prince , Keith M. Self
发明人： Jed D. Griffin , Jerry G. Jex , Brett A. Prince , Keith M. Self
IPC分类号： H04L7/00 , H04L25/49 , H03K5/22
CPC分类号： H04L25/085 , H04L25/08 , H04L25/4908
摘要： In some embodiments, a receiver includes a first conductor to carry a magnitude encoded controlled frequency signal (CFS) and a second conductor to carry a complementary magnitude encoded controlled frequency signal (CCFS). The receiver further includes circuitry to receive the CFS and CCFS from the first and second conductors and to decode them to produce an output signal. Other embodiments are described and claimed.
摘要翻译：在一些实施例中，接收机包括承载幅度编码的受控频率信号（CFS）的第一导体和用于承载互补幅度编码的受控频率信号（CCFS）的第二导体。接收器还包括从第一和第二导体接收CFS和CCFS并且对它们进行解码以产生输出信号的电路。描述和要求保护其他实施例。

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