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1. 发明授权

US6151681A Dynamic device power management 失效
标题翻译：动态设备电源管理
公开(公告)号：US6151681A
公开(公告)日：2000-11-21
申请号：US102245
申请日：1998-06-22
申请人： Philip A. Roden , Patrick C. Neil , David W. Rekieta
发明人： Philip A. Roden , Patrick C. Neil , David W. Rekieta
IPC分类号： G06F1/32 , G06F1/12
CPC分类号： G06F1/3237 , G06F1/3203 , G06F1/3287 , Y02B60/1221 , Y02B60/1282
摘要： A power management method and system which includes providing a system having a plurality of clock operated circuits, each clock operated circuit being operable in response to the receipt of clock signals. A first subplurality of the clock operated circuits receives an uninterrupted stream of clock signals and thereby is uninterruptably operable and a second plurality of the clock operated circuits receives a normally off interruptable stream of clock signals and is normally inoperable. The system is sampled for the presence of data signals being input thereto. The clock signals are sent to the second plurality of circuits in response to the sampling the presence of data signals being input to the system to cause the second plurality of circuits to be operable. The data signals are transmitted to the second plurality of circuits after a time delay equal to or greater than the expired time from the sampling to the sending. The system can have a plurality of input/output terminals with the sampling comprising being at each of the input/output terminals. The system includes a clock for providing the clock signals and a decode logic for sampling at one of the input/output terminals and an arbiter circuit for sampling at the other input/output terminal.
摘要翻译：一种电源管理方法和系统，其包括提供具有多个时钟操作电路的系统，每个时钟操作电路可响应于时钟信号的接收来操作。时钟操作电路的第一子部分接收不间断的时钟信号流，从而不间断地操作，并且第二多个时钟操作电路接收正常关断的可中断时钟信号流，并且通常是不可操作的。对输入的数据信号的存在进行采样。所述时钟信号响应于对所述系统输入的数据信号的存在进行采样而被发送到所述第二多个电路，以使所述第二多个电路可操作。在等于或大于从采样到发送的到期时间的时间延迟之后，数据信号被发送到第二多个电路。该系统可以具有多个输入/输出端子，其中采样包括在每个输入/输出端子处。该系统包括用于提供时钟信号的时钟和用于在输入/输出端子之一处采样的解码逻辑和用于在另一个输入/输出端子处进行采样的仲裁器电路。

2. 发明授权

US6088808A Low power consumption semiconductor integrated circuit device and microprocessor 失效
公开(公告)号：US6088808A
公开(公告)日：2000-07-11
申请号：US966972
申请日：1997-11-10
申请人： Masahiro Iwamura , Shigeya Tanaka , Hideo Maejima , Tetsuo Nakano
发明人： Masahiro Iwamura , Shigeya Tanaka , Hideo Maejima , Tetsuo Nakano
IPC分类号： G06F1/32 , B60Q1/44 , G06F1/26 , G06F9/34 , G06F9/38 , G06F15/78 , G11C11/417 , G11C11/419
CPC分类号： G06F1/3203 , G06F1/26 , G06F1/3287 , G06F15/7832 , G06F9/3822 , G06F9/3824 , G06F9/3836 , G06F9/3859 , G06F9/3869 , G06F9/3885 , G11C11/417 , G11C11/419 , Y02B60/1282 , Y02B60/32
摘要： In semiconductor integrated circuit device and microprocessor including at least one functional circuit block, the start of operation of the functional circuit block is detected prior to the start of operation, the functional circuit block for which the start of operation has been detected is activated prior to the start of operation and inactivated after the termination of operation.

3. 发明授权

US5996083A Microprocessor having software controllable power consumption 失效
标题翻译：具有软件可控功耗的微处理器
公开(公告)号：US5996083A
公开(公告)日：1999-11-30
申请号：US514284
申请日：1995-08-11
申请人： Rajiv Gupta , Prasad Raje
发明人： Rajiv Gupta , Prasad Raje
IPC分类号： G06F1/04 , G06F1/08 , G06F1/32 , G06F9/38 , G06F15/78 , G06F1/00
CPC分类号： G06F9/3885 , G06F1/3203 , G06F1/324 , G06F1/3275 , G06F1/3287 , G06F1/3296 , G06F9/30083 , G06F9/3836 , G06F9/3869 , Y02B60/1217 , Y02B60/1228 , Y02B60/1282 , Y02B60/1285
摘要： A microprocessor is provided which includes a power control register for controlling the rate of execution and therefore the power consumption of individual functional units. The power control register includes a plurality of fields corresponding to the functional units for storing values that control the power consumption of each. The power control register fields can be set by software which has the much greater ability to look out into the future to determine whether the functional units will be required. The functional units are responsive to the corresponding power control register field to adjust their rate of execution responsive to the value stored therein. The rate of execution can be controlled in a number of different ways: dividing down the clock; removing power to the functional unit; disabling the sensor and/or buffer driver of one or more of the ports in a multi-ported RAM; removing data from the functional unit; and changing the data bus width responsive to the control register field. The microprocessor also includes a latency control register which assures that the functional unit is operational after the functional unit is placed from a low power state to a more fully operational state by changing the corresponding field in the power control register.
摘要翻译：提供了一种微处理器，其包括用于控制执行速率并因此控制各个功能单元的功率消耗的功率控制寄存器。功率控制寄存器包括对应于功能单元的多个场，用于存储控制每个功率消耗的值。功率控制寄存器字段可以通过软件来设置，该软件具有更大的能力，以期望将来确定是否需要功能单元。功能单元响应于相应的功率控制寄存器字段来响应于存储在其中的值来调整其执行速率。执行速度可以通过多种不同的方式进行控制：按时间排序; 去除功能单元的电力; 禁用多端口RAM中的一个或多个端口的传感器和/或缓冲器驱动器; 从功能单元移除数据; 并且响应于控制寄存器字段来改变数据总线宽度。微处理器还包括等待时间控制寄存器，其通过改变功率控制寄存器中的相应字段来确保功能单元在功能单元从低功率状态放置到更完全操作状态之后是可操作的。

4. 发明授权

US5903254A User interface for easily setting computer speaker volume and power conservation levels 失效
标题翻译：用户界面，便于设置电脑扬声器的音量和节能水平
公开(公告)号：US5903254A
公开(公告)日：1999-05-11
申请号：US874418
申请日：1997-06-13
申请人： Kevin Warren Mundt , Randall L. Hess , David B. Potter
发明人： Kevin Warren Mundt , Randall L. Hess , David B. Potter
IPC分类号： G06F1/32 , G06F3/033 , G06F3/048 , G06F3/16 , G09G5/08
CPC分类号： G06F1/3287 , G06F1/3203 , G06F1/3246 , G06F3/0481 , G06F3/165 , G06F3/167 , Y02B60/1282
摘要： A user interface of simplifying selection of speaker volume level and power conservation level in a computer system. An icon is presented for setting the speaker volume which includes a bar graph of relative speaker volume. By depressing left or right arrow keys the graph moves and the volume level of the speaker is changed. By depressing the down arrow key when setting the volume level, the speaker is beeped to allow for a level check during the setting process. A series of icons are used to indicate and select power conservation level. Each icon includes a battery with a faucet attached to the side of the battery. Different water flow rates indicate the various conservation levels. A human figure is located adjacent the faucet to indicate the user-customerized conservation level.
摘要翻译：用户界面，简化了计算机系统中扬声器音量和功率节省等级的选择。提供一个用于设置扬声器音量的图标，其中包括相对扬声器音量的条形图。通过按下左或右箭头键，图形移动，并且扬声器的音量水平发生变化。通过在设置音量时按住向下箭头键，扬声器将被唤醒，以便在设置过程中进行电平检查。一系列图标用于指示和选择节能水平。每个图标包括一个连接在电池一侧的水龙头的电池。不同的水流量表示各种保护水平。一个人物位于水龙头附近，以指示用户客户化的保护水平。

5. 发明授权

US5802269A Method and apparatus for power management of distributed direct memory access (DDMA) devices 失效
标题翻译：分布式直接存储器访问（DDMA）设备的电源管理方法和装置
公开(公告)号：US5802269A
公开(公告)日：1998-09-01
申请号：US672869
申请日：1996-06-28
申请人： David Poisner , Rajesh Raman
发明人： David Poisner , Rajesh Raman
IPC分类号： G01R31/30 , G06F11/14 , G06F11/00
CPC分类号： G01R31/3004 , G06F1/3287 , Y02B60/1282 , Y02B60/32
摘要： A method and apparatus for controlling accesses to DMA control registers, specifically operating according to a Distributed Direct Memory Access (DDMA) protocol. When an access to a peripheral device ends in a Master Abort due to the failure of the peripheral device to respond to the DDMA Master component during a DDMA transaction, a System Management Interrupt (SMI#) is generated to the central processing unit. In the resulting execution of the System Management Mode code by the CPU, the cause of the peripheral component not responding (e.g., that the peripheral is in a low power mode, the connection between the DDMA master and the peripheral is interrupted, etc.) is determined. The CPU, executing SMM code, takes steps to correct the problem. For example, if the peripheral is powered down, the CPU will power it up so that the DDMA transaction can subsequently occur. Alternatively, when BIOS is used to power down a peripheral device, the DDMA Master component can determine the peripheral's power status prior to trying the DMA access. If the peripheral device is powered down, the DDMA Master component issues an SMI# to the CPU to cause the peripheral to be powered up prior to the DDMA transaction.
摘要翻译：一种用于控制对DMA控制寄存器的访问的方法和装置，具体根据分布式直接存储器访问（DDMA）协议进行操作。当由于外围设备在DDMA事务期间响应DDMA主组件而发生故障时，对外设进行访问终止，因此会向中央处理单元生成系统管理中断（SMI＃）。在CPU执行系统管理模式代码时，外设组件的响应原因（例如，外设处于低功耗模式，DDMA主机与外设之间的连接中断等）决心，决意，决定。执行SMM代码的CPU需要采取措施来纠正问题。例如，如果外围设备关闭电源，CPU将为其供电，以便随后可能会发生DDMA事务。或者，当使用BIOS来关闭外围设备时，DDMA主组件可以在尝试DMA访问之前确定外设的电源状态。如果外围设备关闭电源，DDMA主控组件向CPU发出SMI＃以使外部设备在DDMA事务之前通电。

6. 发明授权

US5692204A Method and apparatus for computer system power management 失效
标题翻译：计算机系统电源管理方法和装置
公开(公告)号：US5692204A
公开(公告)日：1997-11-25
申请号：US666149
申请日：1996-06-19
申请人： Andrew Radcliffe Rawson , Guy Gil Sotomayor, Jr.
发明人： Andrew Radcliffe Rawson , Guy Gil Sotomayor, Jr.
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/3287 , G06F1/3203 , Y02B60/1282 , Y02B60/32
摘要： A method and apparatus for managing power states of at least one hardware resource, including registering at least one hardware resource power state corresponding to a software process, determining whether a current hardware resource power state fulfills the registered hardware resource power state corresponding to the software process, and modifying the current hardware resource power state that is determined not to fulfill the registered hardware resource power state prior to executing the software process.
摘要翻译：一种用于管理至少一个硬件资源的电力状态的方法和装置，包括登记与软件过程相对应的至少一个硬件资源功率状态，确定当前硬件资源功率状态是否满足对应于软件过程的注册硬件资源功率状态并且在执行软件处理之前修改确定为不满足注册的硬件资源功率状态的当前硬件资源功率状态。

7. 发明授权

US5666537A Power down scheme for idle processor components 失效
标题翻译：空闲处理器组件的掉电方案
公开(公告)号：US5666537A
公开(公告)日：1997-09-09
申请号：US289928
申请日：1994-08-12
申请人： Kathakali Debnath , Anurag Sah , Cong Quoc Khieu
发明人： Kathakali Debnath , Anurag Sah , Cong Quoc Khieu
IPC分类号： G06F1/32 , G06F9/38
CPC分类号： G06F9/3836 , G06F1/3203 , G06F1/3275 , G06F1/3287 , G06F9/30083 , G06F9/3857 , G06F9/3861 , G06F9/3885 , Y02B60/1225 , Y02B60/1228 , Y02B60/1282 , Y02B60/32
摘要： Power down circuitry in a processor for controlling power delivered to functional units of the processor, comprising first and second power down circuits. The first power down circuit comprises a state machine having a decoded instruction as input and a control signal as output. The control signal disables a clock signal to a floating point unit (FPU) when the decoded instruction is not a floating point instruction. The second power down circuit comprises a prediction circuit that generates a predict signal when a cache access cannot occur. The predict signal disables a clock signal to a cache.
摘要翻译：用于控制递送到处理器的功能单元的功率的处理器中的掉电电路，包括第一和第二掉电电路。第一断电电路包括具有作为输入的解码指令和作为输出的控制信号的状态机。当解码的指令不是浮点指令时，控制信号禁止对浮点单元（FPU）的时钟信号。第二断电电路包括在不能发生高速缓存访问时产生预测信号的预测电路。预测信号禁用时钟信号到缓存。

8. 发明授权

US5655124A Selective power-down for high performance CPU/system 失效
标题翻译：高性能CPU /系统的选择性掉电
公开(公告)号：US5655124A
公开(公告)日：1997-08-05
申请号：US487976
申请日：1995-06-07
申请人： Chong Ming Lin
发明人： Chong Ming Lin
IPC分类号： G06F1/04 , G06F1/26 , G06F1/32 , G06F9/30 , G06F9/38 , G06F9/45 , G06F15/78 , G06F1/00 , G06F1/18
CPC分类号： G06F1/3237 , G06F1/3203 , G06F1/3243 , G06F1/3287 , G06F9/3836 , G06F9/3855 , G06F9/3869 , Y02B60/1221 , Y02B60/1239 , Y02B60/1282 , Y02B60/32
摘要： A microelectronic device according to the present invention is made up of two or more functional units, which are all disposed on a single chip, or die. The present invention works on the strategy that all of the functional units on the die are not, and do not need to be operational at a given time in the execution of a computer program that is controlling the microelectronic device. The present invention on a very rapid basis (typically a half clock cycle), therefore, turns on and off the functional units of the microelectronic device in accordance with the requirements of the program being executed. This power down can be achieved by one of three techniques; turning off clock inputs to the functional units, interrupting the supply of power to the functional units, or deactivating input signals to the functional units. The operation of the present invention results in a very significant reduction in power consumption and corresponding heat dissipation by the microelectronic device as compared to the conventional approach of keeping all functional units operational all of the time.
摘要翻译：根据本发明的微电子器件由两个或更多个功能单元组成，它们均设置在单个芯片或管芯上。本发明致力于在执行正在控制微电子器件的计算机程序的给定时间内，芯片上的所有功能单元不是并且不需要操作的策略。因此，基于正在执行的程序的要求，非常快速地（通常是半个时钟周期）本发明导通和关闭微电子器件的功能单元。这种掉电可以通过三种技术之一实现; 关闭功能单元的时钟输入，中断向功能单元供电，或者禁用对功能单元的输入信号。与所有功能单元始终运行的常规方法相比，本发明的操作导致了微功耗器件的功耗和相应散热的非常显着的降低。

9. 发明授权

US5546591A Distributed power management system for battery operated personal computers 失效
标题翻译：用于电池供电的个人电脑的分布式电源管理系统
公开(公告)号：US5546591A
公开(公告)日：1996-08-13
申请号：US190697
申请日：1994-02-01
申请人： Henry Wurzburg , Walter H. Potts
发明人： Henry Wurzburg , Walter H. Potts
IPC分类号： G06F1/32 , G06F13/10 , G06F9/00
CPC分类号： G06F1/3215 , G06F1/3281 , G06F1/3287 , Y02B60/1264 , Y02B60/1282
摘要： A system for providing power to peripheral components associated with a personal computer is disclosed. A local power management unit is located at each controller for a peripheral component in order to provide a distributive power management arrangement. The local power management units communicate with an activity monitor provided in a central power management unit. The foregoing arrangement permits power to be maintained to the bus interface microchips at all times. Deactuation of a controller associated with a peripheral component is accomplished through inhibiting the clock signal produced by the local power management unit associated with the controller. By maintaining power to the bus interface microchips, power leakage through the bus interface microchips is eliminated.
摘要翻译：公开了一种用于向与个人计算机相关联的外围组件提供电力的系统。本地电源管理单元位于用于外围组件的每个控制器上，以便提供分布式电源管理装置。本地电源管理单元与中央电源管理单元中提供的活动监视器进行通信。上述布置允许在总线上将功率保持到总线接口微芯片。通过禁止与控制器相关联的本地电力管理单元产生的时钟信号来实现与外围组件相关联的控制器的去激活。通过维持总线接口微芯片的电源，消除了通过总线接口微芯片的电力泄漏。

10. 发明授权

US5457790A Low power consumption semiconductor integrated circuit device and microprocessor 失效
公开(公告)号：US5457790A
公开(公告)日：1995-10-10
申请号：US136990
申请日：1993-10-18
申请人： Masahiro Iwamura , Shigeya Tanaka , Hideo Maejima , Tetsuo Nakano
发明人： Masahiro Iwamura , Shigeya Tanaka , Hideo Maejima , Tetsuo Nakano
IPC分类号： G06F1/32 , B60Q1/44 , G06F1/26 , G06F9/34 , G06F9/38 , G06F15/78 , G11C11/417 , G11C11/419
CPC分类号： G06F1/3203 , G06F1/26 , G06F1/3287 , G06F15/7832 , G06F9/3822 , G06F9/3824 , G06F9/3836 , G06F9/3859 , G06F9/3869 , G06F9/3885 , G11C11/417 , G11C11/419 , Y02B60/1282 , Y02B60/32
摘要： In semiconductor integrated circuit device and microprocessor including at least one functional circuit block, the start of operation of the functional circuit block is detected prior to the start of operation, the functional circuit block for which the start of operation has been detected is activated prior to the start of operation and inactivated after the termination of operation.

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