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1. 发明授权

US5586307A Method and apparatus supplying synchronous clock signals to circuit components 失效
标题翻译：向电路部件提供同步时钟信号的方法和装置
公开(公告)号：US5586307A
公开(公告)日：1996-12-17
申请号：US86044
申请日：1993-06-30
申请人： Keng L. Wong , Kelly J. Fitzpatrick , Jeffrey E. Smith
发明人： Keng L. Wong , Kelly J. Fitzpatrick , Jeffrey E. Smith
IPC分类号： G06F1/10 , G06F1/32 , H01L21/82 , H01L21/822 , H01L27/04 , H03K5/15 , G06F1/12
CPC分类号： G06F1/3237 , G06F1/10 , G06F1/3203 , G06F1/3287 , Y02B60/1221 , Y02B60/1282
摘要： A clock distribution system and clock interrupt system for an integrated circuit device. Ignoring effects associated with the matched stages, the present invention includes a clock distribution and interrupt system for providing clock signals with less than 100 picoseconds of skew to various components of an integrated circuit device. The present invention utilizes several stages of drivers to evenly supply the distributed clock signals and each stage has RC matched input lines. The present invention advantageously locates the matched stages and clock drivers within the power supply ring of the integrated circuit located on the periphery of the microprocessor topology. This is done in order to better predict the topology surrounding these lines to match the capacitance of these lines. Further, this metal level offers a larger width dimension line (since as a top layer it may be thicker) having less resistance per unit area and also generally avoids spatial competition with other IC components and circuitry. The present invention additionally offers the capability of selectively powering down various components within the integrated device with a power management unit and enable network that is included as a component of the clock distribution system.
摘要翻译：用于集成电路设备的时钟分配系统和时钟中断系统。忽略与匹配级相关的效应，本发明包括时钟分配和中断系统，用于向集成电路器件的各种部件提供小于100皮秒的偏移的时钟信号。本发明利用几级驱动器均匀地提供分布式时钟信号，每级具有RC匹配输入线。本发明有利地位于位于微处理器拓扑周边的集成电路的电源环内的匹配级和时钟驱动器。这样做是为了更好地预测这些线路周围的拓扑，以匹配这些线路的电容。此外，该金属层提供更大的宽度尺寸线（因为顶层可以更厚），每单位面积的电阻较小，并且还通常避免与其它IC组件和电路的空间竞争。本发明另外提供了利用功率管理单元选择性地降低集成设备内的各种组件并使能作为时钟分配系统的组件被包括的网络的能力。

2. 发明授权

US5696953A Method and apparatus for power management of an integrated circuit 失效
标题翻译：集成电路的电源管理方法和装置
公开(公告)号：US5696953A
公开(公告)日：1997-12-09
申请号：US597363
申请日：1996-02-08
申请人： Keng L. Wong , Kelly J. Fitzpatrick , Jeffrey E. Smith
发明人： Keng L. Wong , Kelly J. Fitzpatrick , Jeffrey E. Smith
IPC分类号： G06F1/10 , G06F1/32 , H01L21/82 , H01L21/822 , H01L27/04 , H03K5/15
CPC分类号： G06F1/3237 , G06F1/10 , G06F1/3203 , G06F1/3287 , Y02B60/1221 , Y02B60/1282
摘要： A clock distribution system and clock interrupt system for an integrated circuit device. Ignoring effects associated with the matched stages, the present invention includes a clock distribution and interrupt system for providing clock signals with less than 100 picoseconds of skew to various components of an integrated circuit device. The present invention utilizes several stages of drivers to evenly supply the distributed clock signals and each stage has RC matched input lines. The present invention advantageously locates the matched stages and clock drivers within the power supply ring of the integrated circuit located on the periphery of the microprocessor topology. This is done in order to better predict the topology surrounding these lines to match the capacitance of these lines. Further, this metal level offers a larger width dimension line (since as a top layer it may be thicker) having less resistance per unit area and also generally avoids spatial competition with other IC components and circuitry. The present invention additionally offers the capability of selectively powering down various components within the integrated device with a power management unit and enable network that is included as a component of the clock distribution system.
摘要翻译：用于集成电路设备的时钟分配系统和时钟中断系统。忽略与匹配级相关的效应，本发明包括时钟分配和中断系统，用于向集成电路器件的各种部件提供小于100皮秒的偏移的时钟信号。本发明利用几级驱动器均匀地提供分布式时钟信号，每级具有RC匹配输入线。本发明有利地位于位于微处理器拓扑周边的集成电路的电源环内的匹配级和时钟驱动器。这样做是为了更好地预测这些线路周围的拓扑，以匹配这些线路的电容。此外，该金属层提供较大的宽度尺寸线（因为顶层可以较厚），每单位面积具有较小的电阻，并且还通常避免与其它IC组件和电路的空间竞争。本发明另外提供了利用功率管理单元选择性地降低集成设备内的各种组件并使能作为时钟分配系统的组件被包括的网络的能力。

3. 发明授权

US5564022A Method and apparatus for automatically inserting clock buffers into a logic block to reduce clock skew 失效
标题翻译：用于自动将时钟缓冲器插入到逻辑块中以减少时钟偏移的方法和装置
公开(公告)号：US5564022A
公开(公告)日：1996-10-08
申请号：US193789
申请日：1994-02-09
申请人： Goutam Debnath , Kelly J. Fitzpatrick
发明人： Goutam Debnath , Kelly J. Fitzpatrick
IPC分类号： G06F1/10 , G06F17/50 , H01L27/04
CPC分类号： G06F1/10 , G06F17/5077
摘要： A method and apparatus for inserting clock buffers to reduce clock skew in a logic block in which the proper placement of the cells within the logic block is first determined. Given this cell placement and the location of the local clock lines, the placement of clock buffers within the logic block is determined such that the clock buffers are in close proximity to the local clock lines. Routing is then performed to connect the clock buffers to their corresponding clock trunks and the cells requiring clock signals to their corresponding clock buffers. The performance of the logic block is then evaluated. If the performance does not satisfy a predetermined minimum threshold then the cells are modified to satisfy the minimum threshold, or come closer to attaining it. The clock buffers are removed, and the proper placement of the new cells within the logic block is determined. Given this new cell placement a new set of clock buffers is placed and a new routing is created. The performance is then re-evaluated and, if the minimum threshold still has not been attained, the above process is repeated.
摘要翻译：用于插入时钟缓冲器以减少逻辑块中的时钟偏移的方法和装置，其中首先确定逻辑块内的单元的适当放置。给定该单元布置和本地时钟线的位置，确定逻辑块内的时钟缓冲器的布置，使得时钟缓冲器紧邻本地时钟线。然后执行路由以将时钟缓冲器连接到它们对应的时钟中继线和将时钟信号需要到相应的时钟缓冲器的单元。然后评估逻辑块的性能。如果性能不满足预定的最小阈值，则修改单元以满足最小阈值，或者更接近实现该单元。时钟缓冲器被去除，并且确定新单元在逻辑块内的正确放置。给定这个新的单元格放置一组新的时钟缓冲器被放置并创建一个新的路由。然后再次评估性能，如果仍未达到最小阈值，则重复上述过程。

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