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    • 1. 发明授权
    • Method and apparatus for source synchronous data transfer
    • 源同步数据传输的方法和装置
    • US06178206B1
    • 2001-01-23
    • US09013479
    • 1998-01-26
    • Timothy W. KellyStephen S. PawlowskiKeith M. SelfJeffrey E. Smith
    • Timothy W. KellyStephen S. PawlowskiKeith M. SelfJeffrey E. Smith
    • H04L2500
    • H04L7/0331H04L7/0008
    • A method and apparatus is presented where for transmitting data between two or more components. Data signals are sent in parallel with a clocking signal (e.g., on a bus) so that the data signal can be latched in relation to the clocking signal. For example, two clocking signals, out of phase from each other by 180 degrees, can be sent on bidirectional clocking signal lines and data signals can be sent on a data signal line, the component receiving the clocking and data signals can latch the data signals on each high-to-low transition of either of the two clocking signals. Using the method and apparatus of the present invention, skew problems seen with other bus systems can be reduced which leads to an increase in data transfer rates.
    • 提出了一种用于在两个或更多个组件之间传输数据的方法和装置。 数据信号与时钟信号(例如,总线)并行地发送,使得可以相对于时钟信号锁存数据信号。 例如,可以在双向时钟信号线上发送彼此异相180度的两个时钟信号,并且数据信号可以在数据信号线上发送,接收时钟和数据信号的组件可以锁存数据信号 在两个时钟信号中的任一个的每个从高到低的转换。 使用本发明的方法和装置,可以减少其他总线系统所看到的偏斜问题,这导致数据传输速率的增加。
    • 2. 发明授权
    • Apparatus for receiving/transmitting signals in an input/output pad
buffer cell
    • 用于在输入/输出缓冲单元中接收/发送信号的装置
    • US6151257A
    • 2000-11-21
    • US13482
    • 1998-01-26
    • Smith E. JeffreyTimothy W. KellyStephen W. KissKeith M. Self
    • Smith E. JeffreyTimothy W. KellyStephen W. KissKeith M. Self
    • G11C7/10H03K19/003G11C7/00
    • G11C7/1093G11C7/1051G11C7/1078G11C7/1087H03K19/00323
    • An electronic circuit die is presented including a plurality of first and second input/output (I/O) pad buffer cells. The first I/O pad buffer cells include at least a latch for latching data signals received at a pad in the cell. Adjacent ones of these first I/O pad buffer cells are conductively coupled together using conductive trace pins. The second I/O pad buffer cells include a pad that receives clocking signal which are supplied to the latches of the first I/O pad buffer cells. Accordingly, data signals received at the pads of the die are latched in the pad as opposed to the core logic of the die. One benefit of providing the latching of data signals in the pad is that conductive traces between the latches and the core logic need not be precisely matched, thus reducing cost. Also, the first I/O pad buffer cells can be similarly constructed, thus reducing the complexity and cost of manufacture for the die.
    • 呈现包括多个第一和第二输入/输出(I / O)缓冲区单元的电子电路管芯。 第一I / O缓冲单元至少包括用于锁存在单元中的垫处接收的数据信号的锁存器。 这些第一I / O焊盘缓冲单元中的相邻的一个使用导电迹线引脚导电耦合在一起。 第二I / O焊盘缓冲单元包括接收提供给第一I / O缓冲单元的锁存器的时钟信号的焊盘。 因此,与芯片的核心逻辑相反,在芯片的焊盘处接收的数据信号被锁存在焊盘中。 在焊盘中提供数据信号锁存的一个好处是锁存器和核心逻辑之间的导电迹线不需要精确匹配,从而降低了成本。 此外,可以类似地构造第一I / O缓冲电池,从而降低了芯片制造的复杂性和成本。