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1. 发明授权

US07408420B2 Multi mode clock generator 有权
标题翻译：多模时钟发生器
公开(公告)号：US07408420B2
公开(公告)日：2008-08-05
申请号：US11237268
申请日：2005-09-27
申请人： Keng L. Wong , Feng Wang
发明人： Keng L. Wong , Feng Wang
IPC分类号： H03L7/00
CPC分类号： G06F1/04
摘要： In some embodiments, a clock generator is provided that provides a generator clock. The clock generator comprises a first clock source to provide a first clock and a second clock source to provide a second clock whose frequency at least indirectly tracks a supply to a clock distribution network. The clock generator selectably provides as the generator clock the first clock when the second clock leads the first clock and the second clock when it lags behind the first clock. Other embodiments are claimed and disclosed herein.
摘要翻译：在一些实施例中，提供了提供发生器时钟的时钟发生器。时钟发生器包括提供第一时钟和第二时钟源的第一时钟源，以提供其频率至少间接跟踪到时钟分配网络的电源的第二时钟。当第二个时钟引导第一个时钟时，时钟发生器可选地提供第一个时钟作为发生器时钟，而当第二个时钟滞后于第一个时钟时，时钟发生器可选择地提供第一个时钟。本文要求保护和公开其它实施例。

2. 发明授权

US07310020B2 Self-biased phased-locked loop 有权
公开(公告)号：US07310020B2
公开(公告)日：2007-12-18
申请号：US11321495
申请日：2005-12-29
申请人： Swee Boon Tan , Keng L. Wong
发明人： Swee Boon Tan , Keng L. Wong
IPC分类号： H03L7/00 , H03L7/099
CPC分类号： H03L7/0893 , H03L7/0995 , H03L2207/06
摘要： In general, in one aspect, the disclosure describes a phase-locked loop circuit. The circuit includes an oscillator having a first control input, a second control input, and a third control input, wherein the first control input, the second control input, and the third control input act to control output frequency of the oscillator. The circuit further includes a first charge pump and a second charge pump. A first bias generator is coupled to the first control input of the oscillator and can receive electrical input from the first charge pump. A second bias generator is coupled to the second control input of the oscillator and can receive electrical input from the first charge pump, the second charge pump, and the first bias generator. A third bias generator is coupled to the third control input of the oscillator and can receive electrical input from the second charge pump and the first bias generator.

3. 发明授权

US07242261B2 Voltage control for clock generating circuit 有权
标题翻译：时钟发生电路的电压控制
公开(公告)号：US07242261B2
公开(公告)日：2007-07-10
申请号：US10680498
申请日：2003-10-06
申请人： Keng L. Wong , Hong-Piao Ma , Greg F. Taylor
发明人： Keng L. Wong , Hong-Piao Ma , Greg F. Taylor
IPC分类号： H03B1/00
CPC分类号： H03K5/15013 , G06F1/10 , G06F1/28 , H03K3/011 , H03K3/0315 , H03K5/133
摘要： An apparatus is provided that includes a clock distribution network, a plurality of distributed oscillators provided about the clock distribution network so as to provide clock signals on the clock distribution network and a power control circuit to control power applied to the plurality of distributed oscillators. The power control circuit includes a bandgap device to produce a reference voltage based on a desired power level and a comparing/decision device to receive the reference voltage from the bandgap device and to receive the voltage signal from a source external to the apparatus. The comparing/decision device determines whether the signal received from the power source corresponds to the desired power level.
摘要翻译：提供了一种装置，其包括时钟分配网络，围绕时钟分配网络设置的多个分布式振荡器，以便在时钟分配网络上提供时钟信号;以及功率控制电路，用于控制施加到多个分布式振荡器的功率。功率控制电路包括用于基于期望功率电平产生参考电压的带隙装置和用于从带隙装置接收参考电压并且从设备外部的源接收电压信号的比较/判定装置。比较/判定装置确定从电源接收的信号是否对应于期望的功率电平。

4. 发明授权

US07197659B2 Global I/O timing adjustment using calibrated delay elements 有权
标题翻译：使用校准延迟元件的全局I / O定时调整
公开(公告)号：US07197659B2
公开(公告)日：2007-03-27
申请号：US09965223
申请日：2001-09-28
申请人： Chee How Lim , Keng L. Wong , Songmin Kim
发明人： Chee How Lim , Keng L. Wong , Songmin Kim
IPC分类号： G06F1/12
CPC分类号： H03L7/0812 , G06F1/10 , H03L7/07
摘要： A method transfers a signal from a transmitting device to a receiving device. The signal is output from the transmitting device using a driving circuit. A reference clock signal is received in the transmitting device. An output clock signal is generated according to the received reference clock signal and a feedback clock signal in a phase locked loop. A delay is provided in a path of the reference clock signal and a path of the feedback clock signal. The delay is configured to make the output signal meet a predetermined valid data timing requirement.
摘要翻译：一种方法将信号从发送设备传送到接收设备。使用驱动电路从发送装置输出信号。在发送装置中接收参考时钟信号。根据接收的参考时钟信号和锁相环中的反馈时钟信号产生输出时钟信号。在参考时钟信号的路径和反馈时钟信号的路径中提供延迟。延迟被配置为使输出信号满足预定的有效数据时序要求。

5. 发明授权

US07173461B2 Self-biased phased-locked loop 失效
标题翻译：自偏置锁相环
公开(公告)号：US07173461B2
公开(公告)日：2007-02-06
申请号：US11140684
申请日：2005-05-31
申请人： Swee Boon Tan , Keng L. Wong
发明人： Swee Boon Tan , Keng L. Wong
IPC分类号： H03L7/06
CPC分类号： H03L7/0893 , H03L7/093 , H03L7/0995 , H03L7/10
摘要： In general, in one aspect, the disclosure describes a phase-locked loop circuit. The circuit includes an oscillator having a first control input and a second control input, wherein the first control input and the second control input act to control output frequency of the oscillator. The circuit further includes a first charge pump and a second charge pump. A first bias generator is coupled to the first control input of the oscillator and can receive electrical input from the first charge pump and the second charge pump. A second bias generator is coupled to the second control input of the oscillator and can receive electrical input from the second charge pump and the first bias generator.
摘要翻译：通常，在一个方面，本公开描述了一种锁相环电路。该电路包括具有第一控制输入和第二控制输入的振荡器，其中第一控制输入和第二控制输入用于控制振荡器的输出频率。电路还包括第一电荷泵和第二电荷泵。第一偏置发生器耦合到振荡器的第一控制输入，并且可以接收来自第一电荷泵和第二电荷泵的电输入。第二偏置发生器耦合到振荡器的第二控制输入端并且可以接收来自第二电荷泵和第一偏置发生器的电输入。

6. 发明授权

US06809606B2 Voltage ID based frequency control for clock generating circuit 有权
标题翻译：用于时钟发生电路的基于电压ID的频率控制
公开(公告)号：US06809606B2
公开(公告)日：2004-10-26
申请号：US10136321
申请日：2002-05-02
申请人： Keng L. Wong , Hong-Piao Ma , Greg F. Taylor , Chee How Lim , Robert Greiner , Edward A. Burton , Douglas R. Huard
发明人： Keng L. Wong , Hong-Piao Ma , Greg F. Taylor , Chee How Lim , Robert Greiner , Edward A. Burton , Douglas R. Huard
IPC分类号： H03L100
CPC分类号： G06F1/3203 , G06F1/08 , G06F1/10 , H03L7/0995 , H03L7/18 , Y02D10/126
摘要： An apparatus and method are provided for operating a processor core. This may include a first circuit to operate at a frequency that is dependent on a power supply voltage. A frequency control circuit may be provided to control a frequency of the first circuit by directing a voltage regulator to increase or decrease the power supply voltage.
摘要翻译：提供了一种用于操作处理器核心的装置和方法。这可以包括在取决于电源电压的频率下操作的第一电路。可以提供频率控制电路以通过引导电压调节器来增加或减少电源电压来控制第一电路的频率。

7. 发明授权

US06778033B2 Voltage control for clock generating circuit 有权
公开(公告)号：US06778033B2
公开(公告)日：2004-08-17
申请号：US10136318
申请日：2002-05-02
申请人： Keng L. Wong , Hong-Piao Ma , Greg F. Taylor
发明人： Keng L. Wong , Hong-Piao Ma , Greg F. Taylor
IPC分类号： H03B100
CPC分类号： H03K5/15013 , G06F1/10 , G06F1/28 , H03K3/011 , H03K3/0315 , H03K5/133
摘要： An apparatus is provided that includes a clock distribution network, a plurality of distributed oscillators provided about the clock distribution network so as to provide clock signals on the clock distribution network and a power control circuit to control power applied to the plurality of distributed oscillators. The power control circuit includes a bandgap device to produce a reference voltage based on a desired power level and a comparing/decision device to receive the reference voltage from the bandgap device and to receive the voltage signal from a source external to the apparatus. The comparing/decision device determines whether the signal received from the power source corresponds to the desired power level.

8. 发明授权

US06771134B2 Frequency control for clock generating circuit 有权
标题翻译：时钟发生电路的频率控制
公开(公告)号：US06771134B2
公开(公告)日：2004-08-03
申请号：US10136474
申请日：2002-05-02
申请人： Keng L. Wong , Hong-Piao Ma , Greg F. Taylor , Chee How Lim , Edward A. Burton
发明人： Keng L. Wong , Hong-Piao Ma , Greg F. Taylor , Chee How Lim , Edward A. Burton
IPC分类号： H03B2700
CPC分类号： H03L7/0995 , G06F1/08 , G06F1/10 , H03L7/18
摘要： A clock generating circuit is provided that includes a plurality of distributed ring oscillators to drive a clock distribution network. Multiplexing devices may select a length or delay of each of the ring oscillators. The variable length or delay may thereby adjust the frequency of the clock generating circuit.
摘要翻译：提供了一种时钟发生电路，其包括多个分布式环形振荡器以驱动时钟分配网络。多路复用器件可以选择每个环形振荡器的长度或延迟。因此，可变长度或延迟可以调节时钟发生电路的频率。

9. 发明授权

US06614317B2 Variable lock window for a phase locked loop 失效
公开(公告)号：US06614317B2
公开(公告)日：2003-09-02
申请号：US09865299
申请日：2001-05-24
申请人： Keng L. Wong , Usman Azeez Mughal , Masud Kamal , Chee How Lim , Kent R. Callahan
发明人： Keng L. Wong , Usman Azeez Mughal , Masud Kamal , Chee How Lim , Kent R. Callahan
IPC分类号： H03L700
CPC分类号： H03L7/095 , H03L7/0891 , Y10S331/02
摘要： A lock detector system which operates adaptively based on a frequency of operation. Different lock windows are defined for different frequencies of operation and are automatically formed based on the controlled signal that is used to drive the voltage controlled oscillator of the phase locked loop.

10. 发明授权

US06469533B1 Measuring a characteristic of an integrated circuit 有权
标题翻译：测量集成电路的特性
公开(公告)号：US06469533B1
公开(公告)日：2002-10-22
申请号：US09545922
申请日：2000-04-10
申请人： Nasser A. Kurd , Keng L. Wong , Rachael J. Parker , Hung-Piao Ma
发明人： Nasser A. Kurd , Keng L. Wong , Rachael J. Parker , Hung-Piao Ma
IPC分类号： G01R3102
CPC分类号： G01R31/31926 , G01R31/31905 , G01R31/31915
摘要： An integrated circuit includes a first circuit, a second circuit, at least one test pad and multiplexing circuitry. The second circuit is coupled to the first circuit and has substantially the same design as the first circuit to emulate an electrical characteristic of the first circuit. The multiplexing circuitry selectively couples the test pad(s) to the second circuit to selectively measure the electrical characteristic.
摘要翻译：集成电路包括第一电路，第二电路，至少一个测试焊盘和复用电路。第二电路耦合到第一电路并且具有与第一电路基本相同的设计，以模拟第一电路的电特性。多路复用电路选择性地将测试焊盘耦合到第二电路以选择性地测量电特性。

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