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1. 发明授权

US6006607A Piezoresistive pressure sensor with sculpted diaphragm 失效
标题翻译：压电式压力传感器，带雕刻膜片
公开(公告)号：US6006607A
公开(公告)日：1999-12-28
申请号：US144118
申请日：1998-08-31
申请人： Janusz Bryzek , David W. Burns , Sean S. Cahill , Steven S. Nasiri , James B. Starr
发明人： Janusz Bryzek , David W. Burns , Sean S. Cahill , Steven S. Nasiri , James B. Starr
IPC分类号： G01L9/00 , G01L9/06
CPC分类号： G01L9/0042 , G01L9/0054
摘要： The present invention is a semiconductor pressure sensor. In one embodiment, the semiconductor pressure sensor includes a diaphragm having a first thickness and at least cone raised boss that is coupled to a first side of the diaphragm. The at least one raised boss increases the diaphragm thickness in the region occupied by the at least one raised boss to a second thickness. A plurality of piezoresistors are disposed on a second side of the diaphragm in regions of the first thickness. In another embodiment, a semiconductor pressure sensor diaphragm includes at least one raised boss disposed along a central axis on a first side of the diaphragm. At least two raised bridge regions are disposed along the central axis, interconnecting the at least one raised boss and a diaphragm edge. Each raised bridge region is narrower than the raised boss. A plurality of piezoresistors are disposed on the raised bridge regions of the diaphragm along the central axis.
摘要翻译：本发明是半导体压力传感器。在一个实施例中，半导体压力传感器包括具有第一厚度和至少锥形凸起的隔膜，该凸起联接到隔膜的第一侧。所述至少一个凸起凸台将所述至少一个凸起凸起所占据的区域中的隔膜厚度增加到第二厚度。多个压电电阻器设置在第一厚度的区域中的隔膜的第二侧上。在另一个实施例中，半导体压力传感器膜片包括至少一个凸起的凸起部分，其沿着中心轴线设置在隔膜的第一侧上。至少两个凸起的桥接区域沿着中心轴线布置，将至少一个凸起的凸起和隔膜边缘互连。每个凸起的桥梁区域比凸起的凸起更窄。多个压电电阻器沿着中心轴设置在隔膜的凸起的桥接区域上。

2. 发明授权

US06351996B1 Hermetic packaging for semiconductor pressure sensors 有权
标题翻译：半导体压力传感器的气密封装
公开(公告)号：US06351996B1
公开(公告)日：2002-03-05
申请号：US09191718
申请日：1998-11-12
申请人： Steven S. Nasiri , David W. Burns , Janusz Bryzek , Sean S. Cahill
发明人： Steven S. Nasiri , David W. Burns , Janusz Bryzek , Sean S. Cahill
IPC分类号： G01L904
CPC分类号： G01L19/147 , G01L19/0038 , G01L19/0084
摘要： A hermetic media interface for a sensor package is disclosed. Preferably, the hermetic media interface is incorporated into a pressure sensor package for interfacing directly to fluid and/or gaseous media. In one embodiment, the pressure sensor package includes a semiconductor die and a pressure port that are housed in a pre-molded plastic package. A eutectic solder is coupled between the semiconductor die and the pressure port to solder the same to the semiconductor die. The semiconductor die may be metallized to enhance solderability. In an alternative embodiment, the pressure port is made from one or more plastic materials and the pressure port is attached to the semiconductor die with an adhesive. An integral stress-isolation region may optionally be incorporated on the semiconductor die.
摘要翻译：公开了一种用于传感器封装的密封介质接口。优选地，密封介质界面结合到压力传感器封装中，用于直接与流体和/或气体介质接合。在一个实施例中，压力传感器封装包括容纳在预模制塑料封装中的半导体管芯和压力端口。共晶焊料耦合在半导体管芯和压力端口之间以将其焊接到半导体管芯。半导体管芯可以被金属化以增强可焊性。在替代实施例中，压力端口由一种或多种塑料材料制成，并且压力端口用粘合剂附接到半导体管芯。整体应力隔离区可任选地并入半导体管芯上。

3. 发明授权

US06346742B1 Chip-scale packaged pressure sensor 失效
标题翻译：芯片级封装压力传感器
公开(公告)号：US06346742B1
公开(公告)日：2002-02-12
申请号：US09190500
申请日：1998-11-12
申请人： Janusz Bryzek , David W. Burns , Sean S. Cahill , Steven S. Nasiri
发明人： Janusz Bryzek , David W. Burns , Sean S. Cahill , Steven S. Nasiri
IPC分类号： H01L2312
CPC分类号： G01L19/147 , G01L19/0038 , G01P2015/0828 , H01L2224/48091 , H01L2924/01322 , H01L2924/10253 , H01L2924/00014 , H01L2924/00
摘要： A chip-scale sensor package is described. In one embodiment, the chip-scale sensor package includes a semiconductor substrate having a sensor region, and a semiconductor cap having a recess. The semiconductor cap is bonded to the semiconductor substrate with a thermocompression bond to form a cavity therebetween. The semiconductor substrate is bonded to the semiconductor cap using different types of materials. The semiconductor substrate and/or the semiconductor cap may optionally include a semiconductor device such as an electronically trimmable integrated circuit fabricated thereon. In addition, the semiconductor substrate may optionally include an integral stress isolation flexible region for isolation of the sensor region.
摘要翻译：描述了芯片级传感器封装。在一个实施例中，芯片级传感器封装包括具有传感器区域的半导体衬底和具有凹部的半导体盖。半导体盖通过热压接合到半导体衬底上以在其间形成空腔。使用不同类型的材料将半导体衬底接合到半导体帽。半导体衬底和/或半导体帽可以可选地包括诸如其上制造的电子可调整体集成电路的半导体器件。此外，半导体衬底可以可选地包括用于隔离传感器区域的整体应力隔离柔性区域。

4. 发明授权

US06229190B1 Compensated semiconductor pressure sensor 有权
标题翻译：补偿半导体压力传感器
公开(公告)号：US06229190B1
公开(公告)日：2001-05-08
申请号：US09216073
申请日：1998-12-18
申请人： Janusz Bryzek , David W. Burns , Steven S. Nasiri , Sean S. Cahill
发明人： Janusz Bryzek , David W. Burns , Steven S. Nasiri , Sean S. Cahill
IPC分类号： H01L2982
CPC分类号： G01L19/147 , G01L9/0042 , G01L9/0054 , G01L19/0038 , G01L19/143 , G01P2015/084 , H01L2224/48091 , H01L2224/48247 , H01L2924/16151 , H01L2924/16195 , H01L2924/00014
摘要： A semiconductor pressure sensor compatible with fluid and gaseous media applications is described. The semiconductor pressure sensor includes a sensor capsule having a semiconductor die and a silicon cap that is bonded to the semiconductor die. The semiconductor die includes a diaphragm that incorporates piezoresistive sensors thereon, and a stress isolation mechanism for isolating the diaphragm from packaging and mounting stresses. The silicon cap includes a cavity for allowing the diaphragm to deflect. The semiconductor pressure sensor further includes a pressure port that is hermetically attached to the semiconductor die. The sensor capsule and pressure port may be incorporated into a plastic housing. In one embodiment, the silicon cap is bonded to the semiconductor die to form an integral pressure reference. In an alternative embodiment, a second pressure port is provided for allowing gage or differential pressure measurements. A technique for incorporating the piezoresistive sensors is also described. An ASIC may be optionally attached to the silicon cap, and/or active electronic circuitry may be fabricated on the semiconductor die or silicon cap. Additional coatings may be optionally applied to the pressure port and semiconductor die for enhancing chemical resistance.
摘要翻译：描述了与流体和气体介质应用相兼容的半导体压力传感器。半导体压力传感器包括具有半导体管芯和粘合到半导体管芯上的硅帽的传感器封装。半导体管芯包括在其上结合有压阻传感器的隔膜以及用于将隔膜与封装和安装应力隔离的应力隔离机构。硅帽包括用于允许隔膜偏转的空腔。半导体压力传感器还包括气密地附接到半导体管芯的压力端口。传感器胶囊和压力端口可以结合到塑料外壳中。在一个实施例中，硅帽结合到半导体管芯以形成整体的压力参考。在替代实施例中，提供了用于允许量规或差压测量的第二压力端口。还描述了一种用于结合压阻传感器的技术。 ASIC可以可选地附接到硅帽，和/或有源电子电路可以制造在半导体管芯或硅帽上。另外的涂层可以任选地施加到压力端口和半导体管芯上以提高耐化学性。

5. 发明授权

US06255728B1 Rigid encapsulation package for semiconductor devices 有权
标题翻译：用于半导体器件的刚性封装封装
公开(公告)号：US06255728B1
公开(公告)日：2001-07-03
申请号：US09232801
申请日：1999-01-15
申请人： Steven S. Nasiri , David W. Burns , Janusz Bryzek
发明人： Steven S. Nasiri , David W. Burns , Janusz Bryzek
IPC分类号： H01L2312
CPC分类号： G01L19/147 , G01L19/0038 , G01L19/0084 , H01L2224/48091 , H01L2924/00014
摘要： A rigid encapsulation package for semiconductor sensors, actuators, and devices is described. In one embodiment, a semiconductor pressure sensor includes a sensor element having a deformable diaphragm for measurement of pressure, and a cap that includes a recess. The cap is attached to the sensor element to form a cavity therebetween. The pressure sensor further includes a leadframe, interconnecting bond wires, a pressure port that is coupled to the sensor element, and a nominally rigid material formed over the sensor element, cap, leadframe, and bond wires. The material may include one or more of the following: epoxy, RTV, resins, and gel. The sensor element may include a built-in stress isolation flexible region. A second pressure port may optionally be attached to the housing for providing differential or gage pressure measurements.
摘要翻译：描述了用于半导体传感器，致动器和装置的刚性封装封装。在一个实施例中，半导体压力传感器包括具有用于测量压力的可变形隔膜的传感器元件和包括凹部的盖。盖连接到传感器元件以在它们之间形成空腔。压力传感器还包括引线框架，互连接合线，耦合到传感器元件的压力端口，以及形成在传感器元件，盖子，引线框架和接合线上的标称刚性材料。该材料可以包括以下一种或多种：环氧树脂，RTV，树脂和凝胶。传感器元件可以包括内置的应力隔离柔性区域。可以可选地将第二压力端口附接到壳体以提供差压或量规压力测量。

6. 发明授权

US6147397A Stress isolated integrated circuit and method for making 有权
标题翻译：应力隔离集成电路及其制造方法
公开(公告)号：US6147397A
公开(公告)日：2000-11-14
申请号：US473549
申请日：1999-12-28
申请人： David W. Burns , Janusz Bryzek
发明人： David W. Burns , Janusz Bryzek
IPC分类号： H01L21/764 , H01L23/10 , H01L23/16 , H01L23/495 , H01L23/12 , H01L23/48
CPC分类号： H01L23/10 , H01L21/764 , H01L23/16 , H01L2224/48091 , H01L2224/48247 , H01L2924/10253
摘要： A stress-isolated integrated circuit includes a semiconductor die (24) having first and second surfaces (28, 32) and a semi-circumferential trench (44) formed into the first surface of the die to define a stress-isolated region (48). At least some of the active IC components are located in the stress-isolated region. A cavity (46) is formed into the second surface of the die, the cavity being sized so that the trench opens into the cavity to create a cantilevered stress-isolated region extending from the remainder of the die. The second surface of the die is secured to a lead frame (36), the lead frame having bond wires (42) secured to bond pads (26) on the die. A molding compound (54) encapsulates the die, the cap, the bond wires and a portion of the lead frame to create a molded IC device (20). The invention helps to improve performance characteristics and component variables of analog and mixed-signal integrated circuits by isolating critical portions of the integrated circuits from detrimental packaging and molding stresses.
摘要翻译：应力隔离集成电路包括具有第一和第二表面（28,32）的半导体管芯（24）和形成在管芯的第一表面中的半周向沟槽（44），以限定应力隔离区域（48）。至少一些有源IC部件位于应力隔离区域中。空腔（46）形成在模具的第二表面中，空腔的尺寸设计成使得沟槽开口到空腔中以产生从模具的其余部分延伸的悬臂应力隔离区域。管芯的第二表面被固定到引线框架（36），引线框架具有固定到管芯上的接合焊盘（26）的接合线（42）。模制化合物（54）封装模具，盖子，接合线和引线框架的一部分以形成模制的IC器件（20）。本发明有助于通过将集成电路的关键部分与有害的封装和模制应力隔离来改善模拟和混合信号集成电路的性能特征和分量变量。

7. 发明申请

US20210124544A1 Mobile Display Device with Multiple Display Panels and Segregated System Components 有权
公开(公告)号：US20210124544A1
公开(公告)日：2021-04-29
申请号：US17083274
申请日：2020-10-28
申请人： David W. Burns , Debra Brubaker Burns
发明人： David W. Burns , Debra Brubaker Burns
IPC分类号： G06F3/14 , G06F1/16
摘要： A mobile display device may include a first display panel with a display screen having a viewing surface and a second display panel with a display screen having a viewing surface. The display panels may be coupled with a multi-position hinge. A first operating system may be coupled to the first display panel and a second operating system may be coupled to the second display panel. The first operating system may operate independently of the second operating system and the second operating system may operate independently of the first operating system.

8. 发明授权

US08850165B2 Method and apparatus for assigning thread priority in a processor or the like 有权
标题翻译：用于在处理器等中分配线程优先级的方法和装置
公开(公告)号：US08850165B2
公开(公告)日：2014-09-30
申请号：US13155055
申请日：2011-06-07
申请人： David W. Burns , James D. Allen , Michael D. Upton , Darrell D. Boggs , David J. Sager
发明人： David W. Burns , James D. Allen , Michael D. Upton , Darrell D. Boggs , David J. Sager
IPC分类号： G06F9/38 , G06F9/48
CPC分类号： G06F9/4881 , G06F9/3851
摘要： In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further augment, the effectiveness of the thread precedence counters, starting counters are associated with each thread that serve as a multiplier for the value to be used in the thread precedence counter. The value in the starting counters are manipulated so as to prevent one thread from getting undue priority to the resources of the multi-threaded processor.
摘要翻译：在多线程处理器中，线程优先级变量被设置在内存中。线程优先级的实际分配基于线程优先级计数器的到期。为了进一步扩展，线程优先级计数器的有效性，起始计数器与用作在线程优先级计数器中使用的值的乘数的每个线程相关联。操作起始计数器中的值以防止一个线程对多线程处理器的资源不适当地优先。

9. 发明申请

US20110239221A1 Method and Apparatus for Assigning Thread Priority in a Processor or the Like 有权
标题翻译：用于在处理器等中分配线程优先级的方法和装置
公开(公告)号：US20110239221A1
公开(公告)日：2011-09-29
申请号：US13155055
申请日：2011-06-07
申请人： David W. Burns , James D. Allen , Michael D. Upton , Darrell D. Boggs , David J. Sager
发明人： David W. Burns , James D. Allen , Michael D. Upton , Darrell D. Boggs , David J. Sager
IPC分类号： G06F9/46
CPC分类号： G06F9/4881 , G06F9/3851
摘要： In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further augment, the effectiveness of the thread precedence counters, starting counters are associated with each thread that serve as a multiplier for the value to be used in the thread precedence counter. The value in the starting counters are manipulated so as to prevent one thread from getting undue priority to the resources of the multi-threaded processor.
摘要翻译：在多线程处理器中，线程优先级变量被设置在内存中。线程优先级的实际分配基于线程优先级计数器的到期。为了进一步扩展，线程优先级计数器的有效性，起始计数器与用作在线程优先级计数器中使用的值的乘数的每个线程相关联。操作起始计数器中的值以防止一个线程对多线程处理器的资源不适当地优先。

10. 发明授权

US07877583B2 Method and apparatus for assigning thread priority in a processor or the like 有权
公开(公告)号：US07877583B2
公开(公告)日：2011-01-25
申请号：US12267394
申请日：2008-11-07
申请人： David W. Burns , James D. Allen , Michael D. Upton , Darrell D. Boggs , David J. Sager
发明人： David W. Burns , James D. Allen , Michael D. Upton , Darrell D. Boggs , David J. Sager
IPC分类号： G06F9/30
CPC分类号： G06F9/4881 , G06F9/3851
摘要： In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further augment, the effectiveness of the thread precedence counters, starting counters are associated with each thread that serve as a multiplier for the value to be used in the thread precedence counter. The value in the starting counters are manipulated so as to prevent one thread from getting undue priority to the resources of the multi-threaded processor.

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