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1. 发明授权

US06828669B2 Interconnection substrate having metal columns covered by a resin film, and manufacturing method thereof 有权
标题翻译：具有由树脂膜覆盖的金属柱的互连基板及其制造方法
公开(公告)号：US06828669B2
公开(公告)日：2004-12-07
申请号：US09736864
申请日：2000-12-14
申请人： Takahiro Iijima , Shinichi Wakabayashi , Yuichi Matsuda
发明人： Takahiro Iijima , Shinichi Wakabayashi , Yuichi Matsuda
IPC分类号： H01L2312
CPC分类号： H01L24/12 , H01L21/76885 , H01L23/49811 , H01L24/11 , H01L24/16 , H01L2224/05568 , H01L2224/05573 , H01L2224/13021 , H01L2224/13099 , H01L2224/16237 , H01L2224/81385 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/014 , H01L2924/09701 , H01L2924/12042 , H01L2924/15311 , H01L2924/15787 , H05K1/0271 , H05K1/111 , H05K3/3436 , H05K3/3452 , H05K2201/09736 , H05K2201/0989 , H05K2201/10674 , H05K2203/0597 , Y02P70/611 , Y10S428/901 , Y10T29/49126 , H01L2924/00 , H01L2224/05599
摘要： An interconnection substrate comprises an uppermost interconnection layer having a plurality of terminal pads located at positions corresponding to a plurality of solder bumps (external connection terminals) provided on a semiconductor element which is to be mounted on the interconnection substrate. The interconnection substrate also has a metal column formed on each of the terminal pads and has a resin film covering a side surface of the metal column. The interconnection substrate further has an insulating layer formed on the uppermost interconnection layer so that a gap is formed between the insulating layer and an outer peripheral surface of the resin film.
摘要翻译：互连基板包括最上面的互连层，其具有位于与要安装在互连基板上的半导体元件上的多个焊料凸块（外部连接端子）对应的位置处的多个端子焊盘。互连基板还具有形成在每个端子焊盘上的金属柱，并且具有覆盖金属柱的侧表面的树脂膜。互连衬底还具有形成在最上层的互连层上的绝缘层，从而在绝缘层和树脂膜的外周表面之间形成间隙。

2. 发明授权

US06784535B1 Composite lid for land grid array (LGA) flip-chip package assembly 有权
标题翻译：复合盖板用于焊盘阵列（LGA）倒装芯片组装
公开(公告)号：US06784535B1
公开(公告)日：2004-08-31
申请号：US10631130
申请日：2003-07-31
申请人： Tz-Cheng Chiu
发明人： Tz-Cheng Chiu
IPC分类号： H01L2312
CPC分类号： H01L23/04 , H01L23/10 , H01L2224/16 , H01L2224/73204 , H01L2224/73253 , H01L2924/00014 , H01L2924/01019 , H01L2924/10253 , H01L2924/15311 , H01L2924/16152 , H01L2924/16195 , H01L2224/0401
摘要： A composite lid for a semiconductor package, in which the lid includes at least two materials. The first material is disposed over and attached to the back surface of the die with a low-modulus thermal gel and the second material is disposed towards the perimeter of the lid. The second material has a modulus of elasticity greater than the modulus of elasticity of the first material, and preferably, at least twice that of the first material.
摘要翻译：一种用于半导体封装的复合盖，其中所述盖包括至少两种材料。第一种材料用低模量热凝胶设置在模具的后表面并附着于模具的后表面，并且第二材料朝向盖的周边设置。第二材料的弹性模量大于第一材料的弹性模量，优选为第一材料的弹性模量的至少两倍。

3. 发明授权

US06781230B2 Flat circuit interconnecting device 有权
标题翻译：扁平电路互连装置
公开(公告)号：US06781230B2
公开(公告)日：2004-08-24
申请号：US10195393
申请日：2002-07-16
申请人： Masashi Tsukamoto
发明人： Masashi Tsukamoto
IPC分类号： H01L2312
CPC分类号： H01R12/592 , H01R13/6461 , H05K1/118 , H05K2201/10189
摘要： A flat circuit device without additional terminals can be connected with a connector. An insulator includes a bent portion and a laminated portion of a first and a second insulators forming the bent portion, and ends of a first conductor and a second conductor extend straightly at the bent portion along a curved surface of the bent portion. Thereby, the first conductor and the second conductor are formed straightly in parallel on an outer surface of the bent portion so that the bent portion performs as a connecting terminal.
摘要翻译：没有附加端子的扁平电路装置可以与连接器连接。绝缘体包括形成弯曲部分的第一和第二绝缘体的弯曲部分和层压部分，并且第一导体和第二导体的端部沿着弯曲部分的弯曲表面在弯曲部分处直线延伸。由此，第一导体和第二导体在弯曲部的外表面上平行地形成为弯曲部作为连接端子。

4. 发明授权

US06759746B1 Die attachment and method 失效
标题翻译：模具附件和方法
公开(公告)号：US06759746B1
公开(公告)日：2004-07-06
申请号：US09527281
申请日：2000-03-17
申请人： Robert Bruce Davies
发明人： Robert Bruce Davies
IPC分类号： H01L2312
CPC分类号： H01L23/66 , H01L21/76224 , H01L21/764 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a semiconductor device including a die attach surface having a first pedestal and a first semiconductor die having a first surface formed with a first cavity for mounting the first semiconductor die on the first pedestal. Further provision is made for the formation of a dielectric cavity in the semiconductor die, the first pedestal or both. The cavity allows for fields produced by electronic components disposed on the upper surface of the semiconductor die to penetrate into the dielectric cavity. Inclusion of a second pedestal on a common die attach surface and a second semiconductor die having second cavity for mounting provides for substantially coplanar precision alignment or the first and second semiconductor die.
摘要翻译：一种用于形成半导体器件的方法，该半导体器件包括具有第一基座的管芯附着表面和具有第一表面的第一半导体管芯，该第一表面形成有用于将第一半导体管芯安装在第一基座上的第一腔体。进一步提供在半导体管芯，第一基座或两者中形成电介质腔。空腔允许设置在半导体管芯的上表面上的电子部件产生的场渗透到介电腔中。将第二基座包括在共同的芯片附接表面上，并且具有用于安装的第二腔的第二半导体管芯提供基本上共面的精密对准或第一和第二半导体管芯。

5. 发明授权

US06747350B1 Flip chip package structure 有权
标题翻译：倒装芯片封装结构
公开(公告)号：US06747350B1
公开(公告)日：2004-06-08
申请号：US10455525
申请日：2003-06-06
申请人： Wei-Feng Lin , Yin-Chieh Hsueh , Chung-Ju Wu
发明人： Wei-Feng Lin , Yin-Chieh Hsueh , Chung-Ju Wu
IPC分类号： H01L2312
CPC分类号： H01L23/3128 , H01L21/563 , H01L23/49822 , H01L23/552 , H01L24/32 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2924/14 , H01L2924/15311 , H01L2924/16152 , H01L2924/166 , H01L2924/19041 , H01L2924/3011 , H01L2924/3025 , H01L2924/00
摘要： A flip chip package structure. The structure includes a substrate, an IC chip electrically connected to the substrate through a plurality of conductive bumps, encapsulant between the substrate and IC chip, and an electrically protective device. The substrate has interior wiring, a plurality of first contacts arranged at a predetermined pitch among each other on a surface, and a trace line area beyond the first contacts on the surface. The electrically protective device has a protruding part covering the IC chip, and an extending part extending over the surface of the substrate with a gap as large as 40 mil. The extending part further covers the trace line area, and connects to the surface of the substrate using a fixing material.
摘要翻译：倒装芯片封装结构。该结构包括基板，通过多个导电凸块电连接到基板的IC芯片，基板和IC芯片之间的密封剂以及电保护装置。衬底具有内部布线，在表面上彼此以预定间距布置的多个第一触点以及超过表面上的第一触点的迹线区域。电保护装置具有覆盖IC芯片的突出部分和在基板的表面上延伸大约40密耳的间隙的延伸部分。延伸部分进一步覆盖迹线区域，并使用固定材料连接到基板的表面。

6. 发明授权

US06734550B2 In-situ cap and method of fabricating same for an integrated circuit device 有权
标题翻译：用于集成电路器件的原位盖及其制造方法
公开(公告)号：US06734550B2
公开(公告)日：2004-05-11
申请号：US10270872
申请日：2002-10-15
申请人： John R. Martin , Richard H. Morrison, Jr.
发明人： John R. Martin , Richard H. Morrison, Jr.
IPC分类号： H01L2312
CPC分类号： B81B7/0077 , B81B7/0064 , B81C2203/0136 , B81C2203/0145 , B81C2203/0154 , H01H59/0009 , H01L21/50 , H01L23/10 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/73265 , H01L2924/1433 , H01L2924/00014 , H01L2924/00
摘要： An in-situ cap for an integrated circuit device such as a micromachined device and a method of making such a cap by fabricating an integrated circuit element on a substrate; forming a support layer over the integrated circuit element and forming a cap structure in the support layer covering the integrated circuit element.
摘要翻译：用于诸如微加工装置的集成电路装置的原位盖和通过在基板上制造集成电路元件来制造这种盖的方法; 在所述集成电路元件上形成支撑层，并在覆盖所述集成电路元件的所述支撑层中形成盖结构。

7. 发明授权

US06707157B2 Three dimensional semiconductor integrated circuit device having a piercing electrode 有权
标题翻译：具有穿孔电极的三维半导体集成电路器件
公开(公告)号：US06707157B2
公开(公告)日：2004-03-16
申请号：US09982963
申请日：2001-10-22
申请人： Masataka Hoshino
发明人： Masataka Hoshino
IPC分类号： H01L2312
CPC分类号： H01L27/0688 , H01L21/76898 , H01L23/481 , H01L23/5329 , H01L2224/05571 , H01L2224/05573 , H01L2224/16145 , H01L2924/00011 , H01L2924/00014 , H01L2924/01019 , H01L2924/12044 , H01L2924/15311 , H01L2224/48 , H01L2224/05644 , H01L2224/05647 , H01L2924/01004
摘要： A semiconductor device, includes a semiconductor substrate having a first surface and a second surface opposite the first surface, and having a piercing hole piercing there-through from the first surface to the second surface, an insulating film formed on the first surface of the semiconductor substrate having the piercing hole extended there-through and a piercing electrode formed in the piercing hole and extending from the insulating surface to the second surface, wherein the piercing hole has a first diameter in the insulating film and a second diameter in the semiconductor substrate which is wider than the first diameter, the piercing electrode has a substantially same diameter as the first diameter along a whole length thereof, and an insulating film sleeve lies between the piercing electrode and an inside wall of the piercing hole in the semiconductor substrate.
摘要翻译：一种半导体器件，包括具有第一表面和与第一表面相对的第二表面的半导体衬底，并且具有从第一表面到第二表面穿过穿孔的半导体衬底，形成在半导体的第一表面上的绝缘膜具有穿孔延伸穿过的基板和形成在穿孔中并从绝缘表面延伸到第二表面的穿孔电极，其中穿孔在绝缘膜中具有第一直径，在半导体基板中具有第二直径，比第一直径宽，穿孔电极的整体长度与第一直径基本相同，绝缘膜套筒位于穿孔电极和半导体衬底的穿孔孔内壁之间。

8. 发明授权

US06653720B2 Semiconductor electronic parts 有权
公开(公告)号：US06653720B2
公开(公告)日：2003-11-25
申请号：US10174111
申请日：2002-06-18
申请人： Yutaka Kameda
发明人： Yutaka Kameda
IPC分类号： H01L2312
CPC分类号： H01L24/32 , H01L21/563 , H01L23/49575 , H01L24/29 , H01L24/45 , H01L24/48 , H01L29/0657 , H01L2224/05554 , H01L2224/16145 , H01L2224/26145 , H01L2224/27013 , H01L2224/32145 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/73203 , H01L2224/73204 , H01L2224/83051 , H01L2224/83102 , H01L2224/83365 , H01L2224/83385 , H01L2224/92125 , H01L2924/00014 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/10157 , H01L2924/10162 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/00012 , H01L2924/00 , H01L2924/10155 , H01L2224/45015 , H01L2924/207
摘要： Semiconductor electronic parts 1 comprises electrode pads 7 formed on the surface of a base 2 and adapted to be connected to respective electrode terminals 4 and a bare chip 3 adhesive bonded to the surface of the base 2, wherein adhesive flow-in preventing means 12 is provided between the bare chip 3 and each of the electrode pad 7 for preventing the adhesive 10 for adhesive bonding the bare chip 3 to the base 2 from flowing in the electrode pads 7. Therefore, in an underfill process of adhesive bonding the base 2 to the bare chip 3 placed on the upper part thereof and sealing a gap between both of them with the adhesive 10 during manufacturing semiconductor electronic parts, the adhesive 10 is prevented from flowing out of the outside edge of the bare chip 3 and from depositing on the electrode pads 7 formed on the base 2.

9. 发明授权

US06611054B1 IC package lid for dose enhancement protection 失效
标题翻译： IC封装盖用于剂量增强保护
公开(公告)号：US06611054B1
公开(公告)日：2003-08-26
申请号：US08171998
申请日：1993-12-22
申请人： Thomas J. Dunaway , Richard K. Spielberger
发明人： Thomas J. Dunaway , Richard K. Spielberger
IPC分类号： H01L2312
CPC分类号： H01L23/06 , H01L23/10 , H01L23/552 , H01L24/48 , H01L2224/05599 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2224/85399 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/1616 , H01L2924/1617 , H01L2924/16195 , H01L2224/45015 , H01L2924/207 , H01L2924/00
摘要： An integrated circuit package for use in radiation environments includes a base for receiving an integrated circuit die and has a peripheral surface for receiving a lid. The lid has an inner surface facing the die that has a cladding of a low atomic number material to limit electron emission due to absorbed radiation.
摘要翻译：用于辐射环境的集成电路封装包括用于接收集成电路管芯并具有用于接收盖子的外围表面的基座。盖具有面向模具的内表面，其具有低原子序数材料的包层，以限制由于吸收的辐射引起的电子发射。

10. 发明授权

US06593650B2 Plasma induced depletion of fluorine from surfaces of fluorinated low-k dielectric materials 失效
公开(公告)号：US06593650B2
公开(公告)日：2003-07-15
申请号：US10050463
申请日：2002-01-15
申请人： Steven Towle , Ebrahim Andideh , Lawrence D. Wong
发明人： Steven Towle , Ebrahim Andideh , Lawrence D. Wong
IPC分类号： H01L2312
CPC分类号： H01L21/31058 , H01L21/0212 , H01L21/02126 , H01L21/0234 , H01L21/3105 , H01L21/76826 , H01L21/76829 , H01L21/76831 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A low dielectric constant material having a first fluorine concentration in a near-surface portion and a second fluorine concentration in an interior portion provides an insulator suitable for use in integrated circuits. In a further aspect of the present invention, fluorine is depleted from a near-surface portion of a fluorine containing dielectric material by a reducing plasma. Fluorine in fluorinated low-k dielectric materials, such as SiOF, amorphous fluorinated carbon (a-F:C) and parylene-AF4, can react with surrounding materials such as metals and Si3N4, causing blisters and delamination. Treatment of these fluorinated low-k dielectric materials in a reducing plasma, which may be produced from precursor gases such as H2 or NH3, depletes the surface region of fluorine and hence reduces reaction with surrounding materials and F outgassing. By selecting an appropriate point in the integration flow, specific interfaces which are most susceptible to F-attack can be targeted for depletion.

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