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1. 发明授权

US5412349A PLL clock generator integrated with microprocessor 失效
标题翻译： PLL时钟发生器与微处理器集成
公开(公告)号：US5412349A
公开(公告)日：1995-05-02
申请号：US861288
申请日：1992-03-31
申请人： Ian Young , Keng L. Wong , Jeffrey K. Greason
发明人： Ian Young , Keng L. Wong , Jeffrey K. Greason
IPC分类号： H03K3/0231 , H03L7/089 , H03L7/099 , H03B5/02
CPC分类号： H03L7/0995 , H03K3/0231 , H03L7/0891 , H03L2207/06
摘要： A PLL based deskewed clock generator which may be fully integrated on a microprocessor is disclosed. The clock generator has a skew of less than 0.1 ns with peak to peak jitter of 0.3 ns using a 0.8 .mu.m CMOS technology. The PLL comprises a phase frequency detector, charge pump, loop filter and voltage controlled oscillator from which the internal clock is generated. Since the PLL is on the same chip as the microprocessor, it is difficult to isolate the PLL from the noise generated by the microprocessor core logic and output buffers. Without an external filter, noise from the motherboard also influences the PLL. Power supply noise can cause a direct change in the frequency of the voltage controlled oscillator of the PLL. Circuits which overcome the adverse effects which would be created by such noises are also described.
摘要翻译：公开了一种可以完全集成在微处理器上的基于PLL的偏移时钟发生器。时钟发生器的偏移小于0.1 ns，峰值抖动为0.3 ns，采用0.8μmCMOS技术。 PLL包括相位频率检测器，电荷泵，环路滤波器和产生内部时钟的压控振荡器。由于PLL与微处理器在同一芯片上，所以难以将PLL与微处理器核心逻辑和输出缓冲器产生的噪声隔离开来。没有外部滤波器，主板噪声也会影响PLL。电源噪声可能导致PLL压控振荡器频率的直接变化。还描述了克服由这种噪声产生的不利影响的电路。

2. 发明授权

US5446867A Microprocessor PLL clock circuit with selectable delayed feedback 失效
标题翻译：具有可选延迟反馈的微处理器PLL时钟电路
公开(公告)号：US5446867A
公开(公告)日：1995-08-29
申请号：US890937
申请日：1992-05-29
申请人： Ian Young , Keng L. Wong , Jeffrey Smith
发明人： Ian Young , Keng L. Wong , Jeffrey Smith
IPC分类号： G06F1/10 , H03L7/081 , H03L7/089 , G06F1/00 , G06F1/04 , G06F1/06
CPC分类号： H03L7/081 , G06F1/10 , H03L7/0891
摘要： A circuit for use in high performance microprocessor systems which eliminates skew between a clock signal internal to the microprocessor core and inputs generated by a clock signal external to the microprocessor core. The circuit includes a phase locked loop (PLL), a delay line and a clock driver. The PLL locks and deskews the external clock edge to that of the internal clock to thereby provide an overall reduction of the setup and hold time window to satisfy the tight I/O timings required by high performance microprocessor systems. By incorporating the same PLL in all the closely coupled components of the microprocessor core, similar temperature and power supply tracking of such components is achieved. The PLL is a charge-pump based circuit of the type known in the art incorporating a phase detector, charge pump, loop filter and voltage controlled oscillator (VCO). However, the inclusion of the delay line in the feedback path of the PLL provides advantages not available from PLLs without such a delay line. A programmable tap is provided in the delay line which allows the I/O circuitry of the microprocessor to work with either CMOS or TTL input specifications. Specifically, compensation is provided for the differences in propagation delay between CMOS and TTL input buffers.
摘要翻译：用于高性能微处理器系统的电路，其消除了微处理器内核内部的时钟信号与由微处理器核心外部的时钟信号产生的输入之间的偏差。该电路包括锁相环（PLL），延迟线和时钟驱动器。 PLL锁定并将外部时钟边沿撇除为内部时钟的边沿，从而提供建立和保持时间窗口的全面减少，以满足高性能微处理器系统所需的紧密I / O时序。通过将相同的PLL结合在微处理器核心的所有紧密耦合的组件中，实现了类似的温度和电源跟踪这些组件。 PLL是本领域已知的类型的基于电荷泵的电路，其包括相位检测器，电荷泵，环路滤波器和压控振荡器（VCO）。然而，在PLL的反馈路径中包括延迟线提供了在没有这样的延迟线的情况下不能从PLL获得的优点。在延迟线上提供了一个可编程分接头，允许微处理器的I / O电路工作在CMOS或TTL输入规格。具体来说，为CMOS和TTL输入缓冲器之间的传播延迟的差异提供了补偿。

3. 发明授权

US5280605A Clock speed limiter for microprocessor 失效
标题翻译：微处理器时钟限速器
公开(公告)号：US5280605A
公开(公告)日：1994-01-18
申请号：US988345
申请日：1992-12-09
申请人： Ian Young , Keng L. Wong
发明人： Ian Young , Keng L. Wong
IPC分类号： G06F1/08 , G06F1/04
CPC分类号： G06F1/08
摘要： A speed governor for a microprocessor which prevents the operation above a selected frequency. Three resistors in a bridge network are switched capacitor "resistors" controlled by the input clocking signal. The value of the fourth resistor of the bridge is selected through connections to bonding pads. The bridge through a comparator disrupts the microprocessor's operation. The bondings also permit selection of an oscillator range and phase gap in the internal clocking signals.
摘要翻译：用于微处理器的调速器，其防止在所选频率之上的操作。桥接网络中的三个电阻是由输入时钟信号控制的开关电容器“电阻”。通过连接到焊盘来选择桥的第四个电阻的值。通过比较器的桥断开微处理器的操作。这些键也允许选择内部时钟信号中的振荡器范围和相位差。

4. 发明授权

US5274337A Clock speed limiter for a microprocessor by comparing clock signal with a predetermined frequency 失效
标题翻译：通过将时钟信号与预定频率进行比较，微处理器的时钟限速器
公开(公告)号：US5274337A
公开(公告)日：1993-12-28
申请号：US978182
申请日：1992-11-17
申请人： Ian Young , Keng L. Wong
发明人： Ian Young , Keng L. Wong
IPC分类号： G06F1/08 , H03K9/06 , H03D3/00
CPC分类号： G06F1/08
摘要： A speed governor for a microprocessor which prevents the operation above a selected frequency. Three resistors in a bridge network are switched capacitor "resistors" controlled by the input clocking signal. The value of the fourth resistor of the bridge is selected through connections to bonding pads. The bridge through a comparator disrupts the microprocessor's operation. The bondings also permit selection of an oscillator range and phase gap in the internal clocking signals.
摘要翻译：用于微处理器的调速器，其防止在所选频率之上的操作。桥接网络中的三个电阻是由输入时钟信号控制的开关电容器“电阻”。通过连接到焊盘来选择桥的第四个电阻的值。通过比较器的桥断开微处理器的操作。这些绑定还允许选择内部时钟信号中的振荡器范围和相位差。

5. 发明授权

US07404099B2 Phase-locked loop having dynamically adjustable up/down pulse widths 有权
标题翻译：锁相环具有动态可调节的上/下脉冲宽度
公开(公告)号：US07404099B2
公开(公告)日：2008-07-22
申请号：US10918301
申请日：2004-08-13
申请人： Mingwei Huang , Keng L. Wong , Raymond (Hon-Mo) Law , Chi-Yeu Chao
发明人： Mingwei Huang , Keng L. Wong , Raymond (Hon-Mo) Law , Chi-Yeu Chao
IPC分类号： G06F1/00 , G06F1/12 , G06F1/04
CPC分类号： H03L7/0891 , H03L7/10
摘要： According to embodiments of the present invention, a phase-locked loop (PLL) may include circuitry to select a wide pulse width for the phase-frequency detector control signal when the PLL is in a frequency acquisition stage, a narrow pulse width for the phase-frequency detector control signal when the PLL is in a phase capture stage, and a wide pulse width of the phase-frequency detector control signal when the PLL is in a lock stage.
摘要翻译：根据本发明的实施例，锁相环（PLL）可以包括当PLL处于频率采集级时为相位 - 频率检测器控制信号选择宽脉冲宽度的电路，用于相位的窄脉冲宽度当PLL处于锁相阶段时，PLL处于相位捕获级中的频率检测器控制信号，以及相位 - 频率检测器控制信号的宽脉冲宽度。

6. 发明授权

US07024324B2 Delay element calibration 失效
标题翻译：延迟元件校准
公开(公告)号：US07024324B2
公开(公告)日：2006-04-04
申请号：US10856907
申请日：2004-05-27
申请人： Michael C. Rifani , Keng L. Wong , Christopher Pan
发明人： Michael C. Rifani , Keng L. Wong , Christopher Pan
IPC分类号： G06F19/00
CPC分类号： G01R29/0273
摘要： A method for calibrating a delay element is described herein. In some embodiments, the method may include generating a clock signal with a clock edge, generating a reference signal with a reference edge using an adjustable delay line to delay the clock signal, and delaying a selected one of the clock signal and the reference signal through an array delay line having an array delay element with an array delay. In some embodiments, the method may further include adjusting the adjustable delay line to obtain a first adjustable delay so that the clock and reference edges are aligned on one side of the array delay element, adjusting the adjustable delay line to obtain a second adjustable delay so that the clock and reference edges are aligned on the other side of the array delay element, and ascertaining a delay difference between the first and the second adjustable delays to determine a value of the array delay provided by the array delay element. Other embodiments of the present invention may include, but are not limited to, apparatuses and systems adapted to facilitate practice of the above-described method.
摘要翻译：本文描述了用于校准延迟元件的方法。在一些实施例中，该方法可以包括用时钟沿生成时钟信号，使用可调延迟线产生具有参考边沿的参考信号以延迟时钟信号，以及延迟选定的一个时钟信号和参考信号通过具有阵列延迟的阵列延迟元件的阵列延迟线。在一些实施例中，该方法还可以包括调整可调延迟线以获得第一可调延迟，使得时钟和参考边沿在阵列延迟元件的一侧对准，调节可调延迟线以获得第二可调延迟时钟和参考边沿在阵列延迟元件的另一侧对准，并且确定第一和第二可调延迟之间的延迟差以确定由阵列延迟元件提供的阵列延迟的值。本发明的其它实施例可以包括但不限于适于促进实施上述方法的装置和系统。

7. 发明授权

US06985041B2 Clock generating circuit and method 失效
公开(公告)号：US06985041B2
公开(公告)日：2006-01-10
申请号：US10136390
申请日：2002-05-02
申请人： Keng L. Wong , Niraj Bindal , Hong-Piao Ma , George Geannopoulos , Greg F. Taylor , Edward A. Burton
发明人： Keng L. Wong , Niraj Bindal , Hong-Piao Ma , George Geannopoulos , Greg F. Taylor , Edward A. Burton
IPC分类号： H03B27/00
CPC分类号： G06F1/10 , H03K3/0315 , H03K5/133 , H03K5/15013
摘要： A clock generating circuit is provided that includes a multiplexing device coupled to a clock distribution network to select between a synchronous mode and an asynchronous mode. The device may also include a plurality of distributed ring oscillators to drive the clock distribution network in the asynchronous mode. In the synchronous mode, the multiplexing device may pass a signal from a phase lock loop circuit located external to a core.

8. 发明授权

US06531974B1 Controlling time delay 失效
标题翻译：控制时间延迟
公开(公告)号：US06531974B1
公开(公告)日：2003-03-11
申请号：US09545235
申请日：2000-04-07
申请人： Kent R. Callahan , Keng L. Wong
发明人： Kent R. Callahan , Keng L. Wong
IPC分类号： H03M166
CPC分类号： H03L7/0805 , H03K5/131 , H03K5/133 , H03K2005/00065 , H03K2005/00104 , H03K2005/00208 , H03L7/0995
摘要： Controlling time delay includes using a delay line and a digital to analog converter configured to provide a signal to the delay line and including digital inputs configured to control the delay through the delay line by controlling amplifier gain elements included in the digital to analog converter.
摘要翻译：控制时间延迟包括使用延迟线和数模转换器，其被配置为向延迟线提供信号，并且包括被配置为通过控制包括在数模转换器中的放大器增益元件来控制延迟线的延迟的数字输入。

9. 发明授权

US5801561A Power-on initializing circuit 失效
标题翻译：上电初始化电路
公开(公告)号：US5801561A
公开(公告)日：1998-09-01
申请号：US842501
申请日：1997-04-21
申请人： Keng L. Wong , Gregory F. Taylor , Roshan J. Fernando , Jeffrey E. Smith
发明人： Keng L. Wong , Gregory F. Taylor , Roshan J. Fernando , Jeffrey E. Smith
IPC分类号： H03K17/22
CPC分类号： H03K17/22
摘要： A method and apparatus for reducing contention in an integrated circuit during power-up. According to one aspect of the invention, an initialization circuit is included in an integrated circuit. In response to receiving Vcc, the initialization circuit generates a substitute clock signal and a substitute reset signal. The substitute clock signal and substitute reset signal are substituted for an off chip generated clock signal and an off chip generated reset signal during power-up until a predetermined condition is met. In response to receiving the substitute clock signal and the substitute reset signal, a plurality of circuits on said integrated circuit are initialized.
摘要翻译：一种减少上电期间集成电路竞争的方法和装置。根据本发明的一个方面，在集成电路中包括初始化电路。响应于接收到Vcc，初始化电路产生替代时钟信号和替代复位信号。替代时钟信号和替代复位信号在上电期间代替芯片内产生的时钟信号和芯片外产生的复位信号，直到满足预定条件。响应于接收到替代时钟信号和替代复位信号，初始化所述集成电路上的多个电路。

10. 发明授权

US5696953A Method and apparatus for power management of an integrated circuit 失效
标题翻译：集成电路的电源管理方法和装置
公开(公告)号：US5696953A
公开(公告)日：1997-12-09
申请号：US597363
申请日：1996-02-08
申请人： Keng L. Wong , Kelly J. Fitzpatrick , Jeffrey E. Smith
发明人： Keng L. Wong , Kelly J. Fitzpatrick , Jeffrey E. Smith
IPC分类号： G06F1/10 , G06F1/32 , H01L21/82 , H01L21/822 , H01L27/04 , H03K5/15
CPC分类号： G06F1/3237 , G06F1/10 , G06F1/3203 , G06F1/3287 , Y02B60/1221 , Y02B60/1282
摘要： A clock distribution system and clock interrupt system for an integrated circuit device. Ignoring effects associated with the matched stages, the present invention includes a clock distribution and interrupt system for providing clock signals with less than 100 picoseconds of skew to various components of an integrated circuit device. The present invention utilizes several stages of drivers to evenly supply the distributed clock signals and each stage has RC matched input lines. The present invention advantageously locates the matched stages and clock drivers within the power supply ring of the integrated circuit located on the periphery of the microprocessor topology. This is done in order to better predict the topology surrounding these lines to match the capacitance of these lines. Further, this metal level offers a larger width dimension line (since as a top layer it may be thicker) having less resistance per unit area and also generally avoids spatial competition with other IC components and circuitry. The present invention additionally offers the capability of selectively powering down various components within the integrated device with a power management unit and enable network that is included as a component of the clock distribution system.
摘要翻译：用于集成电路设备的时钟分配系统和时钟中断系统。忽略与匹配级相关的效应，本发明包括时钟分配和中断系统，用于向集成电路器件的各种部件提供小于100皮秒的偏移的时钟信号。本发明利用几级驱动器均匀地提供分布式时钟信号，每级具有RC匹配输入线。本发明有利地位于位于微处理器拓扑周边的集成电路的电源环内的匹配级和时钟驱动器。这样做是为了更好地预测这些线路周围的拓扑，以匹配这些线路的电容。此外，该金属层提供较大的宽度尺寸线（因为顶层可以较厚），每单位面积具有较小的电阻，并且还通常避免与其它IC组件和电路的空间竞争。本发明另外提供了利用功率管理单元选择性地降低集成设备内的各种组件并使能作为时钟分配系统的组件被包括的网络的能力。

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