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1. 发明授权

US06985041B2 Clock generating circuit and method 失效
公开(公告)号：US06985041B2
公开(公告)日：2006-01-10
申请号：US10136390
申请日：2002-05-02
申请人： Keng L. Wong , Niraj Bindal , Hong-Piao Ma , George Geannopoulos , Greg F. Taylor , Edward A. Burton
发明人： Keng L. Wong , Niraj Bindal , Hong-Piao Ma , George Geannopoulos , Greg F. Taylor , Edward A. Burton
IPC分类号： H03B27/00
CPC分类号： G06F1/10 , H03K3/0315 , H03K5/133 , H03K5/15013
摘要： A clock generating circuit is provided that includes a multiplexing device coupled to a clock distribution network to select between a synchronous mode and an asynchronous mode. The device may also include a plurality of distributed ring oscillators to drive the clock distribution network in the asynchronous mode. In the synchronous mode, the multiplexing device may pass a signal from a phase lock loop circuit located external to a core.

2. 发明授权

US06924710B2 Voltage ID based frequency control for clock generating circuit 有权
标题翻译：用于时钟发生电路的基于电压ID的频率控制
公开(公告)号：US06924710B2
公开(公告)日：2005-08-02
申请号：US10659637
申请日：2003-09-09
申请人： Keng L. Wong , Hong-Piao Ma , Greg F. Taylor , Chee How Lim , Robert Greiner , Edward A. Burton , Douglas R. Huard
发明人： Keng L. Wong , Hong-Piao Ma , Greg F. Taylor , Chee How Lim , Robert Greiner , Edward A. Burton , Douglas R. Huard
IPC分类号： G06F1/08 , G06F1/10 , H03L7/099 , H03L7/18 , H03L1/00
CPC分类号： G06F1/3203 , G06F1/08 , G06F1/10 , H03L7/0995 , H03L7/18 , Y02D10/126
摘要： An apparatus and method are provided for operating a processor core. This may include a first circuit to operate at a frequency that is dependent on a power supply voltage. A frequency control circuit may be provided to control a frequency of the first circuit by directing a voltage regulator to increase or decrease the power supply voltage.
摘要翻译：提供了一种用于操作处理器核心的装置和方法。这可以包括在取决于电源电压的频率下操作的第一电路。可以提供频率控制电路以通过引导电压调节器来增加或减少电源电压来控制第一电路的频率。

3. 发明授权

US06809606B2 Voltage ID based frequency control for clock generating circuit 有权
标题翻译：用于时钟发生电路的基于电压ID的频率控制
公开(公告)号：US06809606B2
公开(公告)日：2004-10-26
申请号：US10136321
申请日：2002-05-02
申请人： Keng L. Wong , Hong-Piao Ma , Greg F. Taylor , Chee How Lim , Robert Greiner , Edward A. Burton , Douglas R. Huard
发明人： Keng L. Wong , Hong-Piao Ma , Greg F. Taylor , Chee How Lim , Robert Greiner , Edward A. Burton , Douglas R. Huard
IPC分类号： H03L100
CPC分类号： G06F1/3203 , G06F1/08 , G06F1/10 , H03L7/0995 , H03L7/18 , Y02D10/126
摘要： An apparatus and method are provided for operating a processor core. This may include a first circuit to operate at a frequency that is dependent on a power supply voltage. A frequency control circuit may be provided to control a frequency of the first circuit by directing a voltage regulator to increase or decrease the power supply voltage.
摘要翻译：提供了一种用于操作处理器核心的装置和方法。这可以包括在取决于电源电压的频率下操作的第一电路。可以提供频率控制电路以通过引导电压调节器来增加或减少电源电压来控制第一电路的频率。

4. 发明授权

US06771134B2 Frequency control for clock generating circuit 有权
标题翻译：时钟发生电路的频率控制
公开(公告)号：US06771134B2
公开(公告)日：2004-08-03
申请号：US10136474
申请日：2002-05-02
申请人： Keng L. Wong , Hong-Piao Ma , Greg F. Taylor , Chee How Lim , Edward A. Burton
发明人： Keng L. Wong , Hong-Piao Ma , Greg F. Taylor , Chee How Lim , Edward A. Burton
IPC分类号： H03B2700
CPC分类号： H03L7/0995 , G06F1/08 , G06F1/10 , H03L7/18
摘要： A clock generating circuit is provided that includes a plurality of distributed ring oscillators to drive a clock distribution network. Multiplexing devices may select a length or delay of each of the ring oscillators. The variable length or delay may thereby adjust the frequency of the clock generating circuit.
摘要翻译：提供了一种时钟发生电路，其包括多个分布式环形振荡器以驱动时钟分配网络。多路复用器件可以选择每个环形振荡器的长度或延迟。因此，可变长度或延迟可以调节时钟发生电路的频率。

5. 发明授权

US07242261B2 Voltage control for clock generating circuit 有权
标题翻译：时钟发生电路的电压控制
公开(公告)号：US07242261B2
公开(公告)日：2007-07-10
申请号：US10680498
申请日：2003-10-06
申请人： Keng L. Wong , Hong-Piao Ma , Greg F. Taylor
发明人： Keng L. Wong , Hong-Piao Ma , Greg F. Taylor
IPC分类号： H03B1/00
CPC分类号： H03K5/15013 , G06F1/10 , G06F1/28 , H03K3/011 , H03K3/0315 , H03K5/133
摘要： An apparatus is provided that includes a clock distribution network, a plurality of distributed oscillators provided about the clock distribution network so as to provide clock signals on the clock distribution network and a power control circuit to control power applied to the plurality of distributed oscillators. The power control circuit includes a bandgap device to produce a reference voltage based on a desired power level and a comparing/decision device to receive the reference voltage from the bandgap device and to receive the voltage signal from a source external to the apparatus. The comparing/decision device determines whether the signal received from the power source corresponds to the desired power level.
摘要翻译：提供了一种装置，其包括时钟分配网络，围绕时钟分配网络设置的多个分布式振荡器，以便在时钟分配网络上提供时钟信号;以及功率控制电路，用于控制施加到多个分布式振荡器的功率。功率控制电路包括用于基于期望功率电平产生参考电压的带隙装置和用于从带隙装置接收参考电压并且从设备外部的源接收电压信号的比较/判定装置。比较/判定装置确定从电源接收的信号是否对应于期望的功率电平。

6. 发明授权

US06778033B2 Voltage control for clock generating circuit 有权
公开(公告)号：US06778033B2
公开(公告)日：2004-08-17
申请号：US10136318
申请日：2002-05-02
申请人： Keng L. Wong , Hong-Piao Ma , Greg F. Taylor
发明人： Keng L. Wong , Hong-Piao Ma , Greg F. Taylor
IPC分类号： H03B100
CPC分类号： H03K5/15013 , G06F1/10 , G06F1/28 , H03K3/011 , H03K3/0315 , H03K5/133
摘要： An apparatus is provided that includes a clock distribution network, a plurality of distributed oscillators provided about the clock distribution network so as to provide clock signals on the clock distribution network and a power control circuit to control power applied to the plurality of distributed oscillators. The power control circuit includes a bandgap device to produce a reference voltage based on a desired power level and a comparing/decision device to receive the reference voltage from the bandgap device and to receive the voltage signal from a source external to the apparatus. The comparing/decision device determines whether the signal received from the power source corresponds to the desired power level.

7. 发明授权

US6075832A Method and apparatus for deskewing clock signals 失效
标题翻译：用于校正时钟信号的方法和装置
公开(公告)号：US6075832A
公开(公告)日：2000-06-13
申请号：US946671
申请日：1997-10-07
申请人： George Geannopoulos , Keng L. Wong , Greg F. Taylor , Xia Dai
发明人： George Geannopoulos , Keng L. Wong , Greg F. Taylor , Xia Dai
IPC分类号： G06F1/10 , H03D3/24 , H03D13/00 , H03L7/00 , H03L7/081 , H03L7/087
CPC分类号： H03L7/087 , G06F1/10 , H03L7/0814
摘要： An apparatus for deskewing clock signals in a synchronous digital system. The apparatus contains a phase detection circuit that receives a plurality of clock signals and generates an output based on a phase relationship between those clock signals. A controller then receives the output of the phase detector and determines which one of the plurality of clock signals requires adjustment based on the output of the phase detector and a bit from a delay shift register. The controller transmits a delay signal to one of a plurality of delay circuits which modifies the delay of the clock signal that the controller determined to require adjustment.
摘要翻译：一种在同步数字系统中对时钟信号进行偏移校正的装置。该装置包含相位检测电路，其接收多个时钟信号，并根据这些时钟信号之间的相位关系产生输出。然后，控制器接收相位检测器的输出，并且基于相位检测器的输出和来自延迟移位寄存器的位确定多个时钟信号中的哪一个需要调整。控制器将延迟信号发送到多个延迟电路中的一个，其修改控制器确定需要调整的时钟信号的延迟。

8. 发明授权

US07157924B2 Method and apparatus for on-die voltage fluctuation detection 有权
标题翻译：用于片上电压波动检测的方法和装置
公开(公告)号：US07157924B2
公开(公告)日：2007-01-02
申请号：US10683189
申请日：2003-10-10
申请人： Ali Muhtaroglu , Kent Callahan , Tawfik Arabi , Greg F. Taylor
发明人： Ali Muhtaroglu , Kent Callahan , Tawfik Arabi , Greg F. Taylor
IPC分类号： G01R31/26
CPC分类号： G01R19/16552 , G01R19/16519 , G01R19/16566 , G01R31/275
摘要： An on-die device is provided to measure/detect voltage fluctuations. This may include a control unit to generate differential reference signals (such as differential current signals), a first detector unit and a second detector unit. The differential reference signals may be generated based on a Vcc reference signal and a Vss reference signal. The first detector unit may receive the differential reference signals from the control unit and may receive first voltage signals (also called monitored signals) from a first device under test (DUT) located on the die or from a first area on the die. The first detector unit may provide (or output) a first signal indicative of a voltage fluctuation (voltage droop or overshoot) of the first voltage signals. The second detector unit may receive the differential reference signals from the control unit and may receive second voltage signals (also called monitored signals) from a second device under test (DUT) located on the die. The second detector unit may provide (or output) a second signal indicative of a voltage fluctuation (or voltage droop) of the second voltage signals.
摘要翻译：提供了一种片上设备来测量/检测电压波动。这可以包括用于产生差分参考信号（例如差分电流信号）的控制单元，第一检测器单元和第二检测器单元。可以基于Vcc参考信号和Vss参考信号来生成差分参考信号。第一检测器单元可以从控制单元接收差分参考信号，并且可以从位于管芯上的第一被测器件（DUT）或从管芯上的第一区域接收第一电压信号（也称为监视信号）。第一检测器单元可以提供（或输出）指示第一电压信号的电压波动（电压下降或过冲）的第一信号。第二检测器单元可以从控制单元接收差分参考信号，并且可以从位于管芯上的被测试的第二被测器件（DUT）接收第二电压信号（也称为监视信号）。第二检测器单元可以提供（或输出）指示第二电压信号的电压波动（或电压下降）的第二信号。

9. 发明授权

US06747470B2 Method and apparatus for on-die voltage fluctuation detection 有权
公开(公告)号：US06747470B2
公开(公告)日：2004-06-08
申请号：US10021055
申请日：2001-12-19
申请人： Ali Muhtaroglu , Kent Callahan , Tawfik Arabi , Greg F. Taylor
发明人： Ali Muhtaroglu , Kent Callahan , Tawfik Arabi , Greg F. Taylor
IPC分类号： G01R3102
CPC分类号： G01R19/16552 , G01R19/16519 , G01R19/16566 , G01R31/275
摘要： An on-die device is provided to measure/detect voltage fluctuations. This may include a control unit to generate differential reference signals (such as differential current signals), a first detector unit and a second detector unit. The differential reference signals may be generated based on a Vcc reference signal and a Vss reference signal. The first detector unit may receive the differential reference signals from the control unit and may receive first voltage signals (also called monitored signals) from a first device under test (DUT) located on the die or from a first area on the die. The first detector unit may provide (or output) a first signal indicative of a voltage fluctuation (voltage droop or overshoot) of the first voltage signals. The second detector unit may receive the differential reference signals from the control unit and may receive second voltage signals (also called monitored signals) from a second device under test (DUT) located on the die. The second detector unit may provide (or output) a second signal indicative of a voltage fluctuation (or voltage droop) of the second voltage signals.

10. 发明授权

US06298105B1 Method and apparatus for a low skew, low standby power clock network 有权
标题翻译：低偏移，低待机功率时钟网络的方法和装置
公开(公告)号：US06298105B1
公开(公告)日：2001-10-02
申请号：US09183031
申请日：1998-10-30
申请人： Xia Dai , George Geannopuolos , John Orton , Keng Wong , Greg F. Taylor
发明人： Xia Dai , George Geannopuolos , John Orton , Keng Wong , Greg F. Taylor
IPC分类号： H04L100
CPC分类号： G06F1/3287 , G06F1/10 , G06F1/3203 , H03L7/0814 , H03L7/087 , Y02D10/171
摘要： An apparatus for a low skew, low standby power clock network for a synchronous digital system. The power clock network comprises a reference network, maintaining a reference clock signal, and four clock spines, each with its own respective clock signal. To reduce clock skew within the power clock network (i.e., to keep the clock signals of the clock spines synchronous with the reference clock signal), the present invention employs the use of active and passive delay elements to compensate for such skew. A phase relation extraction logic compares the phase of the clock signals from each respective clock spine to the reference clock signal of the reference network. If it is determined that the clock signals of the spines lag the reference clock signal, the phase relation extraction logic will use an active control driver to “speed-up” the clock signals of the clock spines. And, if the clock signals of the clock spines lead the reference clock signal, the phase relation extraction logic will use capacitive loadings to “slow down” such clock signals. Advantageously, the likelihood of the microprocessor achieving its maximum operating potential is greatly enhanced by the synchronization of such signals.
摘要翻译：一种用于同步数字系统的低偏移，低待机功率时钟网络的装置。功率时钟网络包括参考网络，维护参考时钟信号和四个时钟棘轮，每个具有其各自的时钟信号。为了减少功率时钟网络内的时钟偏移（即，使时钟的时钟信号与参考时钟信号保持同步），本发明采用有源和无源延迟元件来补偿这种偏移。相位关系提取逻辑将来自每个相应时钟脊的时钟信号的相位与参考网络的参考时钟信号进行比较。如果确定脊柱的时钟信号滞后于参考时钟信号，则相位关系提取逻辑将使用主动控制驱动器来“加速”时钟棘轮的时钟信号。而且，如果时钟的时钟信号引导参考时钟信号，则相位关系提取逻辑将使用电容负载来“减慢”这样的时钟信号。有利地，通过这种信号的同步，微处理器实现其最大工作电位的可能性大大提高。

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