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1. 发明授权

US5801561A Power-on initializing circuit 失效
标题翻译：上电初始化电路
公开(公告)号：US5801561A
公开(公告)日：1998-09-01
申请号：US842501
申请日：1997-04-21
申请人： Keng L. Wong , Gregory F. Taylor , Roshan J. Fernando , Jeffrey E. Smith
发明人： Keng L. Wong , Gregory F. Taylor , Roshan J. Fernando , Jeffrey E. Smith
IPC分类号： H03K17/22
CPC分类号： H03K17/22
摘要： A method and apparatus for reducing contention in an integrated circuit during power-up. According to one aspect of the invention, an initialization circuit is included in an integrated circuit. In response to receiving Vcc, the initialization circuit generates a substitute clock signal and a substitute reset signal. The substitute clock signal and substitute reset signal are substituted for an off chip generated clock signal and an off chip generated reset signal during power-up until a predetermined condition is met. In response to receiving the substitute clock signal and the substitute reset signal, a plurality of circuits on said integrated circuit are initialized.
摘要翻译：一种减少上电期间集成电路竞争的方法和装置。根据本发明的一个方面，在集成电路中包括初始化电路。响应于接收到Vcc，初始化电路产生替代时钟信号和替代复位信号。替代时钟信号和替代复位信号在上电期间代替芯片内产生的时钟信号和芯片外产生的复位信号，直到满足预定条件。响应于接收到替代时钟信号和替代复位信号，初始化所述集成电路上的多个电路。

2. 发明授权

US5557225A Pulsed flip-flop circuit 失效
标题翻译：脉冲触发器电路
公开(公告)号：US5557225A
公开(公告)日：1996-09-17
申请号：US367103
申请日：1994-12-30
申请人： Martin S. Denham , Keng L. Wong , Jeffrey E. Smith , Roshan J. Fernando
发明人： Martin S. Denham , Keng L. Wong , Jeffrey E. Smith , Roshan J. Fernando
IPC分类号： H03K3/037
CPC分类号： H03K3/037
摘要： A flip-flop circuit is described. The flip-flop circuit receives the data signal from a data input, receives a trigger signal from a trigger input, generates a pulse signal in response to an edge in the trigger signal, and stores the data signal in response to the pulse. Alternatively, the flip-flop circuit receives a data signal through a data input, receives a trigger signal through a trigger input, stores the data signal in a latch, and suppresses the trigger signal to the latch when the data signal stored in the latch corresponds to the data signal received through the data input.
摘要翻译：描述触发器电路。触发器电路从数据输入接收数据信号，从触发输入接收触发信号，响应于触发信号中的边缘产生脉冲信号，并响应脉冲存储数据信号。或者，触发器电路通过数据输入接收数据信号，通过触发输入接收触发信号，将数据信号存储在锁存器中，并且当存储在锁存器中的数据信号对应于锁存器时，将触发信号抑制到锁存器到通过数据输入接收的数据信号。

3. 发明授权

US6047383A Multiple internal phase-locked loops for synchronization of chipset components and subsystems operating at different frequencies 失效
标题翻译：用于同步芯片组件和不同频率工作的子系统的多个内部锁相环
公开(公告)号：US6047383A
公开(公告)日：2000-04-04
申请号：US12479
申请日：1998-01-23
申请人： Keith M. Self , Jeffrey E. Smith , Keng L. Wong
发明人： Keith M. Self , Jeffrey E. Smith , Keng L. Wong
IPC分类号： G06F1/12
CPC分类号： G06F1/12
摘要： Methods and apparatus for easing design constraints with respect to placement of computer system components and subsystems requiring relative synchronicity at different frequencies is described. In one embodiment the apparatus includes a first phase-locked loop (PLL) formed on an integrated circuit die. A reference clock signal pin is coupled to the first PLL by a path of electrical length L1 for propagating a reference clock signal to the first PLL. A first PLL feedback pin is coupled to the first PLL by a path of electrical length L2, wherein L1.apprxeq.L2. The apparatus includes a programmable counter coupled to the reference clock signal pin, the programmable counter providing a divided reference clock signal to the first PLL. In one embodiment, the method includes the step of providing a reference clock signal to a plurality of PLLs residing within a same integrated circuit. The outputs of at least some of the PLLs are coupled to corresponding output pins of the integrated circuit. The following steps are performed for each selected output pin coupled to provide a synchronized clock signal at the end of a propagation trace: a) determining an electrical length of the propagation trace; and b) providing a feedback trace from the output pin to a feedback pin of the corresponding PLL, wherein the feedback trace is a same electrical length as the propagation trace. A divided-by-n reference clock signal is then provided to at least one of the PLLs, wherein n is not equal to 1.
摘要翻译：描述了关于在不同频率下需要相对同步性的计算机系统组件和子系统的放置的宽松设计约束的方法和装置。在一个实施例中，该装置包括形成在集成电路管芯上的第一锁相环（PLL）。参考时钟信号引脚通过电长度L1的路径耦合到第一PLL，以将参考时钟信号传播到第一PLL。第一PLL反馈引脚通过电长度L2的路径耦合到第一PLL，其中L1 APPROX L2。该装置包括耦合到参考时钟信号引脚的可编程计数器，该可编程计数器向第一PLL提供划分的基准时钟信号。在一个实施例中，该方法包括向驻留在同一集成电路中的多个PLL提供参考时钟信号的步骤。至少一些PLL的输出耦合到集成电路的相应输出引脚。对于耦合以在传播轨迹结束时提供同步时钟信号的每个选择的输出引脚执行以下步骤：a）确定传播轨迹的电长度; 以及b）提供从所述输出引脚到相应PLL的反馈引脚的反馈迹线，其中所述反馈迹线与所述传播迹线具有相同的电长度。然后，将一个分频参考时钟信号提供给至少一个PLL，其中n不等于1。

4. 发明授权

US5586307A Method and apparatus supplying synchronous clock signals to circuit components 失效
标题翻译：向电路部件提供同步时钟信号的方法和装置
公开(公告)号：US5586307A
公开(公告)日：1996-12-17
申请号：US86044
申请日：1993-06-30
申请人： Keng L. Wong , Kelly J. Fitzpatrick , Jeffrey E. Smith
发明人： Keng L. Wong , Kelly J. Fitzpatrick , Jeffrey E. Smith
IPC分类号： G06F1/10 , G06F1/32 , H01L21/82 , H01L21/822 , H01L27/04 , H03K5/15 , G06F1/12
CPC分类号： G06F1/3237 , G06F1/10 , G06F1/3203 , G06F1/3287 , Y02B60/1221 , Y02B60/1282
摘要： A clock distribution system and clock interrupt system for an integrated circuit device. Ignoring effects associated with the matched stages, the present invention includes a clock distribution and interrupt system for providing clock signals with less than 100 picoseconds of skew to various components of an integrated circuit device. The present invention utilizes several stages of drivers to evenly supply the distributed clock signals and each stage has RC matched input lines. The present invention advantageously locates the matched stages and clock drivers within the power supply ring of the integrated circuit located on the periphery of the microprocessor topology. This is done in order to better predict the topology surrounding these lines to match the capacitance of these lines. Further, this metal level offers a larger width dimension line (since as a top layer it may be thicker) having less resistance per unit area and also generally avoids spatial competition with other IC components and circuitry. The present invention additionally offers the capability of selectively powering down various components within the integrated device with a power management unit and enable network that is included as a component of the clock distribution system.
摘要翻译：用于集成电路设备的时钟分配系统和时钟中断系统。忽略与匹配级相关的效应，本发明包括时钟分配和中断系统，用于向集成电路器件的各种部件提供小于100皮秒的偏移的时钟信号。本发明利用几级驱动器均匀地提供分布式时钟信号，每级具有RC匹配输入线。本发明有利地位于位于微处理器拓扑周边的集成电路的电源环内的匹配级和时钟驱动器。这样做是为了更好地预测这些线路周围的拓扑，以匹配这些线路的电容。此外，该金属层提供更大的宽度尺寸线（因为顶层可以更厚），每单位面积的电阻较小，并且还通常避免与其它IC组件和电路的空间竞争。本发明另外提供了利用功率管理单元选择性地降低集成设备内的各种组件并使能作为时钟分配系统的组件被包括的网络的能力。

5. 发明授权

US5696953A Method and apparatus for power management of an integrated circuit 失效
标题翻译：集成电路的电源管理方法和装置
公开(公告)号：US5696953A
公开(公告)日：1997-12-09
申请号：US597363
申请日：1996-02-08
申请人： Keng L. Wong , Kelly J. Fitzpatrick , Jeffrey E. Smith
发明人： Keng L. Wong , Kelly J. Fitzpatrick , Jeffrey E. Smith
IPC分类号： G06F1/10 , G06F1/32 , H01L21/82 , H01L21/822 , H01L27/04 , H03K5/15
CPC分类号： G06F1/3237 , G06F1/10 , G06F1/3203 , G06F1/3287 , Y02B60/1221 , Y02B60/1282
摘要： A clock distribution system and clock interrupt system for an integrated circuit device. Ignoring effects associated with the matched stages, the present invention includes a clock distribution and interrupt system for providing clock signals with less than 100 picoseconds of skew to various components of an integrated circuit device. The present invention utilizes several stages of drivers to evenly supply the distributed clock signals and each stage has RC matched input lines. The present invention advantageously locates the matched stages and clock drivers within the power supply ring of the integrated circuit located on the periphery of the microprocessor topology. This is done in order to better predict the topology surrounding these lines to match the capacitance of these lines. Further, this metal level offers a larger width dimension line (since as a top layer it may be thicker) having less resistance per unit area and also generally avoids spatial competition with other IC components and circuitry. The present invention additionally offers the capability of selectively powering down various components within the integrated device with a power management unit and enable network that is included as a component of the clock distribution system.
摘要翻译：用于集成电路设备的时钟分配系统和时钟中断系统。忽略与匹配级相关的效应，本发明包括时钟分配和中断系统，用于向集成电路器件的各种部件提供小于100皮秒的偏移的时钟信号。本发明利用几级驱动器均匀地提供分布式时钟信号，每级具有RC匹配输入线。本发明有利地位于位于微处理器拓扑周边的集成电路的电源环内的匹配级和时钟驱动器。这样做是为了更好地预测这些线路周围的拓扑，以匹配这些线路的电容。此外，该金属层提供较大的宽度尺寸线（因为顶层可以较厚），每单位面积具有较小的电阻，并且还通常避免与其它IC组件和电路的空间竞争。本发明另外提供了利用功率管理单元选择性地降低集成设备内的各种组件并使能作为时钟分配系统的组件被包括的网络的能力。

6. 发明授权

US5748033A Differential power bus comparator 失效
标题翻译：差分电源总线比较器
公开(公告)号：US5748033A
公开(公告)日：1998-05-05
申请号：US621652
申请日：1996-03-26
申请人： Golnaz Kaveh , Gregory F. Taylor , Jeffrey E. Smith
发明人： Golnaz Kaveh , Gregory F. Taylor , Jeffrey E. Smith
IPC分类号： G05F1/59 , G05F3/02
CPC分类号： G05F1/59
摘要： A method and an apparatus for generating an output voltage for an integrated circuit having multiple power supplies. A comparator circuit is coupled to receive power supply lines from the power bus of an integrated circuit. The power supply lines received from the power bus have different voltages which may vary depending on the particular application. The comparator compares the voltage potentials present on the power supply lines and determines which power supply line carries a voltage having the highest potential. The comparator then generates a corresponding select signal wherein the value of the select signal indicates which particular power supply line has the highest voltage potential. A multiplexor is coupled to receive the select signal as well as the power supply lines from the power bus. Based on the value of the select signal, the multiplexor generates the output voltage in response to the select signal wherein the output voltage is substantially equal to the voltage potential of the power supply line having the highest voltage potential.
摘要翻译：一种用于产生具有多个电源的集成电路的输出电压的方法和装置。比较器电路被耦合以从集成电路的电源总线接收电源线。从电源总线接收的电源线具有不同的电压，这些电压可以根据具体应用而变化。比较器比较电源线上存在的电压电位，并确定哪个电源线具有最高电位的电压。比较器然后产生相应的选择信号，其中选择信号的值指示哪个特定的电源线具有最高的电压电位。多路复用器被耦合以从电力总线接收选择信号以及电源线。基于选择信号的值，多路复用器响应于选择信号产生输出电压，其中输出电压基本上等于具有最高电压电位的电源线的电压电位。

7. 发明授权

US5539337A Clock noise filter for integrated circuits 失效
标题翻译：集成电路的时钟噪声滤波器
公开(公告)号：US5539337A
公开(公告)日：1996-07-23
申请号：US367842
申请日：1994-12-30
申请人： Gregory F. Taylor , Jeffrey E. Smith
发明人： Gregory F. Taylor , Jeffrey E. Smith
IPC分类号： H03K3/013 , H03K3/037 , H03K19/00
CPC分类号： H03K3/013 , H03K3/0375
摘要： A method and apparatus for providing a clock noise filter are described. The clock noise filter uses a transparent latch which has a trigger input and a data input. The data input is coupled to receive an input clock signal to be filtered. The output of the latch is the filtered clock signal. The filtered clock signal has a logic state which corresponds to the logic state of the input clock signal when the trigger input has a first predetermined logic state, and the filtered clock signal is inhibited from changing logic state when the trigger input has a second predetermined logic state. A trigger circuit is provided which has an input coupled to the output of the latch and an output coupled to the trigger input of the latch. The trigger circuit outputs the second predetermined logic state to the trigger input of the latch for a time interval in response to a change in logic state of the filtered clock signal and outputs the first predetermined logic state after the time interval has expired. The trigger circuit uses a delay stage to provide a delayed filtered clock signal to a logic gate. The logic gate receives the filtered clock signal and the delayed filtered clock signal and outputs the first and second predetermined logic states to the trigger input of the latch, depending upon the relative logic states of the filtered clock signal and the delayed filtered clock signal.
摘要翻译：描述了一种用于提供时钟噪声滤波器的方法和装置。时钟噪声滤波器使用具有触发输入和数据输入的透明锁存器。数据输入被耦合以接收要被滤波的输入时钟信号。锁存器的输出是经过滤波的时钟信号。当触发输入具有第一预定逻辑状态时，经滤波的时钟信号具有对应于输入时钟信号的逻辑状态的逻辑状态，并且当触发输入具有第二预定逻辑时，滤波时钟信号被禁止改变逻辑状态州。提供触发电路，其具有耦合到锁存器的输出的输入端和耦合到锁存器的触发输入的输出。响应于滤波后的时钟信号的逻辑状态的变化，触发电路将第二预定逻辑状态输出到锁存器的触发输入一段时间间隔，并在时间间隔到期后输出第一预定逻辑状态。触发电路使用延迟级将延迟的滤波时钟信号提供给逻辑门。逻辑门接收经过滤波的时钟信号和延迟滤波的时钟信号，并根据滤波的时钟信号和延迟滤波的时钟信号的相对逻辑状态将第一和第二预定逻辑状态输出到锁存器的触发输入。

8. 发明申请

US20130091379A1 SYSTEM AND METHOD FOR HIGH-SPEED DATA RECORDING 有权
标题翻译：用于高速数据记录的系统和方法
公开(公告)号：US20130091379A1
公开(公告)日：2013-04-11
申请号：US13625553
申请日：2012-09-24
申请人： Mikael B. Taveniku , Jeffrey E. Smith
发明人： Mikael B. Taveniku , Jeffrey E. Smith
IPC分类号： G06F11/14
CPC分类号： G06F11/1469 , G06F3/061 , G06F3/0656 , G06F3/0683 , G06F11/0727 , G06F11/1428 , G06F11/2094
摘要： A system and method for high speed data recording includes a control computer and a disk pack unit. The disk pack is provided within a shell that provides handling and protection for the disk packs. The disk pack unit provides cooling of the disks and connection for power and disk signaling. A standard connection is provided between the control computer and the disk pack unit. The disk pack units are self sufficient and able to connect to any computer. Multiple disk packs are connected simultaneously to the system, so that one disk pack can be active while one or more disk packs are inactive. To control for power surges, the power to each disk pack is controlled programmatically for the group of disks in a disk pack.
摘要翻译：用于高速数据记录的系统和方法包括控制计算机和盘组件。磁盘包提供在一个外壳内，为磁盘包提供处理和保护。磁盘组件提供磁盘的冷却和电源和磁盘信号的连接。在控制计算机和磁盘组件之间提供标准连接。磁盘包装单元是自给自足的，能够连接到任何计算机。多个磁盘包同时连接到系统，以便在一个或多个磁盘组处于非活动状态时，一个磁盘组可以处于活动状态。为了控制电涌，对于磁盘组中的一组磁盘，以编程方式控制每个磁盘组的电源。

9. 发明申请

US20090252134A1 METHODS AND SYSTEMS FOR A MOBILE, BROADBAND, ROUTABLE INTERNET 有权
标题翻译：移动，宽带，可变互联网的方法和系统
公开(公告)号：US20090252134A1
公开(公告)日：2009-10-08
申请号：US12418363
申请日：2009-04-03
申请人： Ludger Schlicht , Peter Atwal , Scott Y. Seidel , Gregory Clark Copeland , Victor M. T. Pataca , Rajesh K. Mishra , Jeffrey E. Smith
发明人： Ludger Schlicht , Peter Atwal , Scott Y. Seidel , Gregory Clark Copeland , Victor M. T. Pataca , Rajesh K. Mishra , Jeffrey E. Smith
IPC分类号： H04W4/00 , H04J3/00 , G06F15/16
CPC分类号： H04W40/08 , H04L1/0002 , H04L1/0003 , H04L1/0009 , H04L1/0015 , H04L45/123 , H04L45/308 , H04L2001/0097 , H04W16/18 , H04W40/20 , H04W84/18 , H04W84/22 , Y02D70/1222 , Y02D70/1224 , Y02D70/1262 , Y02D70/142 , Y02D70/146 , Y02D70/164 , Y02D70/22 , Y02D70/23 , Y02D70/324 , Y02D70/38
摘要： In embodiments of the present invention improved capabilities are described for a mobile broadband routable internet (MBRI) providing for carrier-grade, networked, broadband, IP-routable communication among a plurality of mobile devices, where the mobile devices may represent a plurality of nodes that are linked together through a mobile ad-hoc network (MANET). Mobile devices may operate as peers in a peer-to-peer network, with full IP routing capabilities enabled within each mobile device, thereby allowing routing of IP-based traffic, including deployment of applications, to the mobile device without need for infrastructure conventionally required for mobile ad hoc networks, such as cellular telephony infrastructure. Full IP-routing to mobile devices may allow seamless integration to the fixed Internet, such as through fixed or mobile access points, such as for backhaul purposes. Thus, the MBRI may function as a standalone mobile Internet, without connection to the fixed Internet, or as an IP-routable extension of another network, whether it be the Internet, a local area network, a wide area network, a cellular network, a personal area network, or some other type of network that is capable of integration with an IP-based network.
摘要翻译：在本发明的实施例中，针对移动宽带可路由互联网（MBRI）描述了改进的能力，该移动宽带可路由互联网（MBRI）提供多个移动设备之间的电信级，网络化，宽带，IP可路由通信，其中移动设备可以表示多个节点它们通过移动自组织网络（MANET）链接在一起。移动设备可以作为对等网络中的对等体运行，其中在每个移动设备内实现全IP路由功能，从而允许将基于IP的流量（包括部署应用）路由到移动设备，而不需要基础设施用于移动自组织网络，例如蜂窝电话基础设施。完全IP路由到移动设备可能允许无缝集成到固定Internet，例如通过固定或移动接入点，例如用于回程目的。因此，无论是互联网，局域网，广域网，蜂窝网络，MBRI还可以作为独立的移动因特网发挥作用，而不需要连接到固定的互联网，或作为另一网络的IP路由扩展。个人区域网络或能够与基于IP的网络集成的某种其他类型的网络。

10. 发明授权

US06178206B1 Method and apparatus for source synchronous data transfer 失效
标题翻译：源同步数据传输的方法和装置
公开(公告)号：US06178206B1
公开(公告)日：2001-01-23
申请号：US09013479
申请日：1998-01-26
申请人： Timothy W. Kelly , Stephen S. Pawlowski , Keith M. Self , Jeffrey E. Smith
发明人： Timothy W. Kelly , Stephen S. Pawlowski , Keith M. Self , Jeffrey E. Smith
IPC分类号： H04L2500
CPC分类号： H04L7/0331 , H04L7/0008
摘要： A method and apparatus is presented where for transmitting data between two or more components. Data signals are sent in parallel with a clocking signal (e.g., on a bus) so that the data signal can be latched in relation to the clocking signal. For example, two clocking signals, out of phase from each other by 180 degrees, can be sent on bidirectional clocking signal lines and data signals can be sent on a data signal line, the component receiving the clocking and data signals can latch the data signals on each high-to-low transition of either of the two clocking signals. Using the method and apparatus of the present invention, skew problems seen with other bus systems can be reduced which leads to an increase in data transfer rates.
摘要翻译：提出了一种用于在两个或更多个组件之间传输数据的方法和装置。数据信号与时钟信号（例如，总线）并行地发送，使得可以相对于时钟信号锁存数据信号。例如，可以在双向时钟信号线上发送彼此异相180度的两个时钟信号，并且数据信号可以在数据信号线上发送，接收时钟和数据信号的组件可以锁存数据信号在两个时钟信号中的任一个的每个从高到低的转换。使用本发明的方法和装置，可以减少其他总线系统所看到的偏斜问题，这导致数据传输速率的增加。

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