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1. 发明授权

US5489542A Method for fabricating semiconductor device in which threshold voltage shift and charge-pumping current are improved 失效
标题翻译：制造半导体器件的方法，其中阈值电压偏移和电荷泵浦电流得到改善
公开(公告)号：US5489542A
公开(公告)日：1996-02-06
申请号：US91921
申请日：1993-07-16
申请人： Hiroshi Iwai , Toyota Morimoto , Hisayo S. Momose , Kikuo Yamabe , Yoshio Ozawa
发明人： Hiroshi Iwai , Toyota Morimoto , Hisayo S. Momose , Kikuo Yamabe , Yoshio Ozawa
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8238 , H01L29/51 , H01L21/265 , H01L21/02 , H01L21/70 , H01L27/00
CPC分类号： H01L21/28185 , H01L21/28202 , H01L21/823857 , H01L29/513 , H01L29/518 , H01L29/66575 , H01L21/28211
摘要： A method for fabricating a semiconductor device on a silicon substrate, consists of producing a silicon oxide film on the silicon substrate producing a thin silicon nitride film on the silicon oxide film, thermally nitriding the silicon nitride film in an atmosphere of nitrogenous gas, producing a conductive film on the silicon nitride film nitrided in the atmosphere of the nitrogenous gas, producing a gate region from the silicon oxide film, the silicon nitride film, and the conductive film, a channel region being positioned under the gate region in the silicon substrate, producing a source region in the silicon substrate adjacent to one side of the channel region, producing a drain region in the silicon substrate adjacent to another side of the channel region, and producing wiring regions on the source region, the drain region, and the gate region.
摘要翻译：一种在硅衬底上制造半导体器件的方法，包括在硅衬底上产生氧化硅膜，在氧化硅膜上产生薄的氮化硅膜，在氮气气氛中氮化氮化硅膜，氮化硅膜上的导电膜在氮气气氛中氮化，从硅氧化膜，氮化硅膜和导电膜产生栅极区，沟道区位于硅衬底的栅极区下方，在所述硅衬底中邻近所述沟道区的一侧产生源极区，在所述硅衬底中与所述沟道区的另一侧相邻的漏极区产生，并且在所述源极区，所述漏极区和所述栅极上产生布线区地区。

2. 发明授权

US5237188A Semiconductor device with nitrided gate insulating film 失效
标题翻译：具有氮化栅极绝缘膜的半导体器件
公开(公告)号：US5237188A
公开(公告)日：1993-08-17
申请号：US798098
申请日：1991-11-27
申请人： Hiroshi Iwai , Toyota Morimoto , Hisayo S. Momose , Kikuo Yamabe , Yoshio Ozawa
发明人： Hiroshi Iwai , Toyota Morimoto , Hisayo S. Momose , Kikuo Yamabe , Yoshio Ozawa
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8238 , H01L29/51
CPC分类号： H01L21/28185 , H01L21/28202 , H01L21/823857 , H01L29/513 , H01L29/518 , H01L29/66575 , H01L21/28211
摘要： A semiconductor device formed on a silicon substrate consisting of the steps of producing a silicon oxide film on the silicon substrate, producing a thin silicon nitride film on the silicon oxide film, thermally nitriding the silicon nitride film in an atmosphere of nitrogenous gas, producing a conductive film on the silicon nitride film nitrided in the atmosphere of the nitrogenous gas, producing a gate region from the silicon oxide film, the silicon nitride film, and the conductive film, a channel region being positioned under the gate region in the silicon substrate, producing a source region in the silicon substrate adjacent to one side of the channel region, producing a drain region in the silicon substrate adjacent to another side of the channel region, and producing wiring regions on the source region, the drain region, and the gate region.
摘要翻译：一种形成在硅衬底上的半导体器件，包括在硅衬底上制造氧化硅膜的步骤，在氧化硅膜上产生薄氮化硅膜，在氮气气氛中对氮化硅膜进行氮化，产生氮化硅膜上的导电膜在氮气气氛中氮化，从硅氧化膜，氮化硅膜和导电膜产生栅极区，沟道区位于硅衬底的栅极区下方，在所述硅衬底中邻近所述沟道区的一侧产生源极区，在所述硅衬底中与所述沟道区的另一侧相邻的漏极区产生，并且在所述源极区，所述漏极区和所述栅极上产生布线区地区。

3. 发明授权

US5543334A Method of screening semiconductor device 失效
标题翻译：半导体器件的筛选方法
公开(公告)号：US5543334A
公开(公告)日：1996-08-06
申请号：US356419
申请日：1994-12-15
申请人： Ichiro Yoshii , Hiroyuki Kamijoh , Yoshio Ozawa , Kikuo Yamabe , Kazuhiko Hashimoto , Katsuya Okumura , Kaoru Hama
发明人： Ichiro Yoshii , Hiroyuki Kamijoh , Yoshio Ozawa , Kikuo Yamabe , Kazuhiko Hashimoto , Katsuya Okumura , Kaoru Hama
IPC分类号： H01L21/66
CPC分类号： H01L22/14 , H01L2924/0002
摘要： A method of screening a semiconductor device. A silicon wafer having gate electrodes formed on the gate oxide film is prepared. An insulating layer is deposited on the silicon wafer. Gate electrode portions of a group of transistors to be tested are exposed. A conductive layer is deposited on the silicon wafer having exposed gate electrodes. The conductive layer is patterned to be a wiring layer so that the gate electrodes of a group of the transistors can be electrically connected to each other. The chip area to be tested is irradiated with light having intensity enough to generate a required quantity of carriers in a depletion layer between a well and a substrate. A predetermined test voltage is applied between the wiring layer and the substrate of the silicon wafer during irradiation of the light to measure current flowing through the wiring layer and the gate oxide film. An abnormality of the gate oxide film can be detected on the basis of the measured current value. The screening method may be conducted before the completion of forming the gate electrodes. Further, gate electrode portions not to be used by a user may not be electrically connected to the gate electrode portions to be used.
摘要翻译：一种半导体器件的屏蔽方法。制备在栅氧化膜上形成栅电极的硅晶片。绝缘层沉积在硅晶片上。待测试的一组晶体管的栅电极部分露出。在具有暴露的栅电极的硅晶片上沉积导电层。导电层被图案化为布线层，使得一组晶体管的栅电极可以彼此电连接。用足够强度的光照射要测试的芯片面积，以在阱和衬底之间的耗尽层中产生所需量的载流子。在光照射期间，在布线层和硅晶片的基板之间施加预定的测试电压，以测量流过布线层和栅氧化膜的电流。可以基于测量的电流值来检测栅氧化膜的异常。筛选方法可以在形成栅电极的完成之前进行。此外，用户不使用的栅电极部分可以不与要使用的栅电极部分电连接。

4. 发明授权

US08637915B2 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US08637915B2
公开(公告)日：2014-01-28
申请号：US13007258
申请日：2011-01-14
申请人： Masayuki Ichige , Fumitaka Arai , Riichiro Shirota , Toshitake Yaegashi , Yoshio Ozawa , Akihito Yamamoto , Ichiro Mizushima , Yoshihiko Saito
发明人： Masayuki Ichige , Fumitaka Arai , Riichiro Shirota , Toshitake Yaegashi , Yoshio Ozawa , Akihito Yamamoto , Ichiro Mizushima , Yoshihiko Saito
IPC分类号： H01L29/788
CPC分类号： H01L29/42336 , H01L21/28273 , H01L27/0207 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/42324 , H01L29/7881
摘要： A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells.
摘要翻译：非易失性半导体存储器包括具有浮动栅极和控制栅极的第一和第二存储单元。第一和第二存储单元的浮动栅极包括第一部分和布置在第一部分上的第二部分，并且第二部分在控制栅极的延伸方向上的宽度比第一部分的宽度窄。第一和第二存储单元的第一部分之间的第一空间填充有一种绝缘体。控制栅极被布置在第一和第二存储单元的第二部分之间的第二空间处。

5. 再颁专利

USRE44630E1 Semiconductor device and method for manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：USRE44630E1
公开(公告)日：2013-12-10
申请号：US13616208
申请日：2012-09-14
申请人： Tetsuya Kai , Ryuji Ohba , Yoshio Ozawa
发明人： Tetsuya Kai , Ryuji Ohba , Yoshio Ozawa
IPC分类号： H01L21/331
CPC分类号： H01L21/28273 , B82Y10/00 , H01L21/28282 , H01L27/11521 , H01L29/42332 , H01L29/7881
摘要： A semiconductor device includes a semiconductor substrate, and a nonvolatile memory cell provided on the semiconductor substrate, the nonvolatile memory cell including a tunnel insulating film provided on a surface of the semiconductor substrate, the tunnel insulating film including semiconductor grains, the semiconductor grains included in both end portions of the tunnel insulating film having smaller grain size than the semiconductor grains included in other portions of the tunnel insulating film, a charge storage layer provided on the tunnel insulating film, an insulating film provided on the charge storage layer, and a control gate electrode provided on the insulating film.
摘要翻译：半导体器件包括半导体衬底和设置在半导体衬底上的非易失性存储单元，所述非易失性存储单元包括设置在所述半导体衬底的表面上的隧道绝缘膜，所述隧道绝缘膜包括半导体晶粒，所述半导体晶粒包括在隧道绝缘膜的两端部比隧道绝缘膜的其他部分所包含的半导体晶粒小的晶粒尺寸，隧道绝缘膜上设置的电荷存储层，设置在电荷存储层上的绝缘膜，以及控制栅电极设置在绝缘膜上。

6. 发明授权

US08604536B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08604536B2
公开(公告)日：2013-12-10
申请号：US12406841
申请日：2009-03-18
申请人： Katsuyuki Sekine , Yoshio Ozawa
发明人： Katsuyuki Sekine , Yoshio Ozawa
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L21/28282 , H01L29/513 , H01L29/66833
摘要： A semiconductor device includes a memory cell transistor including a first lower insulating film provided on a semiconductor substrate, a first intermediate insulating film provided on the first lower insulating film, a first upper insulating film provided on the first intermediate insulating film, and a first gate electrode provided on the first upper insulating film, and a select transistor including a second lower insulating film provided on the semiconductor substrate, a second intermediate insulating film provided on the second lower insulating film, a second upper insulating film provided on the second intermediate insulating film, and a second gate electrode provided on the second upper insulating film, wherein trap density of the second intermediate insulating film is lower than that of the first intermediate insulating film.
摘要翻译：半导体器件包括存储单元晶体管，其包括设置在半导体衬底上的第一下绝缘膜，设置在第一下绝缘膜上的第一中间绝缘膜，设置在第一中间绝缘膜上的第一上绝缘膜和第一栅极设置在第一上绝缘膜上的电极和设置在半导体衬底上的第二下绝缘膜的选择晶体管，设置在第二下绝缘膜上的第二中间绝缘膜，设置在第二中间绝缘膜上的第二上绝缘膜以及设置在第二上绝缘膜上的第二栅电极，其中第二中间绝缘膜的阱密度低于第一中间绝缘膜的陷阱密度。

7. 发明授权

US08324679B2 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US08324679B2
公开(公告)日：2012-12-04
申请号：US13430153
申请日：2012-03-26
申请人： Masayuki Ichige , Fumitaka Arai , Riichiro Shirota , Toshitake Yaegashi , Yoshio Ozawa , Akihito Yamamoto , Ichiro Mizushima , Yoshihiko Saito
发明人： Masayuki Ichige , Fumitaka Arai , Riichiro Shirota , Toshitake Yaegashi , Yoshio Ozawa , Akihito Yamamoto , Ichiro Mizushima , Yoshihiko Saito
IPC分类号： H01L29/788
CPC分类号： H01L29/42336 , H01L21/28273 , H01L27/0207 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/42324 , H01L29/7881
摘要： A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells.
摘要翻译：非易失性半导体存储器包括具有浮动栅极和控制栅极的第一和第二存储单元。第一和第二存储单元的浮动栅极包括第一部分和布置在第一部分上的第二部分，并且第二部分在控制栅极的延伸方向上的宽度比第一部分的宽度窄。第一和第二存储单元的第一部分之间的第一空间填充有一种绝缘体。控制栅极被布置在第一和第二存储单元的第二部分之间的第二空间处。

8. 发明申请

US20120282773A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20120282773A1
公开(公告)日：2012-11-08
申请号：US13487280
申请日：2012-06-04
申请人： Isao Kamioka , Junichi Shiozawa , Ryu Kato , Yoshio Ozawa
发明人： Isao Kamioka , Junichi Shiozawa , Ryu Kato , Yoshio Ozawa
IPC分类号： H01L21/302
CPC分类号： H01L29/7881 , H01L21/76208 , H01L27/11521 , H01L29/66825
摘要： In one embodiment, a method of manufacturing a semiconductor device includes forming a conductive film whose upper surface and side surface are exposed and an insulation film whose upper surface is exposed, on a semiconductor substrate. The method further includes supplying oxidizing ions or nitriding ions contained in plasma generated by a microwave, a radio-frequency wave, or electron cyclotron resonance to the exposed side surface of the conductive film and the exposed upper surface of the insulation film, by applying a predetermined voltage to the semiconductor substrate, thereby performing anisotropic oxidation or anisotropic nitridation of the exposed side surface of the conductive film and the exposed upper surface of the insulation film.
摘要翻译：在一个实施例中，制造半导体器件的方法包括在半导体衬底上形成其上表面和侧表面被暴露的导电膜和上表面暴露的绝缘膜。该方法还包括通过施加微波，射频波或电子回旋共振等将由等离子体产生的等离子体中包含的氧化离子或氮化离子供应到导电膜的暴露侧表面和绝缘膜的暴露的上表面对半导体衬底施加预定的电压，从而进行导电膜的暴露的侧表面和绝缘膜的暴露的上表面的各向异性氧化或各向异性氮化。

9. 发明授权

US08304352B2 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08304352B2
公开(公告)日：2012-11-06
申请号：US13051031
申请日：2011-03-18
申请人： Masayuki Tanaka , Kazuhiro Matsuo , Yoshio Ozawa
发明人： Masayuki Tanaka , Kazuhiro Matsuo , Yoshio Ozawa
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/28282 , H01L27/11568 , H01L27/11582
摘要： According to an embodiment, there is provided a method of manufacturing a semiconductor device, including forming a nitride film by nitriding a surface of an underlying region having a semiconductor region containing silicon as a main component and an insulating region containing silicon and oxygen as a main component and adjacent to the semiconductor region, carrying out oxidation with respect to the nitride film to convert a portion of the nitride film which is formed on the insulating region into an oxide film and to leave a portion of the nitride film which is formed on the semiconductor region as at least part of a charge storage insulating film, forming a block insulating film on the charge storage insulating film, and forming a gate electrode film on the block insulating film.
摘要翻译：根据一个实施例，提供一种制造半导体器件的方法，包括通过氮化作为主要成分的含有硅的半导体区域的下面的区域的表面和以硅和氧为主要的绝缘区域来形成氮化物膜并且与半导体区域相邻，相对于氮化物膜进行氧化，将形成在绝缘区域上的氮化物膜的一部分转换为氧化膜，并且使形成在该半导体层上的氮化膜的一部分半导体区域作为电荷存储绝缘膜的至少一部分，在电荷存储绝缘膜上形成块绝缘膜，并在块绝缘膜上形成栅极电极膜。

10. 发明授权

US08198159B2 Semiconductor memory device and method of manufacturing the same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US08198159B2
公开(公告)日：2012-06-12
申请号：US12054089
申请日：2008-03-24
申请人： Masayuki Tanaka , Yoshio Ozawa , Hirokazu Ishida , Katsuaki Natori , Seiji Inumiya
发明人： Masayuki Tanaka , Yoshio Ozawa , Hirokazu Ishida , Katsuaki Natori , Seiji Inumiya
IPC分类号： H01L21/324 , H01L29/788
CPC分类号： H01L29/7881 , G11C16/0483 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/42324 , H01L29/513
摘要： A semiconductor memory device includes a semiconductor substrate, an isolation insulation film filled in a plurality of trenches formed in the semiconductor substrate to define a plurality of element formation regions, a floating gate of polysilicon provided on each of the element formation regions through a first insulation film, a second insulation film, provided on the floating gate, containing a metal element, a control gate of polysilicon, provided on the second insulation film, and source/drain regions provided in the semiconductor substrate, both a polysilicon conductive layer containing a metal element and a mutual diffusion layer composed of a silicate layer of a mixed oxide material composed of a silicon element contained in the floating gate and the control gate and a metal element contained in the second insulation film are provided on a surface of each of the floating gate and the control gate, respectively.
摘要翻译：半导体存储器件包括半导体衬底，隔离绝缘膜，填充在形成于半导体衬底中的多个沟槽中，以限定多个元件形成区域;多晶硅浮置栅极，通过第一绝缘层设置在每个元件形成区域上; 设置在浮置栅极上的第二绝缘膜，包含设置在第二绝缘膜上的金属元件，多晶硅控制栅极和设置在半导体衬底中的源极/漏极区域，包含金属的多晶硅导电层元件和由浮置栅极中包含的硅元素和控制栅极组成的混合氧化物材料的硅酸盐层和包含在第二绝缘膜中的金属元素构成的互扩散层设置在每个浮动栅极的表面上门和控制门。

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