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1. 发明授权

US5543334A Method of screening semiconductor device 失效
标题翻译：半导体器件的筛选方法
公开(公告)号：US5543334A
公开(公告)日：1996-08-06
申请号：US356419
申请日：1994-12-15
申请人： Ichiro Yoshii , Hiroyuki Kamijoh , Yoshio Ozawa , Kikuo Yamabe , Kazuhiko Hashimoto , Katsuya Okumura , Kaoru Hama
发明人： Ichiro Yoshii , Hiroyuki Kamijoh , Yoshio Ozawa , Kikuo Yamabe , Kazuhiko Hashimoto , Katsuya Okumura , Kaoru Hama
IPC分类号： H01L21/66
CPC分类号： H01L22/14 , H01L2924/0002
摘要： A method of screening a semiconductor device. A silicon wafer having gate electrodes formed on the gate oxide film is prepared. An insulating layer is deposited on the silicon wafer. Gate electrode portions of a group of transistors to be tested are exposed. A conductive layer is deposited on the silicon wafer having exposed gate electrodes. The conductive layer is patterned to be a wiring layer so that the gate electrodes of a group of the transistors can be electrically connected to each other. The chip area to be tested is irradiated with light having intensity enough to generate a required quantity of carriers in a depletion layer between a well and a substrate. A predetermined test voltage is applied between the wiring layer and the substrate of the silicon wafer during irradiation of the light to measure current flowing through the wiring layer and the gate oxide film. An abnormality of the gate oxide film can be detected on the basis of the measured current value. The screening method may be conducted before the completion of forming the gate electrodes. Further, gate electrode portions not to be used by a user may not be electrically connected to the gate electrode portions to be used.
摘要翻译：一种半导体器件的屏蔽方法。制备在栅氧化膜上形成栅电极的硅晶片。绝缘层沉积在硅晶片上。待测试的一组晶体管的栅电极部分露出。在具有暴露的栅电极的硅晶片上沉积导电层。导电层被图案化为布线层，使得一组晶体管的栅电极可以彼此电连接。用足够强度的光照射要测试的芯片面积，以在阱和衬底之间的耗尽层中产生所需量的载流子。在光照射期间，在布线层和硅晶片的基板之间施加预定的测试电压，以测量流过布线层和栅氧化膜的电流。可以基于测量的电流值来检测栅氧化膜的异常。筛选方法可以在形成栅电极的完成之前进行。此外，用户不使用的栅电极部分可以不与要使用的栅电极部分电连接。

2. 发明授权

US5297956A Method and apparatus for heat treating 失效
标题翻译：热处理方法和装置
公开(公告)号：US5297956A
公开(公告)日：1994-03-29
申请号：US799931
申请日：1991-11-29
申请人： Kikuo Yamabe , Keitaro Imai , Katsuya Okumura , Ken Nakao , Seikou Ueno
发明人： Kikuo Yamabe , Keitaro Imai , Katsuya Okumura , Ken Nakao , Seikou Ueno
IPC分类号： H01L21/324 , C30B31/12 , C30B31/14 , H01L21/22 , H01L21/31 , H01L21/673 , H01L21/683 , F23D5/00
CPC分类号： C30B31/12 , C30B31/14
摘要： A method and an apparatus for heat treating in a heat treating apparatus having a heating chamber to be introduced with predetermined gas, a heater disposed around the heating chamber, and jigs disposed in the heating chamber for supporting wafers of a plurality of substrates to be treated in parallel with each other, wherein in order to make the temperature distribution of the wafers of the substrates to be treated in the radial direction uniform in the heat treatment, the jigs are formed to determine the sizes and the shape thereof in predetermined ranges having a gradient according to the heat treating method having a predetermined shape determining procedure so that the jigs are formed in ring-shaped trays (i.e. support-ring) for holding at the peripheries the substrates to be treated and the thickness of the tray is constant or such that the outer peripheral side thereof is thicker than the inner peripheral side thereof.
摘要翻译：一种热处理装置中的热处理方法和装置，其特征在于，具有要加入预定气体的加热室，设置在所述加热室周围的加热器和设置在所述加热室中的夹具，用于支撑待处理的多个基板的晶片彼此并联，其中为了使热处理中要处理的基板的晶片的温度分布均匀，形成夹具以确定其尺寸和形状，其具有在根据具有预定形状确定步骤的热处理方法的梯度，使得夹具形成为环状托盘（即，支撑环），用于在周边保持要处理的基板，并且托盘的厚度等于或等于其外周侧比其内周侧厚。

3. 发明授权

US5354710A Method of manufacturing semiconductor devices using an adsorption enhancement layer 失效
标题翻译：使用吸附增强层制造半导体器件的方法
公开(公告)号：US5354710A
公开(公告)日：1994-10-11
申请号：US17449
申请日：1993-02-12
申请人： Hideichi Kawaguchi , Yoshitaka Tsunashima , Kikuo Yamabe , Katsuya Okumura
发明人： Hideichi Kawaguchi , Yoshitaka Tsunashima , Kikuo Yamabe , Katsuya Okumura
IPC分类号： H01L21/225 , H01L21/334 , H01L21/8242 , H01L21/00 , H01L21/02 , H01L21/385
CPC分类号： H01L27/10861 , H01L21/2256 , H01L29/66181 , Y10S438/923
摘要： A method of manufacturing semiconductor devices comprises the steps of preparing a semiconductor substrate having a surface and a natural oxide film on the surface, forming an adsorption enhancement layer on the surface of the semiconductor substrate, forming an impurity adsorption layer containing impurities on the adsorption enhancement layer, and thermally diffusing the impurities through the adsorption enhancement layer and the natural oxide film into the substrate.
摘要翻译：一种制造半导体器件的方法包括以下步骤：在表面上制备具有表面和自然氧化膜的半导体衬底，在半导体衬底的表面上形成吸附增强层，在吸附增强层上形成含有杂质的杂质吸附层并且通过吸附增强层和天然氧化物膜将杂质热扩散到基底中。

4. 发明授权

US5431561A Method and apparatus for heat treating 失效
标题翻译：热处理方法和装置
公开(公告)号：US5431561A
公开(公告)日：1995-07-11
申请号：US166014
申请日：1993-12-14
申请人： Kikuo Yamabe , Keitaro Imai , Katsuya Okumura , Ken Nakao , Seikou Ueno
发明人： Kikuo Yamabe , Keitaro Imai , Katsuya Okumura , Ken Nakao , Seikou Ueno
IPC分类号： H01L21/324 , C30B31/12 , C30B31/14 , H01L21/22 , H01L21/31 , H01L21/673 , H01L21/683 , F27D5/00
CPC分类号： C30B31/12 , C30B31/14
摘要： A method and an apparatus for heat treating in a heat treating apparatus having a heating chamber to be introduced with predetermined gas, a heater disposed around the heating chamber, and jigs disposed in the heating chamber for supporting wafers of a plurality of substrates to be treated in parallel with each other, wherein in order to make the temperature distribution of the wafers of the substrates to be treated in the radial direction uniform in the heat treatment, the jigs are formed to determine the sizes and the shape thereof in predetermined ranges having a gradient according to the heat treating method having a predetermined shape determining procedure so that the jigs are formed in ring-shaped trays (i.e. support-ring) for holding at the peripheries the substrates to be treated and the thickness of the tray is constant or such that the outer peripheral side thereof is thicker than the inner peripheral side thereof.
摘要翻译：一种热处理装置中的热处理方法和装置，其特征在于，具有要加入预定气体的加热室，设置在所述加热室周围的加热器和设置在所述加热室中的夹具，用于支撑待处理的多个基板的晶片彼此并联，其中为了使热处理中要处理的基板的晶片的温度分布均匀，形成夹具以确定其尺寸和形状，其具有在根据具有预定形状确定步骤的热处理方法的梯度，使得夹具形成为环状托盘（即，支撑环），用于在周边保持要处理的基板，并且托盘的厚度等于或等于其外周侧比其内周侧厚。

5. 发明授权

US5259883A Method of thermally processing semiconductor wafers and an apparatus therefor 失效
标题翻译：半导体晶片的热处理方法及其装置
公开(公告)号：US5259883A
公开(公告)日：1993-11-09
申请号：US27575
申请日：1993-03-05
申请人： Kikuo Yamabe , Katsuya Okumura
发明人： Kikuo Yamabe , Katsuya Okumura
IPC分类号： C23C16/46 , C30B33/00 , F27D15/02 , H01L21/00 , C23C16/00
CPC分类号： H01L21/67115 , C23C16/46 , C30B33/00 , F27D15/02
摘要： An apparatus for thermally processing semiconductor wafers within a reaction tube in which the wafers are thermally processed in a higher temperature region within the reaction tube. The thermally processed semiconductor waters are moved into a lower temperature region within the reaction tube. The rate of heat radiated from the thermally processed semiconductor waters is reduced in the lower temperature region within the reaction tube.
摘要翻译：一种用于在反应管内热处理半导体晶片的装置，其中晶片在反应管内的较高温度区域被热处理。热处理的半导体水被移动到反应管内的较低温度区域。在热处理的半导体水中辐射的热量在反应管内的较低温度区域内降低。

6. 发明授权

US09034467B2 Reticle chuck cleaner 有权
标题翻译：标线卡盘清洁剂
公开(公告)号：US09034467B2
公开(公告)日：2015-05-19
申请号：US13192694
申请日：2011-07-28
申请人： Masamitsu Itoh , Katsuya Okumura , Taro Inada , Jun Watanabe
发明人： Masamitsu Itoh , Katsuya Okumura , Taro Inada , Jun Watanabe
IPC分类号： B32B7/12 , B08B7/00 , G03F7/20
CPC分类号： B08B7/0028 , B05D3/0254 , B05D5/00 , G03F7/707 , G03F7/70925 , Y10T428/28 , Y10T428/2848
摘要： According to one embodiment, a reticle chuck cleaner for cleaning a reticle chuck of an EUV exposure apparatus includes a substrate having a shape to be carried to the reticle chuck of the EUV exposure apparatus, and an adhesive formed on one of the main surfaces of the substrate.
摘要翻译：根据一个实施例，用于清洁EUV曝光装置的光罩卡盘的掩模版卡盘清洁器包括具有要携带到EUV曝光装置的掩模版卡盘的形状的基板，以及形成在其中一个主表面上的粘合剂基质。

7. 发明申请

US20130313429A1 METHOD AND APPARATUS FOR INSPECTING SAMPLE SURFACE 有权
公开(公告)号：US20130313429A1
公开(公告)日：2013-11-28
申请号：US13954425
申请日：2013-07-30
申请人： Nobuharu Noji , Yoshihiko Naito , Hirosi Sobukawa , Kenji Terao , Masahiro Hatakeyama , Katsuya Okumura
发明人： Nobuharu Noji , Yoshihiko Naito , Hirosi Sobukawa , Kenji Terao , Masahiro Hatakeyama , Katsuya Okumura
IPC分类号： H01J37/26
CPC分类号： H01J37/265 , G01R31/307 , H01J37/04 , H01J2237/2441 , H01J2237/2446 , H01J2237/2594 , H01J2237/2817
摘要： Provided is a method and an apparatus for inspecting a sample surface with high accuracy. Provided is a method for inspecting a sample surface by using an electron beam method sample surface inspection apparatus, in which an electron beam generated by an electron gun of the electron beam method sample surface inspection apparatus is irradiated onto the sample surface, and secondary electrons emanating from the sample surface are formed into an image toward an electron detection plane of a detector for inspecting the sample surface, the method characterized in that a condition for forming the secondary electrons into an image on a detection plane of the detector is controlled such that a potential in the sample surface varies in dependence on an amount of the electron beam irradiated onto the sample surface.

8. 发明授权

US08324726B2 Semiconductor device, electrode member and electrode member fabrication method 有权
标题翻译：半导体器件，电极部件和电极部件的制造方法
公开(公告)号：US08324726B2
公开(公告)日：2012-12-04
申请号：US11351338
申请日：2006-02-10
申请人： Katsuya Okumura , Yoshikazu Takahashi , Kazunori Takenouchi
发明人： Katsuya Okumura , Yoshikazu Takahashi , Kazunori Takenouchi
IPC分类号： H01L23/34
CPC分类号： H01L23/49811 , H01L23/49827 , H01L24/37 , H01L24/40 , H01L24/45 , H01L24/48 , H01L25/0655 , H01L25/072 , H01L2224/37147 , H01L2224/40095 , H01L2224/40139 , H01L2224/40225 , H01L2224/45015 , H01L2224/45124 , H01L2224/45147 , H01L2224/48091 , H01L2224/83801 , H01L2224/84801 , H01L2924/00014 , H01L2924/01002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01068 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/1305 , H01L2924/13055 , H01L2924/351 , H05K1/115 , H01L2924/00 , H01L2924/00015 , H01L2224/05599
摘要： A semiconductor device that improves the heat cycle resistance and power cycle resistance of a power module. An electrode member in which copper posts are formed in a plurality of perforations cut in a support made of a ceramic material is soldered onto a side of an IGBT where an emitter electrode is formed. By soldering the copper posts onto the electrode, heat generated in the IGBT is transferred to the electrode member and is radiated. In addition, even if a material of which the IGBT is made and copper differ in thermal expansivity, stress on a soldered interface is reduced and distortion is reduced. This suppresses the appearance of a crack. As a result, the heat cycle resistance and power cycle resistance of a power module can be improved.
摘要翻译：一种改善功率模块的热循环电阻和功率循环电阻的半导体器件。在由陶瓷材料制成的支撑体上切割的多个穿孔中形成铜柱的电极部件被焊接到形成有发射极的IGBT的一侧。通过将铜柱焊接到电极上，在IGBT中产生的热量转移到电极部件并被辐射。此外，即使制造IGBT的材料和铜的热膨胀性不同，焊接界面上的应力降低，并且变形减小。这样可以抑制裂纹的出现。结果，可以提高功率模块的耐热循环电阻和功率循环电阻。

9. 发明授权

US08283755B2 Multichip semiconductor device, chip therefor and method of formation thereof 有权
标题翻译：多芯片半导体器件，芯片及其形成方法
公开(公告)号：US08283755B2
公开(公告)日：2012-10-09
申请号：US13067180
申请日：2011-05-13
申请人： Nobuo Hayasaka , Katsuya Okumura , Keiichi Sasaki , Mie Matsuo
发明人： Nobuo Hayasaka , Katsuya Okumura , Keiichi Sasaki , Mie Matsuo
IPC分类号： H01L29/40
CPC分类号： H01L23/642 , H01L21/76898 , H01L23/367 , H01L23/481 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/0401 , H01L2224/0557 , H01L2224/06181 , H01L2224/13025 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2225/06572 , H01L2225/06589 , H01L2225/1023 , H01L2225/1058 , H01L2924/01046 , H01L2924/01057 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H01L2924/13091 , H01L2924/15174 , H01L2924/15192 , H01L2924/15311 , H01L2924/1532 , H01L2924/15331 , H01L2924/00
摘要： A multichip semiconductor device is disclosed in which chips are stacked each of which comprises a semiconductor substrate formed on top with circuit components and an interlayer insulating film formed on the top of the semiconductor substrate. At least one of the chips has a connect plug of a metal formed in a through hole that passes through the semiconductor substrate and the interlayer insulating film. The chip with the connect plug is electrically connected with another chip by that connect plug.
摘要翻译：公开了一种多芯片半导体器件，其中堆叠芯片，每个芯片包括形成在顶部的半导体衬底和电路部件，以及形成在半导体衬底的顶部上的层间绝缘膜。至少一个芯片具有穿过半导体衬底和层间绝缘膜的通孔中形成的金属的连接插头。具有连接插头的芯片通过该连接插头与另一个芯片电连接。

10. 发明授权

US08247289B2 Capacitor and manufacturing method thereof 有权
标题翻译：电容器及其制造方法
公开(公告)号：US08247289B2
公开(公告)日：2012-08-21
申请号：US11508141
申请日：2006-08-23
申请人： Yoshiki Yamanishi , Muneo Harada , Takahiro Kitano , Tatsuzo Kawaguchi , Yoshihiro Hirota , Kinji Yamada , Tomotaka Shinoda , Katsuya Okumura , Shuichi Kawano
发明人： Yoshiki Yamanishi , Muneo Harada , Takahiro Kitano , Tatsuzo Kawaguchi , Yoshihiro Hirota , Kinji Yamada , Tomotaka Shinoda , Katsuya Okumura , Shuichi Kawano
IPC分类号： H01L21/8242 , H01L21/20 , H01L21/00
CPC分类号： H01L23/50 , H01G4/228 , H01G4/33 , H01L23/481 , H01L24/81 , H01L2224/81801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01056 , H01L2924/01072 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/30105 , H05K1/162 , H05K3/002 , H05K2201/09509 , H05K2201/096 , H05K2201/10378
摘要： A capacitor having a high quality and a manufacturing method of the same are provided.A capacitor has a lower electrode formed on an oxide film, a dielectric layer formed on the lower electrode, an upper electrode formed so as to face the lower electrode with the dielectric layer between, and an upper electrode formed so as to cover the upper electrode, an opening portion of the upper electrode and an opening portion of the dielectric layer. By forming the upper electrode on the dielectric layer, it is possible to pattern the dielectric layer by using the upper electrode as a mask, and provide a capacitor having a high-quality dielectric layer by preventing impurity diffusion into the dielectric layer. By forming the upper electrode on the dielectric layer, it is possible to prevent the dielectric layer from being exposed to etching liquid, liquid developer, etc.
摘要翻译：提供了具有高质量的电容器及其制造方法。电容器具有形成在氧化膜上的下电极，形成在下电极上的电介质层，形成为与电极之间介电层相对的下电极的上电极和形成为覆盖上电极的上电极，上电极的开口部分和电介质层的开口部分。通过在电介质层上形成上电极，可以通过使用上电极作为掩模对电介质层进行图案化，并且通过防止杂质扩散到电介质层中来提供具有高质量电介质层的电容器。通过在电介质层上形成上部电极，可以防止电介质层暴露于蚀刻液体，液体显影剂等

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