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1. 发明授权

US5489542A Method for fabricating semiconductor device in which threshold voltage shift and charge-pumping current are improved 失效
标题翻译：制造半导体器件的方法，其中阈值电压偏移和电荷泵浦电流得到改善
公开(公告)号：US5489542A
公开(公告)日：1996-02-06
申请号：US91921
申请日：1993-07-16
申请人： Hiroshi Iwai , Toyota Morimoto , Hisayo S. Momose , Kikuo Yamabe , Yoshio Ozawa
发明人： Hiroshi Iwai , Toyota Morimoto , Hisayo S. Momose , Kikuo Yamabe , Yoshio Ozawa
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8238 , H01L29/51 , H01L21/265 , H01L21/02 , H01L21/70 , H01L27/00
CPC分类号： H01L21/28185 , H01L21/28202 , H01L21/823857 , H01L29/513 , H01L29/518 , H01L29/66575 , H01L21/28211
摘要： A method for fabricating a semiconductor device on a silicon substrate, consists of producing a silicon oxide film on the silicon substrate producing a thin silicon nitride film on the silicon oxide film, thermally nitriding the silicon nitride film in an atmosphere of nitrogenous gas, producing a conductive film on the silicon nitride film nitrided in the atmosphere of the nitrogenous gas, producing a gate region from the silicon oxide film, the silicon nitride film, and the conductive film, a channel region being positioned under the gate region in the silicon substrate, producing a source region in the silicon substrate adjacent to one side of the channel region, producing a drain region in the silicon substrate adjacent to another side of the channel region, and producing wiring regions on the source region, the drain region, and the gate region.
摘要翻译：一种在硅衬底上制造半导体器件的方法，包括在硅衬底上产生氧化硅膜，在氧化硅膜上产生薄的氮化硅膜，在氮气气氛中氮化氮化硅膜，氮化硅膜上的导电膜在氮气气氛中氮化，从硅氧化膜，氮化硅膜和导电膜产生栅极区，沟道区位于硅衬底的栅极区下方，在所述硅衬底中邻近所述沟道区的一侧产生源极区，在所述硅衬底中与所述沟道区的另一侧相邻的漏极区产生，并且在所述源极区，所述漏极区和所述栅极上产生布线区地区。

2. 发明授权

US5237188A Semiconductor device with nitrided gate insulating film 失效
标题翻译：具有氮化栅极绝缘膜的半导体器件
公开(公告)号：US5237188A
公开(公告)日：1993-08-17
申请号：US798098
申请日：1991-11-27
申请人： Hiroshi Iwai , Toyota Morimoto , Hisayo S. Momose , Kikuo Yamabe , Yoshio Ozawa
发明人： Hiroshi Iwai , Toyota Morimoto , Hisayo S. Momose , Kikuo Yamabe , Yoshio Ozawa
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8238 , H01L29/51
CPC分类号： H01L21/28185 , H01L21/28202 , H01L21/823857 , H01L29/513 , H01L29/518 , H01L29/66575 , H01L21/28211
摘要： A semiconductor device formed on a silicon substrate consisting of the steps of producing a silicon oxide film on the silicon substrate, producing a thin silicon nitride film on the silicon oxide film, thermally nitriding the silicon nitride film in an atmosphere of nitrogenous gas, producing a conductive film on the silicon nitride film nitrided in the atmosphere of the nitrogenous gas, producing a gate region from the silicon oxide film, the silicon nitride film, and the conductive film, a channel region being positioned under the gate region in the silicon substrate, producing a source region in the silicon substrate adjacent to one side of the channel region, producing a drain region in the silicon substrate adjacent to another side of the channel region, and producing wiring regions on the source region, the drain region, and the gate region.
摘要翻译：一种形成在硅衬底上的半导体器件，包括在硅衬底上制造氧化硅膜的步骤，在氧化硅膜上产生薄氮化硅膜，在氮气气氛中对氮化硅膜进行氮化，产生氮化硅膜上的导电膜在氮气气氛中氮化，从硅氧化膜，氮化硅膜和导电膜产生栅极区，沟道区位于硅衬底的栅极区下方，在所述硅衬底中邻近所述沟道区的一侧产生源极区，在所述硅衬底中与所述沟道区的另一侧相邻的漏极区产生，并且在所述源极区，所述漏极区和所述栅极上产生布线区地区。

3. 发明授权

US08804393B2 Semiconductor memory system 有权
公开(公告)号：US08804393B2
公开(公告)日：2014-08-12
申请号：US13418619
申请日：2012-03-13
申请人： Hayato Masubuchi , Naoki Kimura , Manabu Matsumoto , Toyota Morimoto
发明人： Hayato Masubuchi , Naoki Kimura , Manabu Matsumoto , Toyota Morimoto
IPC分类号： G11C5/02
摘要： According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.

4. 发明授权

US07022531B2 Semiconductor memory device and method of fabricating the same 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US07022531B2
公开(公告)日：2006-04-04
申请号：US10618616
申请日：2003-07-15
申请人： Tohru Ozaki , Iwao Kunishima , Toyota Morimoto , Hiroyuki Kanaya
发明人： Tohru Ozaki , Iwao Kunishima , Toyota Morimoto , Hiroyuki Kanaya
IPC分类号： H01L21/00
CPC分类号： H01L27/11502 , H01L27/11507
摘要： A semiconductor memory device including a memory cell block having a plurality of memory transistors formed on a semiconductor substrate. The memory transistors include first and second impurity-diffused regions and a gate formed therebetween. A plurality of memory cells are also included in the memory cell block and have lower electrodes connected to the first impurity-diffused regions, ferroelectric films formed on the lower electrodes and first upper electrodes formed on the ferroelectric films and connected to the second impurity-diffused regions. Further included are block selecting transistors formed on the semiconductor substrate and being connected to one end of the memory cell block. Second upper electrodes are also formed adjoined to the block selecting transistors and being disconnected from the first upper electrode of the memory cells.
摘要翻译：一种半导体存储器件，包括具有形成在半导体衬底上的多个存储晶体管的存储单元块。存储晶体管包括第一和第二杂质扩散区域以及在它们之间形成的栅极。多个存储单元也包括在存储单元块中，并且具有连接到第一杂质扩散区的下电极，形成在下电极上的铁电膜和形成在铁电体膜上的第一上电极并连接到第二杂质扩散区地区。还包括形成在半导体衬底上并连接到存储单元块的一端的块选择晶体管。第二上电极也形成为与块选择晶体管相邻并且与存储单元的第一上电极断开连接。

5. 发明授权

US08873265B2 Semiconductor memory system 有权
标题翻译：半导体存储器系统
公开(公告)号：US08873265B2
公开(公告)日：2014-10-28
申请号：US13418619
申请日：2012-03-13
申请人： Hayato Masubuchi , Naoki Kimura , Manabu Matsumoto , Toyota Morimoto
发明人： Hayato Masubuchi , Naoki Kimura , Manabu Matsumoto , Toyota Morimoto
IPC分类号： G11C5/02 , H01L23/498 , H05K1/02 , H01L23/31 , H05K3/30
CPC分类号： H01L25/18 , G11C5/02 , H01L23/3121 , H01L23/3142 , H01L23/49822 , H01L23/49838 , H01L23/5286 , H01L23/552 , H01L23/562 , H01L25/0655 , H01L25/50 , H01L27/115 , H01L2924/0002 , H05K1/0225 , H05K1/0271 , H05K1/0298 , H05K1/181 , H05K3/305 , H05K2201/09136 , H05K2201/09681 , H05K2201/10159 , Y02P70/613 , H01L2924/00
摘要： According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.
摘要翻译：根据一个实施例，半导体存储器系统包括衬底，多个元件和粘合剂部分。基板具有其中形成布线图案并且在平面图中具有大致矩形形状的多层结构。元件沿着衬底的表面层侧的长边方向设置和布置。粘合剂部分填充在元件之间的间隙中，并且在元件和基板之间的间隙中填充元件的表面。

6. 发明授权

US06611015B2 Semiconductor device including dummy upper electrode 失效
标题翻译：半导体器件包括虚拟上电极
公开(公告)号：US06611015B2
公开(公告)日：2003-08-26
申请号：US09956001
申请日：2001-09-20
申请人： Tohru Ozaki , Iwao Kunishima , Toyota Morimoto , Hiroyuki Kanaya
发明人： Tohru Ozaki , Iwao Kunishima , Toyota Morimoto , Hiroyuki Kanaya
IPC分类号： H01L27108
CPC分类号： H01L27/11502 , H01L27/11507
摘要： A semiconductor memory device including a memory cell block having a plurality of memory transistors formed on a semiconductor substrate. The memory transistors include first and second impurity-diffused regions and a gate formed therebetween. A plurality of memory cells are also included in the memory cell block and have lower electrodes connected to the first impurity-diffused regions, ferroelectric films formed on the lower electrodes and first upper electrodes formed on the ferroelectric films and connected to the second impurity-diffused regions. Further included are block selecting transistors formed on the semiconductor substrate and being connected to one end of the memory cell block. Second upper electrodes are also formed adjoined to the block selecting transistors and being disconnected from the first upper electrode of the memory cells.
摘要翻译：一种半导体存储器件，包括具有形成在半导体衬底上的多个存储晶体管的存储单元块。存储晶体管包括第一和第二杂质扩散区域以及在它们之间形成的栅极。多个存储单元也包括在存储单元块中，并且具有连接到第一杂质扩散区的下电极，形成在下电极上的铁电膜和形成在铁电体膜上的第一上电极并连接到第二杂质扩散区地区。还包括形成在半导体衬底上并连接到存储单元块的一端的块选择晶体管。第二上电极也形成为与块选择晶体管相邻并且与存储单元的第一上电极断开连接。

7. 发明申请

US20050176199A1 Semiconductor memory device and method of fabricating the same 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20050176199A1
公开(公告)日：2005-08-11
申请号：US10618616
申请日：2003-07-15
申请人： Tohru Ozaki , Iwao Kunishima , Toyota Morimoto , Hiroyuki Kanaya
发明人： Tohru Ozaki , Iwao Kunishima , Toyota Morimoto , Hiroyuki Kanaya
IPC分类号： H01L27/105 , H01L21/8246 , H01L27/115 , H01L21/336
CPC分类号： H01L27/11502 , H01L27/11507
摘要： A semiconductor memory device including a memory cell block having a plurality of memory transistors formed on a semiconductor substrate. The memory transistors include first and second impurity-diffused regions and a gate formed therebetween. A plurality of memory cells are also included in the memory cell block and have lower electrodes connected to the first impurity-diffused regions, ferroelectric films formed on the lower electrodes and first upper electrodes formed on the ferroelectric films and connected to the second impurity-diffused regions. Further included are block selecting transistors formed on the semiconductor substrate and being connected to one end of the memory cell block. Second upper electrodes are also formed adjoined to the block selecting transistors and being disconnected from the first upper electrode of the memory cells.
摘要翻译：一种半导体存储器件，包括具有形成在半导体衬底上的多个存储晶体管的存储单元块。存储晶体管包括第一和第二杂质扩散区域以及在它们之间形成的栅极。多个存储单元也包括在存储单元块中，并且具有连接到第一杂质扩散区的下电极，形成在下电极上的铁电膜和形成在铁电体膜上的第一上电极并连接到第二杂质扩散区地区。还包括形成在半导体衬底上并连接到存储单元块的一端的块选择晶体管。第二上电极也形成为与块选择晶体管相邻并且与存储单元的第一上电极断开连接。

8. 发明授权

US06504198B2 Horizontal type ferroelectric memory and manufacturing method of the same 失效
标题翻译：水平式铁电存储器及其制造方法相同
公开(公告)号：US06504198B2
公开(公告)日：2003-01-07
申请号：US09816478
申请日：2001-03-26
申请人： Toyota Morimoto
发明人： Toyota Morimoto
IPC分类号： H01L2976
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/60 , H01L28/75
摘要： A ferroelectric capacitor is horizontally disposed, in which opposite surfaces of a pair of capacitor electrodes are disposed along the surface of a semiconductor substrate, and an oxidative diffusion barrier film is formed on an upper end of the contact plug having a lower end connected to the diffusion region of a memory cell transistor during the manufacturing steps, after which under the condition where a top end of the contact plug is covered by the oxidative diffusion barrier film, a high-temperature annealing is performed so as to restore any damage applied to the ferroelectric capacitor that may be caused during the manufacturing steps thereof, followed by the removing step of the oxidative diffusion barrier film existing on the surface of the contact plug, and then followed by a forming step of a metallic wiring to obtain a ferroelectric memory product.
摘要翻译：水平设置铁电电容器，其中一对电容器电极的相对表面沿着半导体衬底的表面设置，并且氧化扩散阻挡膜形成在接触插塞的上端，该接触插塞的上端连接到在制造步骤期间存储单元晶体管的扩散区域之后，在接触塞顶端被氧化扩散阻挡膜覆盖的状态下进行高温退火，以恢复对在其制造步骤中可能引起的铁电电容器，随后存在于接触插塞表面上的氧化扩散阻挡膜的去除步骤，随后进行金属布线的形成步骤以获得铁电存储器产品。

9. 发明授权

US06897502B2 Semiconductor memory device and its manufacturing method 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US06897502B2
公开(公告)日：2005-05-24
申请号：US10620698
申请日：2003-07-17
申请人： Shinichi Watanabe , Toyota Morimoto , Tohru Ozaki , Haruhiko Koyama
发明人： Shinichi Watanabe , Toyota Morimoto , Tohru Ozaki , Haruhiko Koyama
IPC分类号： H01L27/105 , H01L21/8246 , H01L27/115 , H01L29/76
CPC分类号： H01L27/11502 , H01L27/11507
摘要： A first impurity diffusion area is formed in the semiconductor substrate at a bottom of the first trench formed in a surface of the semiconductor substrate. A second impurity diffusion area is formed in the surface of the semiconductor substrate, each have one end contacting a first side wall of the first trench, and each have the same conductive type as the first impurity diffusion area. A first gate electrode is provided on the first side wall between the first and second impurity diffusion areas with a gate insulating film interposed therebetween. A first ferroelectric film is provided on a first lower electrode, which is provided on the second impurity area. A first upper electrode is provided on the first ferroelectric film. A first interconnection layer is provided above the first upper electrode. A first contact plug electrically connects the first interconnection layer and first impurity diffusion area.
摘要翻译：在形成于半导体衬底的表面中的第一沟槽的底部的半导体衬底中形成第一杂质扩散区。在半导体基板的表面形成第二杂质扩散区域，每个第一杂质扩散区域的一端与第一沟槽的第一侧壁接触，并且各自具有与第一杂质扩散区域相同的导电类型。第一栅电极设置在第一和第二杂质扩散区之间的第一侧壁上，其间插入有栅极绝缘膜。第一铁电体膜设置在设置在第二杂质区域上的第一下部电极上。第一上电极设置在第一铁电体膜上。第一互连层设置在第一上电极上方。第一接触插塞电连接第一互连层和第一杂质扩散区。

10. 发明申请

US20120235141A1 SEMICONDUCTOR MEMORY SYSTEM 有权
标题翻译：半导体存储系统
公开(公告)号：US20120235141A1
公开(公告)日：2012-09-20
申请号：US13418619
申请日：2012-03-13
申请人： Hayato MASUBUCHI , Naoki Kimura , Manabu Matsumoto , Toyota Morimoto
发明人： Hayato MASUBUCHI , Naoki Kimura , Manabu Matsumoto , Toyota Morimoto
IPC分类号： H01L23/58 , H01L23/48
CPC分类号： H01L25/18 , G11C5/02 , H01L23/3121 , H01L23/3142 , H01L23/49822 , H01L23/49838 , H01L23/5286 , H01L23/552 , H01L23/562 , H01L25/0655 , H01L25/50 , H01L27/115 , H01L2924/0002 , H05K1/0225 , H05K1/0271 , H05K1/0298 , H05K1/181 , H05K3/305 , H05K2201/09136 , H05K2201/09681 , H05K2201/10159 , Y02P70/613 , H01L2924/00
摘要： According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.
摘要翻译：根据一个实施例，半导体存储器系统包括衬底，多个元件和粘合剂部分。基板具有其中形成布线图案并且在平面图中具有大致矩形形状的多层结构。元件沿着衬底的表面层侧的长边方向设置和布置。粘合剂部分填充在元件之间的间隙中，并且在元件和基板之间的间隙中填充元件的表面。

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