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1. 发明授权

US06034878A Source-clock-synchronized memory system and memory unit 失效
标题翻译：源时钟同步存储器系统和存储单元
公开(公告)号：US06034878A
公开(公告)日：2000-03-07
申请号：US992210
申请日：1997-12-16
申请人： Hideki Osaka , Masaya Umemura , Akira Yamagiwa , Toshitsugu Takekuma
发明人： Hideki Osaka , Masaya Umemura , Akira Yamagiwa , Toshitsugu Takekuma
IPC分类号： G06F12/06 , G06F1/10 , G06F12/00 , G06F13/16 , G11C5/00 , G11C11/401 , G11C11/407 , G11C13/00
CPC分类号： G06F13/1684
摘要： A source-clock-synchronized memory system having a large data storage capacity per memory bank and a high mounting density. The invention includes a memory unit having a first memory riser board B1 mounted on a base board through a first connector C1 and a second memory riser board B2 mounted on the base board BB through a second connector C2. The first memory riser board has a plurality of first memory modules mounted on the front surface thereof and the second memory riser board has a plurality of second memory modules mounted on the front surface thereof. The first and second memory riser boards are arranged in such a way that the back surface of the first memory riser board faces the back surface of the second memory riser board. The invention further includes a board linking connector for connecting signal lines on the first memory riser board to corresponding signal lines on the second memory riser board.
摘要翻译：源时钟同步的存储器系统，每个存储体具有大的数据存储容量和高的安装密度。本发明包括具有通过第一连接器C1安装在基板上的第一存储器提升板B1和通过第二连接器C2安装在基板BB上的第二存储器提升板B2的存储单元。第一存储器提升板具有安装在其前表面上的多个第一存储器模块，并且第二存储器提升板具有安装在其前表面上的多个第二存储器模块。第一和第二存储器提升板被布置成使得第一存储器提升板的后表面面向第二存储器提升板的后表面。本发明还包括板连接连接器，用于将第一存储器提升板上的信号线连接到第二存储器提升板上的相应信号线。

2. 发明授权

US6125419A Bus system, printed circuit board, signal transmission line, series circuit and memory module 失效
标题翻译：总线系统，印刷电路板，信号传输线，串联电路和内存模块
公开(公告)号：US6125419A
公开(公告)日：2000-09-26
申请号：US874721
申请日：1997-06-13
申请人： Masaya Umemura , Hideki Osaka , Toshitsugu Takekuma
发明人： Masaya Umemura , Hideki Osaka , Toshitsugu Takekuma
IPC分类号： G06F13/40 , G06F13/00
CPC分类号： G06F13/4086
摘要： There are provided plural synchronous RAMs, a memory controller, a bus for inputting the signal output from the memory controller 1a to the synchronous RAMs, and a bus for inputting the signals output from the synchronous RAMs to the memory controller. Each of the buses has a main line and two stub lines connected to the trunk like. Each of the synchronous RAMs is connected to the corresponding stub line so that the sum of the bus length of the bus between the synchronous RAM and the memory controller and the bus length of the bus between the synchronous RAM and the memory controller is substantially constant among all of said synchronous RAMs. Therefore, the signal transmission time between the bus master and the plural bus slaves can be shortened without increasing the number of pins of the bus master while keeping the signal transmission time substantially constant among the plural bus slaves.
摘要翻译：提供了多个同步RAM，存储器控制器，用于将从存储器控制器1a输出的信号输入到同步RAM的总线，以及用于将从同步RAM输出的信号输入到存储器控制器的总线。每条公交车都有一条主干线和两根短线连接到树干上。每个同步RAM连接到相应的存根线，使得同步RAM和存储器控制器之间的总线总线长度与同步RAM与存储器控制器之间的总线长度之和基本恒定所有的同步RAM。因此，在多个总线从站之间保持信号传输时间基本恒定的同时，可以缩短总线主机与多个总线从站之间的信号传输时间，而不增加总线主机的引脚数。

3. 发明授权

US06766404B1 Branch bus system for inter-LSI data transmission 失效
标题翻译：分支总线系统，用于LSI间数据传输
公开(公告)号：US06766404B1
公开(公告)日：2004-07-20
申请号：US09568055
申请日：2000-05-10
申请人： Hideki Osaka , Akira Yamagiwa , Kenichi Ishibashi
发明人： Hideki Osaka , Akira Yamagiwa , Kenichi Ishibashi
IPC分类号： G06F100
CPC分类号： H04L25/0278 , G06F13/4077
摘要： A fast transfer bus system capable of fast data transfer with no reflection at branch points. Four LSIs having constant-impedance interfaces are connected via two variable resistors each having three signal terminals. A variable impedance LSI is connected between these variable resistors. When the LSIs connected to the variable resistor do not work as a bus driver, three variable resistance elements in each variable resistor are set to have a value of ⅓ of the characteristic impedance Zo of connection lines, and are connected in a Y-letter shape. When one of LSIs connected to the variable resistor works as a bus driver, the values of the variable resistance elements are set to low impedance or Zo.
摘要翻译：快速传输总线系统，能够快速传输数据，在分支点无反射。具有恒定阻抗接口的四个LSI通过两个可变电阻器连接，每个可变电阻器具有三个信号端子。可变阻抗LSI连接在这些可变电阻之间。当连接到可变电阻器的LSI不能用作总线驱动器时，每个可变电阻器中的三个可变电阻元件被设置为连接线的特性阻抗Zo的1/3，并且以Y- 字母形状。当连接到可变电阻器的LSI中的一个作为总线驱动器工作时，可变电阻元件的值被设置为低阻抗或Zo。

4. 发明授权

US06441638B2 Bus system and circuit board 失效
标题翻译：总线系统和电路板
公开(公告)号：US06441638B2
公开(公告)日：2002-08-27
申请号：US09215456
申请日：1998-12-17
申请人： Hideki Osaka , Shinichi Suzuki , Akira Yamagiwa , Toshiro Takahashi
发明人： Hideki Osaka , Shinichi Suzuki , Akira Yamagiwa , Toshiro Takahashi
IPC分类号： H03K1716
CPC分类号： G06F13/4086
摘要： A bus system with an improved propagation velocity, comprising main lines, and a plurality of stub lines provided on a one-to-one correspondence with a plurality of modules, and connecting the corresponding modules to the main lines.
摘要翻译：具有改善的传播速度的总线系统，包括主线，以及与多个模块一一对应地提供的多个短截线，并将相应的模块连接到主线。

5. 发明授权

US06600790B1 Gap-coupling bus system 有权
标题翻译：间隙耦合总线系统
公开(公告)号：US06600790B1
公开(公告)日：2003-07-29
申请号：US09297359
申请日：1999-04-30
申请人： Masaya Umemura , Hideki Osaka
发明人： Masaya Umemura , Hideki Osaka
IPC分类号： H04B300
CPC分类号： G06F13/4072 , H05K1/0228 , H05K1/023 , H05K1/0245 , H05K2201/09263 , H05K2201/097 , H05K2201/10022
摘要： There is provided a gap coupling type bus system, which makes it possible to mutually transfer data between all the modules connected to the bus. The gap coupling type bus system comprises for at least three modules, each module being provided with at least one sending/receiving circuit for sending and receiving a signal: at least three signal lines (21-26) respectively connected to the at least three modules (11-16); and terminating resistors (31-36) connected to respective signal lines at the other ends of the signal lines, each terminating resistor having generally same value as characteristic impedance of the signal line. Those at least three signal lines (21-26) have portions (1-2, 1-3, 2-3, . . . ) laid in parallel with one another with a predetermined gap, correspondingly to every combination of different two modules out of those at least three modules (11-16).
摘要翻译：提供了一种间隙耦合型总线系统，这使得可以在连接到总线的所有模块之间相互传送数据。间隙耦合型总线系统包括至少三个模块，每个模块设置有至少一个用于发送和接收信号的发送/接收电路：至少三个信号线（21-26），分别连接到至少三个模块（11-16）; 以及连接到信号线的另一端的相应信号线的端接电阻器（31-36），每个终端电阻器具有与信号线的特征阻抗大致相同的值。那些至少三条信号线（21-26）具有以预定间隙彼此平行放置的部分（1-2,1-3,3-3 ...），对应于不同的两个模块的每个组合至少有三个模块（11-16）。

6. 发明授权

US5462442A Module for information processing apparatus using stacked printed circuit boards and connector for stacking printed circuit boards 失效
标题翻译：用于堆叠印刷电路板的信息处理装置和用于堆叠印刷电路板的连接器的模块
公开(公告)号：US5462442A
公开(公告)日：1995-10-31
申请号：US197841
申请日：1994-02-17
申请人： Masaya Umemura , Toshihiko Ogura , Hideki Osaka , Masatsugu Shinozaki
发明人： Masaya Umemura , Toshihiko Ogura , Hideki Osaka , Masatsugu Shinozaki
IPC分类号： H01R24/00 , H01R31/06 , H05K1/14 , H05K7/14 , H05K1/00
CPC分类号： H01R23/68 , H05K1/144 , H05K7/1441 , H01R12/722
摘要： In a connector having a plurality of first contact groups arranged in a predetermined pattern, conductors whose one ends are connected to the first contact groups, and a plurality of second contact groups arranged in a pattern corresponding to the pattern of the first contact groups, the conductors for connecting the first contact groups and the second contact groups cause portions of the first contact groups to be connected to the second contact groups at different positions within the above-described pattern. Accordingly, even when the contacts of the same sort of signal lines having one-to-one correspondence are allocated to the contact conductors located at the same positions within the boards for constituting the respective modules, the one-to-one correspondence can be maintained, and thus the printed-circuit boards of the modules can be commonly utilized.
摘要翻译：在具有以预定图案布置的多个第一接触组的连接器中，其一端连接到第一接触组的导体和以与第一接触组的图案对应的图案布置的多个第二接触组，用于连接第一接触组和第二接触组的导体使得第一接触组的部分在上述图案中的不同位置处连接到第二接触组。因此，即使将具有一一对应的相同种类的信号线的触点分配给位于用于构成各个模块的板内的相同位置的接触导体，也可以保持一一对应，因此可以通常使用模块的印刷电路板。

7. 发明授权

US06496886B1 Directional coupling bus system using printed board 失效
标题翻译：使用印刷板的定向耦合总线系统
公开(公告)号：US06496886B1
公开(公告)日：2002-12-17
申请号：US09429441
申请日：1999-10-28
申请人： Hideki Osaka , Toyohiko Komatsu , Masahiro Kitano , Akira Yamagiwa , Ryoichi Kurihara
发明人： Hideki Osaka , Toyohiko Komatsu , Masahiro Kitano , Akira Yamagiwa , Ryoichi Kurihara
IPC分类号： H01P518
CPC分类号： H01P5/185 , H01P5/187 , H05K1/0228 , H05K1/023 , H05K1/0239 , H05K3/4623 , H05K2201/09236 , H05K2201/09845 , H05K2201/10689
摘要： In a printed board mounting method using a directional coupling bus for a high-speed data transfer, multi-bit data are transferred between nodes at a low cost. For this purpose, to transfer multi-bit data by directional coupling, a one-bit multi-coupling wiring network is vertically configured in a multilayered printed board. This minimizes the width of an area occupied by each bit along a wiring direction of the board to thereby implement a multi-bit configuration.
摘要翻译：在使用用于高速数据传输的定向耦合总线的印刷电路板安装方法中，以比较低的成本在节点之间传送多位数据。为此，为了通过定向耦合传输多位数据，在多层印刷电路板中垂直配置一位多耦合布线网络。这使得沿着板的布线方向的每个位占据的面积的宽度最小化，从而实现多位配置。

8. 发明授权

US5787261A Data transfer system, computer system and active-line inserted/withdrawn functional circuit board 失效
标题翻译：数据传输系统，计算机系统和有源线插拔功能电路板
公开(公告)号：US5787261A
公开(公告)日：1998-07-28
申请号：US563106
申请日：1995-11-27
申请人： Hideki Osaka , Akira Yamagiwa , Ryoichi Kurihara , Masao Inoue
发明人： Hideki Osaka , Akira Yamagiwa , Ryoichi Kurihara , Masao Inoue
IPC分类号： G06F13/40 , G06F13/00
CPC分类号： G06F13/4081
摘要： It is an object of the present invention to provide an active-line inserted/withdrawn functional circuit board, a data transfer system and a computer system which systems allow the functional circuit board to be inserted and withdrawn with signal lines remaining in an active state while achieving a high speed data-transfer of a bus, and the reliability to be enhanced by eliminating malfunctions which occur particularly during the insertion of a functional circuit board. The data transfer system or the computer system comprising: a functional circuit board having a functional circuit, a pre-charge resistor and a switching element connected in parallel to an input/output signal path of the functional circuit and a switching control means for controlling the conduction of the switching element through synchronization with a delayed clock signal resulting from delaying a bus clock signal for use in data transfers through the bus by a time shorter than a bus-clock cycle time of the bus clock signal; and a connector provided on an input/output end of the parallel connection of the pre-charge resistor and the switching element, whereby the functional circuit board can be inserted and withdrawn to and from the bus.
摘要翻译：本发明的目的是提供一种有源线插入/取出功能电路板，数据传输系统和计算机系统，其中系统允许功能电路板被插入和撤回，信号线保持在活动状态，同时实现总线的高速数据传送，以及通过消除特别是在插入功能电路板期间发生的故障而增强的可靠性。数据传送系统或计算机系统包括：功能电路板，具有与功能电路的输入/输出信号路径并联连接的功能电路，预充电电阻和开关元件;以及开关控制装置，用于控制功能电路开关元件通过与延迟总线时钟信号的延迟时钟信号同步地传导，以用于通过总线的数据传输比总线时钟信号的总线时钟周期时间短的时间; 以及设置在预充电电阻器和开关元件的并联连接的输入/输出端上的连接器，由此功能电路板可以从总线插入和拔出。

9. 发明申请

US20130132056A1 SIMULATION APPARATUS AND SIMULATION METHOD 有权
标题翻译：模拟装置和模拟方法
公开(公告)号：US20130132056A1
公开(公告)日：2013-05-23
申请号：US13702636
申请日：2011-05-13
申请人： Tadanobu Toba , Kenichi Shimbo , Hidefumi Ibe , Hideki Osaka
发明人： Tadanobu Toba , Kenichi Shimbo , Hidefumi Ibe , Hideki Osaka
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G01R31/31816 , G06F17/5022 , G06F2217/70
摘要： A simulation apparatus includes a discrete events simulation section to perform a discrete type simulation of components of a configured model as defined based on attribute information that is information on parts of the components of the defined configured model and connection information showing a connectional relationship among the components of the defined configured model; and a soft error rate computation processing section to compute a soft error rate of the defined configured model based on the simulation result of the discrete events simulation section and data on soft error rates in the attribute information.
摘要翻译：模拟装置包括：离散事件模拟部分，用于执行基于属性信息定义的配置模型的分量的离散类型模拟，所述属性信息是关于所定义的配置模型的组件的部分的信息，以及示出组件之间的连接关系的连接信息的定义配置模型; 以及软错误率计算处理部，基于离散事件模拟部的模拟结果和属性信息中的软错误率的数据来计算定义的配置模型的软错误率。

10. 发明授权

US07711817B2 Data processing apparatus and network system that outputs quality of service information to a user 失效
标题翻译：向用户输出服务质量信息的数据处理装置和网络系统
公开(公告)号：US07711817B2
公开(公告)日：2010-05-04
申请号：US12243081
申请日：2008-10-01
申请人： Ryuichi Hattori , Toshihiko Ogura , Takashi Oeda , Koichi Okazawa , Hideki Osaka , Tsunehiro Tobita , Tsutomu Hara
发明人： Ryuichi Hattori , Toshihiko Ogura , Takashi Oeda , Koichi Okazawa , Hideki Osaka , Tsunehiro Tobita , Tsutomu Hara
IPC分类号： G06F15/173
CPC分类号： G06F9/5055 , G06F9/5044 , G06F2209/5015 , H04L29/12047 , H04L41/5009 , H04L61/15 , H04L67/36
摘要： In each of the information processing apparatuses connected to each other via a network, there is arranged a quality of service (QOS) table to which functions and performance thereof are registered. When an information processing apparatus is additionally linked with the network, a QOS table thereof is automatically registered to a local directory of the network such that an agent converts the contents of the QOS table into service information to be supplied via a user interface to the user. Thanks to the operation, information of functions and performance of each information processing apparatus connected to the network is converted into service information for the user. Consequently, the user can much more directly receive necessary services.
摘要翻译：在通过网络彼此连接的每个信息处理设备中，布置了其功能和性能被注册到其中的服务质量（QOS）表。当信息处理设备另外与网络链接时，其QOS表被自动地注册到网络的本地目录，使得代理将QOS表的内容转换成要经由用户界面提供给用户的服务信息。由于操作，连接到网络的每个信息处理设备的功能和性能的信息被转换成用户的服务信息。因此，用户可以更多地直接接收必要的服务。

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