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1. 发明授权

US06766404B1 Branch bus system for inter-LSI data transmission 失效
标题翻译：分支总线系统，用于LSI间数据传输
公开(公告)号：US06766404B1
公开(公告)日：2004-07-20
申请号：US09568055
申请日：2000-05-10
申请人： Hideki Osaka , Akira Yamagiwa , Kenichi Ishibashi
发明人： Hideki Osaka , Akira Yamagiwa , Kenichi Ishibashi
IPC分类号： G06F100
CPC分类号： H04L25/0278 , G06F13/4077
摘要： A fast transfer bus system capable of fast data transfer with no reflection at branch points. Four LSIs having constant-impedance interfaces are connected via two variable resistors each having three signal terminals. A variable impedance LSI is connected between these variable resistors. When the LSIs connected to the variable resistor do not work as a bus driver, three variable resistance elements in each variable resistor are set to have a value of ⅓ of the characteristic impedance Zo of connection lines, and are connected in a Y-letter shape. When one of LSIs connected to the variable resistor works as a bus driver, the values of the variable resistance elements are set to low impedance or Zo.
摘要翻译：快速传输总线系统，能够快速传输数据，在分支点无反射。具有恒定阻抗接口的四个LSI通过两个可变电阻器连接，每个可变电阻器具有三个信号端子。可变阻抗LSI连接在这些可变电阻之间。当连接到可变电阻器的LSI不能用作总线驱动器时，每个可变电阻器中的三个可变电阻元件被设置为连接线的特性阻抗Zo的1/3，并且以Y- 字母形状。当连接到可变电阻器的LSI中的一个作为总线驱动器工作时，可变电阻元件的值被设置为低阻抗或Zo。

2. 发明授权

US06441638B2 Bus system and circuit board 失效
标题翻译：总线系统和电路板
公开(公告)号：US06441638B2
公开(公告)日：2002-08-27
申请号：US09215456
申请日：1998-12-17
申请人： Hideki Osaka , Shinichi Suzuki , Akira Yamagiwa , Toshiro Takahashi
发明人： Hideki Osaka , Shinichi Suzuki , Akira Yamagiwa , Toshiro Takahashi
IPC分类号： H03K1716
CPC分类号： G06F13/4086
摘要： A bus system with an improved propagation velocity, comprising main lines, and a plurality of stub lines provided on a one-to-one correspondence with a plurality of modules, and connecting the corresponding modules to the main lines.
摘要翻译：具有改善的传播速度的总线系统，包括主线，以及与多个模块一一对应地提供的多个短截线，并将相应的模块连接到主线。

3. 发明授权

US5666302A Simultaneous bidirectional transmission apparatus for transmitting and receiving differential signals 失效
标题翻译：用于发送和接收差分信号的同时双向传输装置
公开(公告)号：US5666302A
公开(公告)日：1997-09-09
申请号：US496195
申请日：1995-06-28
申请人： Akira Tanaka , Kenichi Ishibashi , Akira Yamagiwa , Takehisa Hayashi
发明人： Akira Tanaka , Kenichi Ishibashi , Akira Yamagiwa , Takehisa Hayashi
IPC分类号： H04L5/14 , H04B1/58 , H04B3/20 , H04L25/02 , G06G7/02
CPC分类号： H04B1/58 , H04B1/583 , H04B1/586
摘要： A simultaneous bidirectional transmission apparatus for transmitting and receiving differential signals solves a generation of pulse noise problem in the receiving circuit due to the inversion of the output of the transmission circuit. For a pair of input/output devices connected together by transmission lines, each input/output device has a differential transmitting circuit, a differential receiving circuit and six resistors. The output of the transmitting circuit does not affect an input to the receiving circuit, and the receiving circuit receives only the output of the transmitting circuit of the other input/output device. The resistors, a passive element circuit and the output resistance of the transmitting circuit form, in combination, a waveform shaping filter and a matching terminating circuit.
摘要翻译：用于发送和接收差分信号的同时双向传输装置由于传输电路的输出反转而解决接收电路中的脉冲噪声问题的产生。对于通过传输线连接在一起的一对输入/输出设备，每个输入/输出设备具有差分发射电路，差分接收电路和六个电阻器。发送电路的输出不影响到接收电路的输入，接收电路仅接收另一个输入/输出装置的发送电路的输出。电阻器，无源元件电路和发射电路的输出电阻组合形成波形整形滤波器和匹配终端电路。

4. 发明授权

US06034878A Source-clock-synchronized memory system and memory unit 失效
标题翻译：源时钟同步存储器系统和存储单元
公开(公告)号：US06034878A
公开(公告)日：2000-03-07
申请号：US992210
申请日：1997-12-16
申请人： Hideki Osaka , Masaya Umemura , Akira Yamagiwa , Toshitsugu Takekuma
发明人： Hideki Osaka , Masaya Umemura , Akira Yamagiwa , Toshitsugu Takekuma
IPC分类号： G06F12/06 , G06F1/10 , G06F12/00 , G06F13/16 , G11C5/00 , G11C11/401 , G11C11/407 , G11C13/00
CPC分类号： G06F13/1684
摘要： A source-clock-synchronized memory system having a large data storage capacity per memory bank and a high mounting density. The invention includes a memory unit having a first memory riser board B1 mounted on a base board through a first connector C1 and a second memory riser board B2 mounted on the base board BB through a second connector C2. The first memory riser board has a plurality of first memory modules mounted on the front surface thereof and the second memory riser board has a plurality of second memory modules mounted on the front surface thereof. The first and second memory riser boards are arranged in such a way that the back surface of the first memory riser board faces the back surface of the second memory riser board. The invention further includes a board linking connector for connecting signal lines on the first memory riser board to corresponding signal lines on the second memory riser board.
摘要翻译：源时钟同步的存储器系统，每个存储体具有大的数据存储容量和高的安装密度。本发明包括具有通过第一连接器C1安装在基板上的第一存储器提升板B1和通过第二连接器C2安装在基板BB上的第二存储器提升板B2的存储单元。第一存储器提升板具有安装在其前表面上的多个第一存储器模块，并且第二存储器提升板具有安装在其前表面上的多个第二存储器模块。第一和第二存储器提升板被布置成使得第一存储器提升板的后表面面向第二存储器提升板的后表面。本发明还包括板连接连接器，用于将第一存储器提升板上的信号线连接到第二存储器提升板上的相应信号线。

5. 发明授权

US5787261A Data transfer system, computer system and active-line inserted/withdrawn functional circuit board 失效
标题翻译：数据传输系统，计算机系统和有源线插拔功能电路板
公开(公告)号：US5787261A
公开(公告)日：1998-07-28
申请号：US563106
申请日：1995-11-27
申请人： Hideki Osaka , Akira Yamagiwa , Ryoichi Kurihara , Masao Inoue
发明人： Hideki Osaka , Akira Yamagiwa , Ryoichi Kurihara , Masao Inoue
IPC分类号： G06F13/40 , G06F13/00
CPC分类号： G06F13/4081
摘要： It is an object of the present invention to provide an active-line inserted/withdrawn functional circuit board, a data transfer system and a computer system which systems allow the functional circuit board to be inserted and withdrawn with signal lines remaining in an active state while achieving a high speed data-transfer of a bus, and the reliability to be enhanced by eliminating malfunctions which occur particularly during the insertion of a functional circuit board. The data transfer system or the computer system comprising: a functional circuit board having a functional circuit, a pre-charge resistor and a switching element connected in parallel to an input/output signal path of the functional circuit and a switching control means for controlling the conduction of the switching element through synchronization with a delayed clock signal resulting from delaying a bus clock signal for use in data transfers through the bus by a time shorter than a bus-clock cycle time of the bus clock signal; and a connector provided on an input/output end of the parallel connection of the pre-charge resistor and the switching element, whereby the functional circuit board can be inserted and withdrawn to and from the bus.
摘要翻译：本发明的目的是提供一种有源线插入/取出功能电路板，数据传输系统和计算机系统，其中系统允许功能电路板被插入和撤回，信号线保持在活动状态，同时实现总线的高速数据传送，以及通过消除特别是在插入功能电路板期间发生的故障而增强的可靠性。数据传送系统或计算机系统包括：功能电路板，具有与功能电路的输入/输出信号路径并联连接的功能电路，预充电电阻和开关元件;以及开关控制装置，用于控制功能电路开关元件通过与延迟总线时钟信号的延迟时钟信号同步地传导，以用于通过总线的数据传输比总线时钟信号的总线时钟周期时间短的时间; 以及设置在预充电电阻器和开关元件的并联连接的输入/输出端上的连接器，由此功能电路板可以从总线插入和拔出。

6. 发明授权

US5872471A Simultaneous bidirectional transmission circuit 失效
标题翻译：同时双向传输电路
公开(公告)号：US5872471A
公开(公告)日：1999-02-16
申请号：US773307
申请日：1996-12-24
申请人： Kenichi Ishibashi , Takehisa Hayashi , Tsutomu Goto , Akira Yamagiwa , Toshitsugu Takekuma , Toshiro Takahashi , Tatsuhiro Aida
发明人： Kenichi Ishibashi , Takehisa Hayashi , Tsutomu Goto , Akira Yamagiwa , Toshitsugu Takekuma , Toshiro Takahashi , Tatsuhiro Aida
IPC分类号： H03K19/0185 , H04L5/14 , H03K17/00
CPC分类号： H03K19/018592 , H04L5/1423
摘要： In a simultaneous bidirectional transmission circuit for conducting simultaneous two-way communication between LSIs via a transmission line, an input/output circuit connected to the transmission line is included in an LSI. The input/output circuit has a driver and a receiver. The driver sends out an output signal depending on a logical signal within the LSI to the transmission line. The receiver receives a mixed signal having a mixture of a received signal and the output signal via the transmission line. The signal to be received by the receiver in an LSI has been sent out to the transmission line by the other party i.e., another LSI in communication therewith. The receiver receives the logical signal output as well. The receives derives a difference between the mixed signal and the logical signal output, thereby removing the component of the logical signal from the mixed signal, and outputs the received signal. The receiver has a reference circuit for receiving the logical signal and outputting it to a bias circuit, a bias circuit for generating a divided voltage signal in conjunction with internal resistance of the reference circuit, and a differential receiver for receiving the mixed signal and the divided voltage signal and outputting the difference between them. The reference circuit and the bias circuit are formed by using MOS transistors.
摘要翻译：在用于经由传输线在LSI之间进行同时双向通信的同时双向传输电路中，连接到传输线的输入/输出电路被包括在LSI中。输入/输出电路具有驱动器和接收器。驱动器根据LSI内的逻辑信号将输出信号发送到传输线。接收机通过传输线接收具有接收信号和输出信号的混合的混合信号。由LSI中的接收机接收到的信号已被另一方发送到传输线，即与其通信的另一个LSI。接收器也接收逻辑信号输出。接收导出混合信号和逻辑信号输出之间的差异，从而从混合信号中去除逻辑信号的分量，并输出接收信号。接收器具有用于接收逻辑信号并将其输出到偏置电路的参考电路，用于产生与参考电路的内部电阻相分离的电压信号的偏置电路，以及用于接收混合信号和分频的差分接收器电压信号并输出它们之间的差异。参考电路和偏置电路通过使用MOS晶体管形成。

7. 发明授权

US5794020A Data transfer apparatus fetching reception data at maximum margin of timing 失效
标题翻译：数据传送装置以最大的定时边缘取出接收数据
公开(公告)号：US5794020A
公开(公告)日：1998-08-11
申请号：US663982
申请日：1996-06-14
申请人： Akira Tanaka , Toshio Doi , Kenichi Ishibashi , Takehisa Hayashi , Akira Yamagiwa
发明人： Akira Tanaka , Toshio Doi , Kenichi Ishibashi , Takehisa Hayashi , Akira Yamagiwa
IPC分类号： H04L7/00 , G06F1/12 , H04L7/02 , H04L7/033 , H04L7/08
CPC分类号： H04L7/0337 , H04L7/0008 , H04L7/0041
摘要： A first variable delay circuit delays the reception data from the transmitting unit which is outputted from an input buffer and generates the delayed data to a data unidentifying time detecting portion. First and second latches have latch timings at regular intervals before and after a latch timing of a third latch for receiving and outputting by second and third variable delay circuits, respectively. In an adjusting operation, delay amounts of the second and third variable delay circuits are fixed to a value which is sufficiently smaller than a transfer period, a delay amount of the variable delay circuit is increased, a judging circuit detects a preceding edge of the reception data, subsequently, the delay amounts of the second and third variable delay circuits are sequentially increased while maintaining to the same value, and a following edge of the reception data is detected. In this instance, the timing of the third latch is set to the optimum point of the maximum margin. In a normal operation, the judging circuit detects a deviation from the optimum point and the delay amount of the first variable delay circuit is finely adjusted in accordance with the detection, thereby maintaining the latch timing of the reception data at the optimum point.
摘要翻译：第一可变延迟电路延迟从输入缓冲器输出的发送单元的接收数据，并将延迟的数据生成到数据未识别时间检测部分。第一和第二锁存器分别在第三锁存器的锁存定时之前和之后以规则的间隔分别具有第二和第三可变延迟电路接收和输出的锁存定时。在调整操作中，第二和第三可变延迟电路的延迟量被固定为足够小于传送周期的值，可变延迟电路的延迟量增加，判断电路检测到接收的前一边缘数据，随后，第二和第三可变延迟电路的延迟量依次增加同时保持相同的值，并且检测接收数据的后沿。在这种情况下，第三锁存器的定时被设置为最大裕量的最佳点。在正常操作中，判断电路检测到与最佳点的偏差，并且根据检测精细地调整第一可变延迟电路的延迟量，从而将接收数据的锁存定时保持在最佳点。

8. 发明授权

US06049221A Semiconductor integrated circuit system having function of automatically adjusting output resistance value 失效
标题翻译：具有自动调节输出电阻值功能的半导体集成电路系统
公开(公告)号：US06049221A
公开(公告)日：2000-04-11
申请号：US111804
申请日：1998-07-08
申请人： Kenichi Ishibashi , Takehisa Hayashi , Tsutomu Goto , Hideki Murayama , Akira Yamagiwa , Yasuhiro Ishii , Naoki Hamanaka , Masabumi Shibata
发明人： Kenichi Ishibashi , Takehisa Hayashi , Tsutomu Goto , Hideki Murayama , Akira Yamagiwa , Yasuhiro Ishii , Naoki Hamanaka , Masabumi Shibata
IPC分类号： H03K19/003 , H03K19/00 , H03K19/0175 , H04L25/02 , H03K19/175
CPC分类号： H03K19/0005
摘要： A semiconductor integrated circuit system having a function of automatically adjusting an output resistance value with reference to a temperature of an LSI which is operating. When a count value obtained from a counter by counting the output of a timer becomes equal to a predetermined value, a temperature sensor measures temperatures of LSIs. If a temperature fluctuation measured from a previous measured value is greater than a predetermined width, then a control apparatus issues an output resistance value adjustment request signal to output resistance adjustment units of the LSIs. When receiving the output resistance value adjustment request signal, the output resistance value adjustment units stop the signal transmission between the LSIs, adjust output resistance values of output circuits in such a manner that the output resistance values are matched with a characteristic impedance of a transmission line, and maintains the adjusted output resistance values until the output resistance value adjustment units receive next output resistance value adjustment request signal.
摘要翻译：具有参照正在运行的LSI的温度来自动调整输出电阻值的功能的半导体集成电路系统。当通过对计时器的输出进行计数而得到的计数值等于预定值时，温度传感器测量LSI的温度。如果从先前测量值测量的温度波动大于预定宽度，则控制装置发出输出电阻值调整请求信号以输出LSI的电阻调节单元。当接收到输出电阻值调整请求信号时，输出电阻值调节单元停止LSI之间的信号传输，以输出电阻值与传输线的特性阻抗匹配的方式调整输出电路的输出电阻值并保持调整后的输出电阻值直到输出电阻值调整单元接收到下一个输出电阻值调整请求信号。

9. 发明授权

US5867541A Method and system for synchronizing data having skew 失效
标题翻译：用于同步具有偏斜的数据的方法和系统
公开(公告)号：US5867541A
公开(公告)日：1999-02-02
申请号：US441613
申请日：1995-05-15
申请人： Akira Tanaka , Kenichi Ishibashi , Takehisa Hayashi , Akira Yamagiwa
发明人： Akira Tanaka , Kenichi Ishibashi , Takehisa Hayashi , Akira Yamagiwa
IPC分类号： G06F13/42 , H04L7/00 , H04L7/033
CPC分类号： H04L7/0337 , H04L7/0037 , H04L7/0008
摘要： Data is transmitted from any one of a plurality of transmitters in synchronism with a first clock. A receiver receives the data in synchronism with the first clock and a second clock having a predetermined phase relationship with the first clock. Control information is previously held in the receiver regarding data reception conditions associated with the plurality of transmitters to control reception conditions of the receiver on the basis of the control information.
摘要翻译：数据从多个发射机中的任何一个与第一时钟同步发送。接收机与第一时钟同步地接收数据，第二时钟与第一时钟具有预定的相位关系。先前在接收机中保持与多个发射机有关的数据接收条件的控制信息，以根据控制信息来控制接收机的接收条件。

10. 发明授权

US06496886B1 Directional coupling bus system using printed board 失效
标题翻译：使用印刷板的定向耦合总线系统
公开(公告)号：US06496886B1
公开(公告)日：2002-12-17
申请号：US09429441
申请日：1999-10-28
申请人： Hideki Osaka , Toyohiko Komatsu , Masahiro Kitano , Akira Yamagiwa , Ryoichi Kurihara
发明人： Hideki Osaka , Toyohiko Komatsu , Masahiro Kitano , Akira Yamagiwa , Ryoichi Kurihara
IPC分类号： H01P518
CPC分类号： H01P5/185 , H01P5/187 , H05K1/0228 , H05K1/023 , H05K1/0239 , H05K3/4623 , H05K2201/09236 , H05K2201/09845 , H05K2201/10689
摘要： In a printed board mounting method using a directional coupling bus for a high-speed data transfer, multi-bit data are transferred between nodes at a low cost. For this purpose, to transfer multi-bit data by directional coupling, a one-bit multi-coupling wiring network is vertically configured in a multilayered printed board. This minimizes the width of an area occupied by each bit along a wiring direction of the board to thereby implement a multi-bit configuration.
摘要翻译：在使用用于高速数据传输的定向耦合总线的印刷电路板安装方法中，以比较低的成本在节点之间传送多位数据。为此，为了通过定向耦合传输多位数据，在多层印刷电路板中垂直配置一位多耦合布线网络。这使得沿着板的布线方向的每个位占据的面积的宽度最小化，从而实现多位配置。

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