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1. 发明授权

US6125419A Bus system, printed circuit board, signal transmission line, series circuit and memory module 失效
标题翻译：总线系统，印刷电路板，信号传输线，串联电路和内存模块
公开(公告)号：US6125419A
公开(公告)日：2000-09-26
申请号：US874721
申请日：1997-06-13
申请人： Masaya Umemura , Hideki Osaka , Toshitsugu Takekuma
发明人： Masaya Umemura , Hideki Osaka , Toshitsugu Takekuma
IPC分类号： G06F13/40 , G06F13/00
CPC分类号： G06F13/4086
摘要： There are provided plural synchronous RAMs, a memory controller, a bus for inputting the signal output from the memory controller 1a to the synchronous RAMs, and a bus for inputting the signals output from the synchronous RAMs to the memory controller. Each of the buses has a main line and two stub lines connected to the trunk like. Each of the synchronous RAMs is connected to the corresponding stub line so that the sum of the bus length of the bus between the synchronous RAM and the memory controller and the bus length of the bus between the synchronous RAM and the memory controller is substantially constant among all of said synchronous RAMs. Therefore, the signal transmission time between the bus master and the plural bus slaves can be shortened without increasing the number of pins of the bus master while keeping the signal transmission time substantially constant among the plural bus slaves.
摘要翻译：提供了多个同步RAM，存储器控制器，用于将从存储器控制器1a输出的信号输入到同步RAM的总线，以及用于将从同步RAM输出的信号输入到存储器控制器的总线。每条公交车都有一条主干线和两根短线连接到树干上。每个同步RAM连接到相应的存根线，使得同步RAM和存储器控制器之间的总线总线长度与同步RAM与存储器控制器之间的总线长度之和基本恒定所有的同步RAM。因此，在多个总线从站之间保持信号传输时间基本恒定的同时，可以缩短总线主机与多个总线从站之间的信号传输时间，而不增加总线主机的引脚数。

2. 发明授权

US06034878A Source-clock-synchronized memory system and memory unit 失效
标题翻译：源时钟同步存储器系统和存储单元
公开(公告)号：US06034878A
公开(公告)日：2000-03-07
申请号：US992210
申请日：1997-12-16
申请人： Hideki Osaka , Masaya Umemura , Akira Yamagiwa , Toshitsugu Takekuma
发明人： Hideki Osaka , Masaya Umemura , Akira Yamagiwa , Toshitsugu Takekuma
IPC分类号： G06F12/06 , G06F1/10 , G06F12/00 , G06F13/16 , G11C5/00 , G11C11/401 , G11C11/407 , G11C13/00
CPC分类号： G06F13/1684
摘要： A source-clock-synchronized memory system having a large data storage capacity per memory bank and a high mounting density. The invention includes a memory unit having a first memory riser board B1 mounted on a base board through a first connector C1 and a second memory riser board B2 mounted on the base board BB through a second connector C2. The first memory riser board has a plurality of first memory modules mounted on the front surface thereof and the second memory riser board has a plurality of second memory modules mounted on the front surface thereof. The first and second memory riser boards are arranged in such a way that the back surface of the first memory riser board faces the back surface of the second memory riser board. The invention further includes a board linking connector for connecting signal lines on the first memory riser board to corresponding signal lines on the second memory riser board.
摘要翻译：源时钟同步的存储器系统，每个存储体具有大的数据存储容量和高的安装密度。本发明包括具有通过第一连接器C1安装在基板上的第一存储器提升板B1和通过第二连接器C2安装在基板BB上的第二存储器提升板B2的存储单元。第一存储器提升板具有安装在其前表面上的多个第一存储器模块，并且第二存储器提升板具有安装在其前表面上的多个第二存储器模块。第一和第二存储器提升板被布置成使得第一存储器提升板的后表面面向第二存储器提升板的后表面。本发明还包括板连接连接器，用于将第一存储器提升板上的信号线连接到第二存储器提升板上的相应信号线。

3. 发明授权

US5933623A Synchronous data transfer system 失效
标题翻译：同步数据传输系统
公开(公告)号：US5933623A
公开(公告)日：1999-08-03
申请号：US736212
申请日：1996-10-25
申请人： Masaya Umemura , Toshitsugu Takekuma
发明人： Masaya Umemura , Toshitsugu Takekuma
IPC分类号： G06F13/42 , G06F15/163
CPC分类号： G06F13/4243
摘要： A synchronous data transfer system includes an oscillation circuit and a plurality of nodes connected to the oscillation circuit. Each node includes at least an internal logic circuit. Each of the nodes outputs a phase reference signal indicating phase of the clock signal, data processed by the internal logic circuit in response to the phase reference signal, and a transfer end signal indicating an end of transferring the data, respectively, in synchronism with the clock signal. A phase reference signal bus is connected to each node. A data bus is connected to each node for transmitting the data and a transfer end signal bus is connected to each node for transmitting the transfer end signal. A sender node includes a sending unit for sending data to a receiver node with a delay after the phase reference signal transmitted to the phase reference signal bus by the sender node, and sending simultaneously the transfer end signal to the receiver node. The receiver node includes a selecting unit for converting the phase reference signal into phase information to select a clock signal having a predetermined phase based on the received clock signal and a receiving unit for receiving data from the sender node using the selected clock signal.
摘要翻译：同步数据传输系统包括振荡电路和连接到振荡电路的多个节点。每个节点至少包括一个内部逻辑电路。每个节点输出指示时钟信号的相位的相位参考信号，响应于相位参考信号由内部逻辑电路处理的数据，以及指示分别传送数据的结束的传送结束信号，与时钟信号。相位参考信号总线连接到每个节点。数据总线连接到每个节点用于发送数据，并且传送结束信号总线连接到每个节点用于发送传送结束信号。发送方节点包括发送单元，用于在发送方节点将相位参考信号发送到相位参考信号总线之后延迟地向接收方节点发送数据，同时将发送结束信号发送到接收方节点。接收器节点包括：选择单元，用于将相位参考信号转换成相位信息，以基于接收到的时钟信号选择具有预定相位的时钟信号;以及接收单元，用于使用所选择的时钟信号从发送器节点接收数据。

4. 发明授权

US6088829A Synchronous data transfer system 有权
标题翻译：同步数据传输系统
公开(公告)号：US6088829A
公开(公告)日：2000-07-11
申请号：US261177
申请日：1999-03-03
申请人： Masaya Umemura , Toshitsugu Takekuma
发明人： Masaya Umemura , Toshitsugu Takekuma
IPC分类号： G06F13/42
CPC分类号： G06F13/4243
摘要： A synchronous data transfer system includes an oscillation circuit and a plurality of nodes connected to the oscillation circuit and each including at least an internal logic circuit. Each of the nodes outputs a phase reference signal indicating phase of the clock signal, data processed by the internal logic circuit provided internally of the node. The system further includes a transfer end signal indicating an end of the data transfer, in synchronism with the clock signal, and a phase reference signal bus connected to each of the plural nodes, a data bus connected to each of the plural nodes for transmitting the data and a transfer end signal bus connected to each of the plural nodes for transmitting the transfer end signal. A sender node of the plural nodes includes sending unit for sending the data to a receiver node of the plural nodes with a delay relative to the phase reference signal which the sender node itself sent onto the phase reference signal bus while sending simultaneously the transfer end signal to the receiver node, whereas the receiver node includes at least a selecting unit for converting the phase reference signal received into phase information to thereby select a clock signal having a predetermined phase with the clock signal received by the receiver node and a receiving unit for receiving the data from the sender node by using the selected clock signal.
摘要翻译：同步数据传输系统包括振荡电路和连接到振荡电路的多个节点，并且每个节点至少包括一个内部逻辑电路。每个节点输出指示时钟信号相位的相位参考信号，由在节点内部提供的内部逻辑电路处理的数据。该系统还包括与时钟信号同步的表示数据传送结束的传送结束信号和连接到多个节点中的每一个的相位参考信号总线，连接到多个节点中的每一个的数据总线，用于发送数据和连接到多个节点中的每一个的传送结束信号总线，用于发送传送结束信号。多个节点的发送节点包括发送单元，用于将发送方节点本身发送到相位参考信号总线上的相位参考信号延迟地发送到多个节点的接收器节点，同时同时发送传送结束信号而接收机节点至少包括一个选择单元，用于将接收的相位参考信号转换为相位信息，从而选择具有由接收器节点接收的时钟信号的预定相位的时钟信号，以及用于接收的接收单元来自发送方节点的数据通过使用选定的时钟信号。

5. 发明授权

US06600790B1 Gap-coupling bus system 有权
标题翻译：间隙耦合总线系统
公开(公告)号：US06600790B1
公开(公告)日：2003-07-29
申请号：US09297359
申请日：1999-04-30
申请人： Masaya Umemura , Hideki Osaka
发明人： Masaya Umemura , Hideki Osaka
IPC分类号： H04B300
CPC分类号： G06F13/4072 , H05K1/0228 , H05K1/023 , H05K1/0245 , H05K2201/09263 , H05K2201/097 , H05K2201/10022
摘要： There is provided a gap coupling type bus system, which makes it possible to mutually transfer data between all the modules connected to the bus. The gap coupling type bus system comprises for at least three modules, each module being provided with at least one sending/receiving circuit for sending and receiving a signal: at least three signal lines (21-26) respectively connected to the at least three modules (11-16); and terminating resistors (31-36) connected to respective signal lines at the other ends of the signal lines, each terminating resistor having generally same value as characteristic impedance of the signal line. Those at least three signal lines (21-26) have portions (1-2, 1-3, 2-3, . . . ) laid in parallel with one another with a predetermined gap, correspondingly to every combination of different two modules out of those at least three modules (11-16).
摘要翻译：提供了一种间隙耦合型总线系统，这使得可以在连接到总线的所有模块之间相互传送数据。间隙耦合型总线系统包括至少三个模块，每个模块设置有至少一个用于发送和接收信号的发送/接收电路：至少三个信号线（21-26），分别连接到至少三个模块（11-16）; 以及连接到信号线的另一端的相应信号线的端接电阻器（31-36），每个终端电阻器具有与信号线的特征阻抗大致相同的值。那些至少三条信号线（21-26）具有以预定间隙彼此平行放置的部分（1-2,1-3,3-3 ...），对应于不同的两个模块的每个组合至少有三个模块（11-16）。

6. 发明授权

US5462442A Module for information processing apparatus using stacked printed circuit boards and connector for stacking printed circuit boards 失效
标题翻译：用于堆叠印刷电路板的信息处理装置和用于堆叠印刷电路板的连接器的模块
公开(公告)号：US5462442A
公开(公告)日：1995-10-31
申请号：US197841
申请日：1994-02-17
申请人： Masaya Umemura , Toshihiko Ogura , Hideki Osaka , Masatsugu Shinozaki
发明人： Masaya Umemura , Toshihiko Ogura , Hideki Osaka , Masatsugu Shinozaki
IPC分类号： H01R24/00 , H01R31/06 , H05K1/14 , H05K7/14 , H05K1/00
CPC分类号： H01R23/68 , H05K1/144 , H05K7/1441 , H01R12/722
摘要： In a connector having a plurality of first contact groups arranged in a predetermined pattern, conductors whose one ends are connected to the first contact groups, and a plurality of second contact groups arranged in a pattern corresponding to the pattern of the first contact groups, the conductors for connecting the first contact groups and the second contact groups cause portions of the first contact groups to be connected to the second contact groups at different positions within the above-described pattern. Accordingly, even when the contacts of the same sort of signal lines having one-to-one correspondence are allocated to the contact conductors located at the same positions within the boards for constituting the respective modules, the one-to-one correspondence can be maintained, and thus the printed-circuit boards of the modules can be commonly utilized.
摘要翻译：在具有以预定图案布置的多个第一接触组的连接器中，其一端连接到第一接触组的导体和以与第一接触组的图案对应的图案布置的多个第二接触组，用于连接第一接触组和第二接触组的导体使得第一接触组的部分在上述图案中的不同位置处连接到第二接触组。因此，即使将具有一一对应的相同种类的信号线的触点分配给位于用于构成各个模块的板内的相同位置的接触导体，也可以保持一一对应，因此可以通常使用模块的印刷电路板。

7. 发明申请

US20070197182A1 Radio equipment 失效
公开(公告)号：US20070197182A1
公开(公告)日：2007-08-23
申请号：US11785127
申请日：2007-04-16
申请人： Masaya Umemura , Yukihide Inagaki , Isao Takita , Tsutomu Hara
发明人： Masaya Umemura , Yukihide Inagaki , Isao Takita , Tsutomu Hara
IPC分类号： H04B1/06
CPC分类号： H04B1/40 , H04B1/109 , H04B1/52
摘要： A radio equipment, wherein an attenuator (10) is inserted between antennas (91, 92) and a radio module (2), and output and input sensitivities are raised and lowered simultaneously so as to keep the balance of a radio covering range with an input receiver coverage at a constant, and the antenna (91) and the antenna (92) with attenuator are switched over by a switch (8) to increase and decrease the radio coverage range and input receiver coverage while keeping the balance of the dynamic radio coverage range with the input receiver coverage.

8. 发明申请

US20050101360A1 Radio equipment 失效
标题翻译：无线电设备
公开(公告)号：US20050101360A1
公开(公告)日：2005-05-12
申请号：US10399679
申请日：2001-10-19
申请人： Masaya Umemura , Yukihide Inagaki , Isao Takita , Tsutomu Hara
发明人： Masaya Umemura , Yukihide Inagaki , Isao Takita , Tsutomu Hara
IPC分类号： H04B1/10 , H04B1/38 , H04B1/3822 , H04B1/44 , H03C7/02 , H04B1/02 , H04B7/02
CPC分类号： H04B1/40 , H04B1/109 , H04B1/52
摘要： A radio equipment, wherein an attenuator (10) is inserted between antennas (91, 92) and a radio module (2), and output and input sensitivities are raised and lowered simultaneously so as to keep the balance of a radio covering range with an input receiver coverage at a constant, and the antenna (91) and the antenna (92) with attenuator are switched over by a switch (8) to increase and decrease the radio coverage range and input receiver coverage while keeping the balance of the dynamic radio coverage range with the input receiver coverage.
摘要翻译：一种无线电设备，其中在天线（91,92）和无线电模块（2）之间插入衰减器（10），并且输出和输入灵敏度被同时升高和降低，以便将无线电覆盖范围的平衡保持为以恒定的输入接收机覆盖，并且具有衰减器的天线（91）和天线（92）由开关（8）切换，以增加和减少无线电覆盖范围并输入接收机覆盖，同时保持动态无线电的平衡覆盖范围与输入接收机覆盖范围。

9. 发明申请

US20050031092A1 Telephone communication system 失效
标题翻译：电话通讯系统
公开(公告)号：US20050031092A1
公开(公告)日：2005-02-10
申请号：US10651258
申请日：2003-08-29
申请人： Masaya Umemura , Takeo Tomokane , Kazushige Hiroi
发明人： Masaya Umemura , Takeo Tomokane , Kazushige Hiroi
IPC分类号： H04B7/24 , H04M11/00 , H04N7/14 , H04Q7/38
CPC分类号： H04N7/147 , H04M3/42263 , H04M3/58 , H04M2201/20 , H04M2203/2094 , H04N7/142
摘要： A video-phone call with a portable video-phone terminal is enabled for a cellular phone which has not video-phone service provided, by making use of cameras and display devices placed on the street. For a video-phone call to a portable video-phone terminal, a media converter in a service center distributes data so as to send video data to a public communication terminal on the street, and voice data to a cellular phone without video recording/reproducing capability. A call agent in a service center issues an ID in response to a request from the cellular phone without video recording/reproducing capability on voice call. This ID may be received by a service center via a detector such as a sensor deployed on the street, to provide a video-phone service by using a public communication terminal on the street in the vicinity of the detector.
摘要翻译：通过使用放置在街道上的相机和显示设备，可以为没有提供视频电话服务的蜂窝电话启用具有便携式视频电话终端的视频电话。对于对便携式视频电话终端的视频电话呼叫，服务中心的媒体转换器分配数据，以将视频数据发送到街道上的公共通信终端，并将语音数据发送到蜂窝电话而不进行视频记录/再现能力。响应于来自蜂窝电话的请求而在语音呼叫中没有视频记录/再现能力的情况下，服务中心的呼叫代理发出ID。该ID可以由服务中心经由诸如部署在街道上的传感器的检测器接收，以通过使用在检测器附近的街道上的公共通信终端来提供视频电话服务。

10. 发明授权

US06425037B1 Information processing system, bus arbiter, and bus controlling method 有权
标题翻译：信息处理系统，总线仲裁器和总线控制方法
公开(公告)号：US06425037B1
公开(公告)日：2002-07-23
申请号：US09407064
申请日：1999-09-28
申请人： Nobukazu Kondo , Koichi Okazawa , Yukihiro Seki , Ryuichi Hattori , Masaya Umemura , Shigemi Adachi , Kouichi Nakai , Takashi Moriyama
发明人： Nobukazu Kondo , Koichi Okazawa , Yukihiro Seki , Ryuichi Hattori , Masaya Umemura , Shigemi Adachi , Kouichi Nakai , Takashi Moriyama
IPC分类号： G06F1300
CPC分类号： G06F13/364
摘要： The present invention provides a means for preventing execution of a transaction such as main storage access from obstruction by bus competition with low-speed IO access and improving the bus occupation efficiency. The present invention includes a first bus, a second bus, a plurality of modules connected to both buses, a bus conversion means for performing protocol conversion of information between both buses, a bus arbiter for arbitrating a bus occupation right request of a bus master, and a storage means for storing access data up to a predetermined amount when the access destination is a predetermined module. Each bus master outputs access destination information and when the bus arbiter judges that one of the bus masters issues a bus occupation right request when it performs an access operation, the bus arbiter refers to the access destination information and the data storage status of the storage means and decides whether or not to give a bus occupation right to the bus master.
摘要翻译：本发明提供了一种用于防止诸如通过具有低速IO接入的总线竞争阻塞的主存储访问的事务的执行并提高总线占用效率的手段。本发明包括第一总线，第二总线，多个连接到两个总线的模块，用于在两个总线之间执行信息的协议转换的总线转换装置，用于仲裁总线主机的总线占用权请求的总线仲裁器，以及用于当存储访问数据达到预定量时存储访问数据的存储装置访问目的地是预定模块。每个总线主机输出接入目的地信息，当总线仲裁器在执行访问操作时判断其中一个总线主机发出总线占用权请求时，总线仲裁器参考存取装置的访问目的地信息和数据存储状态并决定是否给予巴士总线职业权。

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