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    • 5. 发明授权
    • Hardware execution driven application level derating calculation for soft error rate analysis
    • 软件错误率分析的硬件执行驱动应用级降额计算
    • US08949101B2
    • 2015-02-03
    • US13271827
    • 2011-10-12
    • Pradip BoseMeeta S. GuptaPrabhakar N. KudvaDaniel A. Prener
    • Pradip BoseMeeta S. GuptaPrabhakar N. KudvaDaniel A. Prener
    • G01R31/3181G06F17/50G01R31/3183
    • G01R31/31816G01R31/318357G06F17/5022
    • Mechanisms are provided for predicting effects of soft errors on an integrated circuit device design. A data processing system is configured to implement a unified derating tool that includes a machine derating front-end engine used to generate machine derating information, and an application derating front-end engine used to generate application derating information, for the integrated circuit device design. The machine derating front-end engine executes a simulation of the integrated circuit device design to generate the machine derating information. The application derating front-end engine executes an application workload on existing hardware similar in architecture to the integrated circuit device design and injects a fault into the existing hardware during execution of the application workload to generate application derating information. The machine derating information is combined with the application derating information to generate at least one soft error rate value for the integrated circuit device design.
    • 提供了用于预测软错误对集成电路器件设计的影响的机制。 数据处理系统被配置为实现统一的降额工具,其包括用于生成机器降额信息的机器降额前端引擎和用于生成应用降额信息的应用降级前端引擎用于集成电路器件设计。 机器降额前端引擎执行集成电路设备设计的仿真以生成机器降额信息。 应用降级前端引擎在架构上与集成电路设备设计类似的现有硬件上执行应用程序工作负载,并在执行应用程序工作负载期间将故障注入到现有硬件中,以生成应用程序降级信息。 机器降额信息与应用降级信息组合以产生用于集成电路设备设计的至少一个软错误率值。
    • 9. 发明申请
    • EMBEDDED TRANSIENT SCANNING SYSTEM APPARATUS AND METHODOLOGY
    • 嵌入式瞬态扫描系统设备和方法
    • US20130132007A1
    • 2013-05-23
    • US13664563
    • 2012-10-31
    • Pragma Design, Inc.
    • Jeffrey C. Dunnihoo
    • G01R31/28
    • G01R31/2879G01R31/002G01R31/26G01R31/2884G01R31/31816G06F17/40G06F19/00
    • Systems and methods for scanning and characterizing an integrated circuit for transient events. Embedded apparatus can detect transient events that may be incident on the integrated circuit, and moreover, identify particular nodes of the integrated circuit that are affected by the transient event. Additionally, the integrated circuit can be characterized by applying known transient pulses of varying severity to selected nodes of the integrated circuit, detecting the severity levels at which the selected nodes can fail, and storing indications pertaining to pulse severity at which selected nodes can fail. Moreover, based on the characterization, targeted protection mechanisms can be provided for nodes that are characterized as being susceptible.
    • 用于扫描和表征瞬态事件的集成电路的系统和方法。 嵌入式设备可以检测可能入射到集成电路上的瞬态事件,此外,识别受瞬态事件影响的集成电路的特定节点。 此外,集成电路的特征可以在于,对集成电路的选定节点应用不同严重程度的已知瞬态脉冲,检测所选节点可能发生故障的严重性级别,以及存储所选节点可能失败的脉冲严重性的指示。 此外,基于表征,可以为表征为易感的节点提供目标保护机制。