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    • 2. 发明授权
    • Bus system, printed circuit board, signal transmission line, series
circuit and memory module
    • 总线系统,印刷电路板,信号传输线,串联电路和内存模块
    • US6125419A
    • 2000-09-26
    • US874721
    • 1997-06-13
    • Masaya UmemuraHideki OsakaToshitsugu Takekuma
    • Masaya UmemuraHideki OsakaToshitsugu Takekuma
    • G06F13/40G06F13/00
    • G06F13/4086
    • There are provided plural synchronous RAMs, a memory controller, a bus for inputting the signal output from the memory controller 1a to the synchronous RAMs, and a bus for inputting the signals output from the synchronous RAMs to the memory controller. Each of the buses has a main line and two stub lines connected to the trunk like. Each of the synchronous RAMs is connected to the corresponding stub line so that the sum of the bus length of the bus between the synchronous RAM and the memory controller and the bus length of the bus between the synchronous RAM and the memory controller is substantially constant among all of said synchronous RAMs. Therefore, the signal transmission time between the bus master and the plural bus slaves can be shortened without increasing the number of pins of the bus master while keeping the signal transmission time substantially constant among the plural bus slaves.
    • 提供了多个同步RAM,存储器控制器,用于将从存储器控制器1a输出的信号输入到同步RAM的总线,以及用于将从同步RAM输出的信号输入到存储器控制器的总线。 每条公交车都有一条主干线和两根短线连接到树干上。 每个同步RAM连接到相应的存根线,使得同步RAM和存储器控制器之间的总线总线长度与同步RAM与存储器控制器之间的总线长度之和基本恒定 所有的同步RAM。 因此,在多个总线从站之间保持信号传输时间基本恒定的同时,可以缩短总线主机与多个总线从站之间的信号传输时间,而不增加总线主机的引脚数。
    • 3. 发明授权
    • Gap-coupling bus system
    • 间隙耦合总线系统
    • US06600790B1
    • 2003-07-29
    • US09297359
    • 1999-04-30
    • Masaya UmemuraHideki Osaka
    • Masaya UmemuraHideki Osaka
    • H04B300
    • G06F13/4072H05K1/0228H05K1/023H05K1/0245H05K2201/09263H05K2201/097H05K2201/10022
    • There is provided a gap coupling type bus system, which makes it possible to mutually transfer data between all the modules connected to the bus. The gap coupling type bus system comprises for at least three modules, each module being provided with at least one sending/receiving circuit for sending and receiving a signal: at least three signal lines (21-26) respectively connected to the at least three modules (11-16); and terminating resistors (31-36) connected to respective signal lines at the other ends of the signal lines, each terminating resistor having generally same value as characteristic impedance of the signal line. Those at least three signal lines (21-26) have portions (1-2, 1-3, 2-3, . . . ) laid in parallel with one another with a predetermined gap, correspondingly to every combination of different two modules out of those at least three modules (11-16).
    • 提供了一种间隙耦合型总线系统,这使得可以在连接到总线的所有模块之间相互传送数据。 间隙耦合型总线系统包括至少三个模块,每个模块设置有至少一个用于发送和接收信号的发送/接收电路:至少三个信号线(21-26),分别连接到至少三个模块 (11-16); 以及连接到信号线的另一端的相应信号线的端接电阻器(31-36),每个终端电阻器具有与信号线的特征阻抗大致相同的值。 那些至少三条信号线(21-26)具有以预定间隙彼此平行放置的部分(1-2,1-3,3-3 ...),对应于不同的两个模块的每个组合 至少有三个模块(11-16)。
    • 4. 发明授权
    • Source-clock-synchronized memory system and memory unit
    • 源时钟同步存储器系统和存储单元
    • US06034878A
    • 2000-03-07
    • US992210
    • 1997-12-16
    • Hideki OsakaMasaya UmemuraAkira YamagiwaToshitsugu Takekuma
    • Hideki OsakaMasaya UmemuraAkira YamagiwaToshitsugu Takekuma
    • G06F12/06G06F1/10G06F12/00G06F13/16G11C5/00G11C11/401G11C11/407G11C13/00
    • G06F13/1684
    • A source-clock-synchronized memory system having a large data storage capacity per memory bank and a high mounting density. The invention includes a memory unit having a first memory riser board B1 mounted on a base board through a first connector C1 and a second memory riser board B2 mounted on the base board BB through a second connector C2. The first memory riser board has a plurality of first memory modules mounted on the front surface thereof and the second memory riser board has a plurality of second memory modules mounted on the front surface thereof. The first and second memory riser boards are arranged in such a way that the back surface of the first memory riser board faces the back surface of the second memory riser board. The invention further includes a board linking connector for connecting signal lines on the first memory riser board to corresponding signal lines on the second memory riser board.
    • 源时钟同步的存储器系统,每个存储体具有大的数据存储容量和高的安装密度。 本发明包括具有通过第一连接器C1安装在基板上的第一存储器提升板B1和通过第二连接器C2安装在基板BB上的第二存储器提升板B2的存储单元。 第一存储器提升板具有安装在其前表面上的多个第一存储器模块,并且第二存储器提升板具有安装在其前表面上的多个第二存储器模块。 第一和第二存储器提升板被布置成使得第一存储器提升板的后表面面向第二存储器提升板的后表面。 本发明还包括板连接连接器,用于将第一存储器提升板上的信号线连接到第二存储器提升板上的相应信号线。