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1. 发明授权

US06509687B1 Metal/dielectric laminate with electrodes and process thereof 失效
标题翻译：具有电极的金属/电介质层压板及其工艺
公开(公告)号：US06509687B1
公开(公告)日：2003-01-21
申请号：US09450530
申请日：1999-11-30
申请人： Govindarajan Natarajan , Raschid J. Bezama , John U. Knickerbocker , Robert W. Pasco
发明人： Govindarajan Natarajan , Raschid J. Bezama , John U. Knickerbocker , Robert W. Pasco
IPC分类号： H01J2964
CPC分类号： H01J29/467 , H01J31/127
摘要： The present invention relates generally to a new electrode forming metal/magnetic-ceramic laminate with through-holes and process thereof. More particularly, the invention encompasses a new process for fabrication of a large area ceramic laminate magnet with a significant number of holes, integrated metal plate(s) and co-sintered electrodes for electron and electron beam control. The present invention also relates to a magnetic matrix display (MMD), and electron beam source, and methods of manufacture thereof.
摘要翻译：本发明一般涉及具有通孔的新型电极形成金属/磁陶瓷层压体及其工艺。更具体地，本发明包括用于制造具有大量孔的大面积陶瓷层压体磁体的新方法，用于电子和电子束控制的集成金属板和共烧结电极。本发明还涉及磁矩阵显示器（MMD）和电子束源，及其制造方法。

2. 发明授权

US5541005A Large ceramic article and method of manufacturing 失效
标题翻译：大型陶瓷制品及其制造方法
公开(公告)号：US5541005A
公开(公告)日：1996-07-30
申请号：US438825
申请日：1995-05-11
申请人： Raschid J. Bezama , Jon A. Casey , Mario E. Ecker , Shaji Farooq , Irene S. Frantz , Katherine G. Frase , David H. Gabriels , Lester W. Herron , John U. Knickerbocker , Sarah H. Knickerbocker , Govindarajan Natarajan , John Thomson , Yee-Ming Ting , Sharon L. Tracy , Robert M. Troncillito , Vivek M. Sura , Donald R. Wall , Giai V. Yen
发明人： Raschid J. Bezama , Jon A. Casey , Mario E. Ecker , Shaji Farooq , Irene S. Frantz , Katherine G. Frase , David H. Gabriels , Lester W. Herron , John U. Knickerbocker , Sarah H. Knickerbocker , Govindarajan Natarajan , John Thomson , Yee-Ming Ting , Sharon L. Tracy , Robert M. Troncillito , Vivek M. Sura , Donald R. Wall , Giai V. Yen
IPC分类号： B28B11/02 , H01L21/48 , H01L21/768 , H01L23/15 , H01L23/522 , H05K1/03 , H05K1/14 , H05K3/46 , B22F3/105
CPC分类号： H05K1/142 , H01L21/4807 , H01L23/15 , H05K3/46 , H05K3/4629 , H01L2924/0002 , H01L2924/09701 , H05K1/0306 , H05K2201/09972 , Y10T428/12049 , Y10T428/12146 , Y10T428/16 , Y10T428/163 , Y10T428/166 , Y10T428/192
摘要： A large ceramic substrate article for electronic applications including at least one layer of sintered ceramic material, the layer including a plurality of greensheet segments of ceramic material joined edge to edge. Also disclosed is a method of fabricating a large ceramic greensheet article as well as a large ceramic substrate article.
摘要翻译：一种用于电子应用的大型陶瓷衬底制品，包括至少一层烧结陶瓷材料，该层包括多个边缘到边缘连接的陶瓷材料毛坯块。还公开了一种制造大型陶瓷毛坯制品的方法以及大型陶瓷基片制品。

3. 发明授权

US06955777B2 Method of forming a plate for dispensing chemicals 有权
标题翻译：形成用于分配化学品的板的方法
公开(公告)号：US06955777B2
公开(公告)日：2005-10-18
申请号：US10338093
申请日：2003-01-07
申请人： Govindarajan Natarajan , Umar Ahmad , Raschid J. Bezama , James N. Humenik , John U. Knickerbocker , Rao V. Vallabhaneni
发明人： Govindarajan Natarajan , Umar Ahmad , Raschid J. Bezama , James N. Humenik , John U. Knickerbocker , Rao V. Vallabhaneni
IPC分类号： B01L3/00 , B29C65/00 , B32B18/00 , C03B29/00 , C04B33/34 , C04B37/00
CPC分类号： B32B18/00 , B01J2219/00286 , B01J2219/00317 , B01L3/502707 , B01L3/5085 , B01L2200/12 , B01L2300/0816 , B01L2300/0819 , B01L2300/0887 , B01L2300/12 , B81B2203/0338 , B81B2203/0353 , B81C1/00119 , C04B35/645 , C04B2235/6567 , C04B2237/341 , C04B2237/343 , C04B2237/366 , C04B2237/62 , C04B2237/704
摘要： A plate for use in mixing and testing materials in the pharmaceutical industry is formed by a method in which apertures in a set of greensheets are formed by a material removal process, at least some of the apertures being filled with a fugitive material that escapes during sintering.
摘要翻译：在制药工业中用于混合和测试材料的板材是通过一种方法形成的，其中通过材料去除工艺形成一组绿叶片中的孔，至少一些孔被填充有在烧结过程中逸出的逃逸材料。

4. 发明授权

US5538582A Method for forming cavities without using an insert 失效
标题翻译：在不使用插入件的情况下形成空腔的方法
公开(公告)号：US5538582A
公开(公告)日：1996-07-23
申请号：US305620
申请日：1994-09-14
申请人： Govindarajan Natarajan , Raschid J. Bezama , John U. Knickerbocker
发明人： Govindarajan Natarajan , Raschid J. Bezama , John U. Knickerbocker
IPC分类号： B32B18/00 , B23B35/00 , B28B11/02 , H05K3/46 , B32B31/04 , B32B31/20
CPC分类号： B32B37/0023 , B32B37/10 , B32B37/26 , B32B2315/02
摘要： The present invention relates generally to a new method for forming cavities without using an insert. More particularly, the invention encompasses method for fabricating cavities in MLC (multi-layer ceramic) without using inserts.
摘要翻译：本发明一般涉及一种用于在不使用插入件的情况下形成空腔的新方法。更具体地说，本发明包括在不使用插入件的情况下在MLC（多层陶瓷）中制造空腔的方法。

5. 发明授权

US5439636A Large ceramic articles and method of manufacturing 失效
标题翻译：大型陶瓷制品及其制造方法
公开(公告)号：US5439636A
公开(公告)日：1995-08-08
申请号：US836675
申请日：1992-02-18
申请人： Raschid J. Bezama , Jon A. Casey , Mario E. Ecker , Shaji Farooq , Irene S. Frantz , Katharine G. Frase , David H. Gabriels , Lester W. Herron , John U. Knickerbocker , Sara H. Knickerbocker , Govindarajan Natarajan , John Thomson , Yee-Ming Ting , Sharon L. Tracy , Robert M. Troncillito , Vivek M. Sura , Donald R. Wall , Giai V. Yen
发明人： Raschid J. Bezama , Jon A. Casey , Mario E. Ecker , Shaji Farooq , Irene S. Frantz , Katharine G. Frase , David H. Gabriels , Lester W. Herron , John U. Knickerbocker , Sara H. Knickerbocker , Govindarajan Natarajan , John Thomson , Yee-Ming Ting , Sharon L. Tracy , Robert M. Troncillito , Vivek M. Sura , Donald R. Wall , Giai V. Yen
IPC分类号： B28B11/02 , H01L21/48 , H01L21/768 , H01L23/15 , H01L23/522 , H05K1/03 , H05K1/14 , H05K3/46 , B22F3/00
CPC分类号： H05K1/142 , H01L21/4807 , H01L23/15 , H05K3/46 , H05K3/4629 , H01L2924/0002 , H01L2924/09701 , H05K1/0306 , H05K2201/09972 , Y10T428/12049 , Y10T428/12146 , Y10T428/16 , Y10T428/163 , Y10T428/166 , Y10T428/192
摘要： A large ceramic substrate article for electronic applications including at least one layer of sintered ceramic material, the layer including a plurality of greensheet segments of ceramic material joined edge to edge. Also disclosed is a method of fabricating a large ceramic greensheet article as well as a large ceramic substrate article.
摘要翻译：一种用于电子应用的大型陶瓷衬底制品，包括至少一层烧结陶瓷材料，该层包括多个边缘到边缘连接的陶瓷材料毛坯块。还公开了一种制造大型陶瓷毛坯制品的方法以及大型陶瓷基片制品。

6. 发明授权

US06395337B1 Substrate with ceramic coating for camber modification and method for making 失效
标题翻译：具有陶瓷涂层的基体用于外观修改和制造方法
公开(公告)号：US06395337B1
公开(公告)日：2002-05-28
申请号：US09364845
申请日：1999-07-30
申请人： Raschid J. Bezama , Govindarajan Natarajan , Robert W. Pasco
发明人： Raschid J. Bezama , Govindarajan Natarajan , Robert W. Pasco
IPC分类号： B05D302
CPC分类号： B32B18/00 , C04B35/10 , C04B35/581 , C04B41/009 , C04B41/5022 , C04B41/86 , C04B2111/00844 , C04B2237/064 , C04B2237/341 , C04B2237/343 , C04B2237/366 , C04B2237/564 , H01L21/481 , H05K1/0306 , H05K3/4629 , C04B41/4539 , C04B41/4578
摘要： A multilayer ceramic substrate contains a ceramic coating which is different in composition than the main body of the multilayer ceramic substrate to control camber of the multilayer ceramic substrate during sintering. The primary component of the ceramic coating is a secondary component of the main body of the multilayer ceramic substrate.
摘要翻译：多层陶瓷基板包含与多层陶瓷基板的主体不同的陶瓷涂层，以在烧结期间控制多层陶瓷基板的弯度。陶瓷涂层的主要成分是多层陶瓷基体的主体的次要成分。

7. 发明授权

US06745932B2 Low strain chip removal apparatus 有权
标题翻译：低应变片去除装置
公开(公告)号：US06745932B2
公开(公告)日：2004-06-08
申请号：US10235008
申请日：2002-09-03
申请人： Raschid J. Bezama , Govindarajan Natarajan , Robert W. Pasco
发明人： Raschid J. Bezama , Govindarajan Natarajan , Robert W. Pasco
IPC分类号： B23K1018
CPC分类号： B23K1/018 , B23K2101/40
摘要： A method and structure for a chip detach apparatus and method that limits the solder ball maximum shear rate and, more particularly, that delays the application of shear force until a minimum predefined temperature is reached. The chip detach apparatus and method can be applied to chips with high solder ball counts, chips with small solder ball sizes, and chips with weak surface strength. The chip detach apparatus and method measures and accounts for variability in the electronic module manufacturing and assembly.
摘要翻译：用于限制焊球最大剪切速率的切屑分离装置和方法的方法和结构，更具体地说，延迟剪切力的施加直到达到最小预定温度。芯片分离装置和方法可以应用于具有高焊球计数的芯片，具有小焊球尺寸的芯片和具有弱表面强度的芯片。芯片分离装置和方法测量并考虑了电子模块制造和组装中的变化。

8. 发明授权

US06459039B1 Method and apparatus to manufacture an electronic package with direct wiring pattern 失效
标题翻译：制造具有直接布线图案的电子封装的方法和装置
公开(公告)号：US06459039B1
公开(公告)日：2002-10-01
申请号：US09597906
申请日：2000-06-19
申请人： Raschid J. Bezama , Govindarajan Natarajan , Robert W. Pasco
发明人： Raschid J. Bezama , Govindarajan Natarajan , Robert W. Pasco
IPC分类号： H05K102
CPC分类号： H01L23/49827 , H01L2224/16 , H01L2924/00014 , H01L2924/01079 , H01L2924/15174 , H01L2924/15311 , H01L2924/3011 , H05K1/113 , H05K3/3436 , H05K2201/09836 , H05K2201/10378 , Y02P70/613 , H01L2224/0401
摘要： An electronic package assembly for electrical interconnection between two electronic modules having differing conductive array parameters is disclosed. The electronic package assembly includes two electronic modules, providing between the two electronic modules an interposer having a top surface and a bottom surface; a first set of conductive arrays having a first conductive array parameter on the top surface, and a second set of conductive arrays having a second conductive array parameter on the bottom surface, the second conductive array and the first conductive array having differing parameters. A plurality of conductors traverses a thickness of the interposer of the electronic package assembly, with the conductors including a conductive material optionally coated with a dielectric material, the conductors having a first end at the first conductive arrays and a second end at the second conductive arrays, whereby the conductors connecting the first and second conductive arrays therein are adapted to spatially transform the differing parameters to provide an electrical interconnection. A conductive matrix surrounds the conductors of the interposer of the electronic package assembly. The first set of conductive arrays includes the same conductive array parameters as a first electronic module and the second set of conductive arrays includes the same conductive array parameters as a second electronic module.
摘要翻译：公开了一种用于具有不同导电阵列参数的两个电子模块之间的电互连的电子封装组件。电子封装组件包括两个电子模块，在两个电子模块之间提供具有顶表面和底表面的插入件; 具有在顶表面上具有第一导电阵列参数的第一组导电阵列和在底表面上具有第二导电阵列参数的第二组导电阵列，所述第二导电阵列和第一导电阵列具有不同的参数。多个导体横穿电子封装组件的插入件的厚度，其中导体包括任选涂覆有电介质材料的导电材料，导体在第一导电阵列处具有第一端，在第二导电阵列处具有第二端由此连接其中的第一和第二导电阵列的导体适于空间转换不同的参数以提供电互连。导电矩阵围绕电子封装组件的插入件的导体。第一组导电阵列包括与第一电子模块相同的导电阵列参数，第二组导电阵列包括与第二电子模块相同的导电阵列参数。

9. 发明授权

US06562169B2 Multi-level web structure in use for thin sheet processing 失效
标题翻译：用于薄板加工的多层网状结构
公开(公告)号：US06562169B2
公开(公告)日：2003-05-13
申请号：US09765027
申请日：2001-01-17
申请人： Govindarajan Natarajan , Raschid J. Bezama , Jon A. Casey , Amy C. Flack , Robert W. Pasco , Arnold W. Terpening , Renee L. Weisman
发明人： Govindarajan Natarajan , Raschid J. Bezama , Jon A. Casey , Amy C. Flack , Robert W. Pasco , Arnold W. Terpening , Renee L. Weisman
IPC分类号： B32B3118
CPC分类号： B32B18/00 , C04B2235/6562 , C04B2237/068 , C04B2237/122 , C04B2237/123 , C04B2237/366 , H05K1/0306 , H05K3/4611 , H05K3/4629 , Y10T156/1056 , Y10T156/1057
摘要： A method of processing greensheets, wherein the following steps are performed: a) providing a greensheet having a width, length, thickness, a first side and a second side; b) bonding to the first side of the greensheet at least one strip, wherein the strip lies in a first plane; c) bonding to the second side of the green sheet at least one strip, wherein the strip lies in a second plane; d) processing the greensheet; and e) removing the strips from the processed greensheet.
摘要翻译：一种处理毛坯的方法，其中执行以下步骤：a）提供具有宽度，长度，厚度，第一侧面和第二侧面的毛坯; b）将至少一个条带结合到毛坯的第一侧，其中所述条带位于第一平面中; c）将至少一个条带连接到所述生片的第二侧，其中所述条位于第二平面中; d）处理所述毛坯; 从处理过的毛坯上去除条带。

10. 发明授权

US06332782B1 Spatial transformation interposer for electronic packaging 失效
标题翻译：电子封装空间转换插件
公开(公告)号：US06332782B1
公开(公告)日：2001-12-25
申请号：US09597919
申请日：2000-06-19
申请人： Raschid J. Bezama , Govindarajan Natarajan , Robert W. Pasco
发明人： Raschid J. Bezama , Govindarajan Natarajan , Robert W. Pasco
IPC分类号： H01R1200
CPC分类号： H05K1/141 , H01L2224/16225 , H01L2924/15174 , H01L2924/15311 , H01R13/24 , H05K1/113 , H05K3/3436 , H05K3/368 , H05K7/1061 , H05K2201/049 , H05K2201/09836 , H05K2201/10378 , H05K2201/10734
摘要： An interconnect substrate structure for electrical interconnection between two electronic modules having differing conductive array parameters. The interconnect structure comprises an interposer having a top surface and a bottom surface; a first set of conductive arrays having a first conductive array parameter on the top surface, and a second set of conductive arrays having a second conductive array parameter on the bottom surface, the second conductive array and the first conductive array having differing parameters. A plurality of conductors traverses a thickness of the interposer, with the conductors comprising a conductive material optionally coated with a dielectric material, the conductors having a first end at the first conductive arrays and a second end at the second conductive arrays, whereby the conductors connecting the first and second conductive arrays therein are adapted to spatially transform the differing parameters to provide an electrical interconnection. A conductive matrix surrounds the conductors. The first set of conductive arrays comprise the same conductive array parameters as a first electronic module and the second set of conductive arrays comprise the same conductive array parameters as a second electronic module.
摘要翻译：一种互连衬底结构，用于具有不同导电阵列参数的两个电子模块之间的电互连。互连结构包括具有顶表面和底表面的插入件; 具有在顶表面上具有第一导电阵列参数的第一组导电阵列和在底表面上具有第二导电阵列参数的第二组导电阵列，所述第二导电阵列和第一导电阵列具有不同的参数。多个导体横穿插入件的厚度，导体包括任选地涂覆有电介质材料的导电材料，导体在第一导电阵列处具有第一端，在第二导电阵列处具有第二端，由此导体连接其中的第一和第二导电阵列适于空间转换不同的参数以提供电互连。导电矩阵围绕导体。第一组导电阵列包括与第一电子模块相同的导电阵列参数，并且第二组导电阵列包括与第二电子模块相同的导电阵列参数。

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