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1. 发明授权

US5541005A Large ceramic article and method of manufacturing 失效
标题翻译：大型陶瓷制品及其制造方法
公开(公告)号：US5541005A
公开(公告)日：1996-07-30
申请号：US438825
申请日：1995-05-11
申请人： Raschid J. Bezama , Jon A. Casey , Mario E. Ecker , Shaji Farooq , Irene S. Frantz , Katherine G. Frase , David H. Gabriels , Lester W. Herron , John U. Knickerbocker , Sarah H. Knickerbocker , Govindarajan Natarajan , John Thomson , Yee-Ming Ting , Sharon L. Tracy , Robert M. Troncillito , Vivek M. Sura , Donald R. Wall , Giai V. Yen
发明人： Raschid J. Bezama , Jon A. Casey , Mario E. Ecker , Shaji Farooq , Irene S. Frantz , Katherine G. Frase , David H. Gabriels , Lester W. Herron , John U. Knickerbocker , Sarah H. Knickerbocker , Govindarajan Natarajan , John Thomson , Yee-Ming Ting , Sharon L. Tracy , Robert M. Troncillito , Vivek M. Sura , Donald R. Wall , Giai V. Yen
IPC分类号： B28B11/02 , H01L21/48 , H01L21/768 , H01L23/15 , H01L23/522 , H05K1/03 , H05K1/14 , H05K3/46 , B22F3/105
CPC分类号： H05K1/142 , H01L21/4807 , H01L23/15 , H05K3/46 , H05K3/4629 , H01L2924/0002 , H01L2924/09701 , H05K1/0306 , H05K2201/09972 , Y10T428/12049 , Y10T428/12146 , Y10T428/16 , Y10T428/163 , Y10T428/166 , Y10T428/192
摘要： A large ceramic substrate article for electronic applications including at least one layer of sintered ceramic material, the layer including a plurality of greensheet segments of ceramic material joined edge to edge. Also disclosed is a method of fabricating a large ceramic greensheet article as well as a large ceramic substrate article.
摘要翻译：一种用于电子应用的大型陶瓷衬底制品，包括至少一层烧结陶瓷材料，该层包括多个边缘到边缘连接的陶瓷材料毛坯块。还公开了一种制造大型陶瓷毛坯制品的方法以及大型陶瓷基片制品。

2. 发明授权

US5439636A Large ceramic articles and method of manufacturing 失效
标题翻译：大型陶瓷制品及其制造方法
公开(公告)号：US5439636A
公开(公告)日：1995-08-08
申请号：US836675
申请日：1992-02-18
申请人： Raschid J. Bezama , Jon A. Casey , Mario E. Ecker , Shaji Farooq , Irene S. Frantz , Katharine G. Frase , David H. Gabriels , Lester W. Herron , John U. Knickerbocker , Sara H. Knickerbocker , Govindarajan Natarajan , John Thomson , Yee-Ming Ting , Sharon L. Tracy , Robert M. Troncillito , Vivek M. Sura , Donald R. Wall , Giai V. Yen
发明人： Raschid J. Bezama , Jon A. Casey , Mario E. Ecker , Shaji Farooq , Irene S. Frantz , Katharine G. Frase , David H. Gabriels , Lester W. Herron , John U. Knickerbocker , Sara H. Knickerbocker , Govindarajan Natarajan , John Thomson , Yee-Ming Ting , Sharon L. Tracy , Robert M. Troncillito , Vivek M. Sura , Donald R. Wall , Giai V. Yen
IPC分类号： B28B11/02 , H01L21/48 , H01L21/768 , H01L23/15 , H01L23/522 , H05K1/03 , H05K1/14 , H05K3/46 , B22F3/00
CPC分类号： H05K1/142 , H01L21/4807 , H01L23/15 , H05K3/46 , H05K3/4629 , H01L2924/0002 , H01L2924/09701 , H05K1/0306 , H05K2201/09972 , Y10T428/12049 , Y10T428/12146 , Y10T428/16 , Y10T428/163 , Y10T428/166 , Y10T428/192
摘要： A large ceramic substrate article for electronic applications including at least one layer of sintered ceramic material, the layer including a plurality of greensheet segments of ceramic material joined edge to edge. Also disclosed is a method of fabricating a large ceramic greensheet article as well as a large ceramic substrate article.
摘要翻译：一种用于电子应用的大型陶瓷衬底制品，包括至少一层烧结陶瓷材料，该层包括多个边缘到边缘连接的陶瓷材料毛坯块。还公开了一种制造大型陶瓷毛坯制品的方法以及大型陶瓷基片制品。

3. 发明授权

US5418796A Synergistic multiple bit error correction for memory of array chips 失效
标题翻译：用于阵列芯片存储器的协同多位纠错
公开(公告)号：US5418796A
公开(公告)日：1995-05-23
申请号：US675994
申请日：1991-03-26
申请人： Donald W. Price , Yee-Ming Ting
发明人： Donald W. Price , Yee-Ming Ting
IPC分类号： G06F11/10 , G06F12/16 , H03M13/00
CPC分类号： G06F11/1028
摘要： A two-level multiple bit error correction scheme includes at the first level a memory chip with a memory error detection capability that produces a chip error signal (CES) when it detects errors in the bits leaving that chip and at the second level an off-chip ECC facility which interprets generated syndrome bits and chip error signals in order to determine which bits are bad. There are two types of codes distinguished by the absence or presence of parity bits. The use of parity bits allows for the detection of single bit errors in data read from the chip. Therefore, the CES is active only for detected multiple bit errors. Chips not using parity bits are less expensive, but the CES must be active for both single bit and multiple bit errors.
摘要翻译：两级多位错误校正方案在第一级包括具有存储器错误检测能力的存储器芯片，当存储器芯片检测到离开该芯片的位中的错误并且在第二级处产生偏移信号时产生芯片误差信号（CES）芯片ECC设备，其解释生成的校正子位和码片错误信号，以便确定哪些位是坏的。有两种类型的代码是由不存在或存在奇偶校验位来区分的。奇偶校验位的使用允许检测从芯片读取的数据中的单位错误。因此，CES只对检测到的多个位错误有效。不使用奇偶校验位的芯片成本较低，但CES必须对单位和多位错误都有效。

4. 发明授权

US4991084A N.times.M round robin order arbitrating switching matrix system 失效
标题翻译： NxM循环次序仲裁切换矩阵系统
公开(公告)号：US4991084A
公开(公告)日：1991-02-05
申请号：US152779
申请日：1988-02-05
申请人： William K. Rodiger , Jon E. Thorson , Yee-Ming Ting
发明人： William K. Rodiger , Jon E. Thorson , Yee-Ming Ting
IPC分类号： G06F15/16 , G06F9/52 , G06F13/14 , G06F13/16 , G06F15/167 , G06F15/177
CPC分类号： G06F13/1657 , G06F13/14
摘要： An N.times.M matrix adapted to couple N inputs from N processor to M basic storage modules is disclosed. The system includes arbitrators and gating means for each output responsive to request signals for simultaneously coupling data from a plurality of processors to requested basic storage modules under arbitrator control.

5. 发明授权

US5278800A Memory system and unique memory chip allowing island interlace 失效
标题翻译：内存系统和独特的内存芯片允许岛交错
公开(公告)号：US5278800A
公开(公告)日：1994-01-11
申请号：US786139
申请日：1991-10-31
申请人： Warren W. Grunbok , Billy J. Knowles , William R. Milani , Douglas R. Moran , Dale E. Pontius , Donald W. Price , Robert Tamlyn , Yee-Ming Ting , De Tran , Henry Yeh
发明人： Warren W. Grunbok , Billy J. Knowles , William R. Milani , Douglas R. Moran , Dale E. Pontius , Donald W. Price , Robert Tamlyn , Yee-Ming Ting , De Tran , Henry Yeh
IPC分类号： G06F12/06 , G06F13/16 , G11C8/12 , G11C7/00
CPC分类号： G06F12/06 , G06F13/1657 , G11C8/12
摘要： A memory system and a unique memory chip is disclosed wherein multiple islands on a chip can be separately accessed by separate island controllers whereby concurrent use of the several islands or arrays on a chip can be achieved.
摘要翻译：公开了一种存储器系统和独特的存储器芯片，其中芯片上的多个岛可以由单独的岛控制器单独访问，从而可以实现芯片上的多个岛或阵列的并发使用。

6. 发明授权

US5265232A Coherence control by data invalidation in selected processor caches without broadcasting to processor caches not having the data 失效
标题翻译：在所选处理器高速缓存中通过数据无效的一致性控制，而无需广播到不具有数据的处理器缓存
公开(公告)号：US5265232A
公开(公告)日：1993-11-23
申请号：US679900
申请日：1991-04-03
申请人： Patrick M. Gannon , Michael Ignatowski , Matthew A. Krygowski , Lishing Liu , Donald W. Price , William K. Rodiger , Gregory Salyer , Yee-Ming Ting , Michael P. Witt
发明人： Patrick M. Gannon , Michael Ignatowski , Matthew A. Krygowski , Lishing Liu , Donald W. Price , William K. Rodiger , Gregory Salyer , Yee-Ming Ting , Michael P. Witt
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/082 , G06F12/0811
摘要： A coherence directory and its methods of operation are disclosed for private processor caches in a multiple processor system to control data coherence in the system. It provides cross-invalidate (XI) controls for the assignment of exclusive and public ownership to data units in the processor caches, including required cross-invalidation of data units among the processor caches to obtain data coherence in the system in an efficient manner. The coherence directory can be used in a multiple processor system with or without any shared second level (L2) cache, shared or private. When a shared L2 cache is used to improve system access time, the coherence directory can also be used as the second level directory for the shared L2 cache and eliminate the need for any additional L2 directory(s).

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