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1. 发明授权

US06204710B1 Precision trim circuit for delay lines 失效
标题翻译：精密微调电路延时线
公开(公告)号：US06204710B1
公开(公告)日：2001-03-20
申请号：US09102730
申请日：1998-06-22
申请人： F. Erich Goetting , Paul G. Hyland , Joseph H. Hassoun
发明人： F. Erich Goetting , Paul G. Hyland , Joseph H. Hassoun
IPC分类号： H03K513
CPC分类号： H03K5/133 , H03K2005/00058 , H03K2005/00084
摘要： A precision trim circuit for a tuneable delay line is provided. The precision trim circuit provides delays greater than the base delay of the tuneable delay line. By using larger delays than conventional trim circuits, the precision trim circuit of the present invention can use components that react to process and environmental variations in the same manner as the components of the tuneable delay line. Specifically, one embodiment of the precision trim circuit comprises a first delay element providing a delay greater than or equal to the base delay of the tuneable delay line. The precision trim circuit also comprises a second delay element providing a greater delay than the first delay element. A multiplexer coupled to the first delay element and the second delay element is used to select the amount of delay provided by the precision trim circuit. Other embodiments include additional delay elements providing varying delay values.
摘要翻译：提供了一种用于可调延迟线的精密微调电路。精密微调电路提供大于可调延迟线的基本延迟的延迟。通过使用比传统的微调电路更大的延迟，本发明的精密微调电路可以以与可调延迟线的组件相同的方式使用对处理和环境变化做出反应的组件。具体地，精密微调电路的一个实施例包括提供大于或等于可调延迟线的基本延迟的延迟的第一延迟元件。精密微调电路还包括提供比第一延迟元件更大的延迟的第二延迟元件。耦合到第一延迟元件和第二延迟元件的多路复用器用于选择由精密调整电路提供的延迟量。其他实施例包括提供可变延迟值的附加延迟元件。

2. 发明授权

US06289068B1 Delay lock loop with clock phase shifter 失效
标题翻译：带时钟移相器的延时锁定环
公开(公告)号：US06289068B1
公开(公告)日：2001-09-11
申请号：US09102740
申请日：1998-06-22
申请人： Joseph H. Hassoun , F. Erich Goetting , John D. Logue
发明人： Joseph H. Hassoun , F. Erich Goetting , John D. Logue
IPC分类号： H03D324
CPC分类号： H03L7/0814 , G06F1/10 , H03L7/07
摘要： A delay lock loop uses a clock phase shifter with a delay line to synchronize a reference clock signal with a skewed clock signal. The delay line is coupled to a reference input terminal of the delay lock loop and generates a delayed clock signal that is provided to the clock phase shifter. The clock phase shifter generates one or more phase-shifted clock signals from the delayed clock signal. An output generator coupled to the delay line, the clock phase shifter, and an output terminal of the delay lock loop provides either the delayed clock signal or one of the phase-shifted clock signals as an output clock signal of the delayed lock loop. The propagation delay of the delay line is set to synchronize the reference clock signal with the skewed clock signal, which is received on a feedback input terminal of the delay lock loop. A phase detector compares the reference clock signal and the skewed clock signal to determine the appropriate propagation delay for the delay line.
摘要翻译：延迟锁定环使用具有延迟线的时钟移相器来使参考时钟信号与偏斜时钟信号同步。延迟线耦合到延迟锁定环的参考输入端，并产生提供给时钟移相器的延迟时钟信号。时钟移相器从延迟的时钟信号产生一个或多个相移时钟信号。耦合到延迟线的输出发生器，时钟移相器和延迟锁定环路的输出端子提供延迟时钟信号或相移时钟信号中的一个作为延迟锁定环路的输出时钟信号。延迟线的传播延迟被设置为使参考时钟信号与延迟锁定环路的反馈输入端上接收到的偏斜时钟信号同步。相位检测器比较参考时钟信号和偏斜时钟信号，以确定延迟线的适当传播延迟。

3. 发明授权

US06587534B2 Delay lock loop with clock phase shifter 有权
标题翻译：带时钟移相器的延时锁定环
公开(公告)号：US06587534B2
公开(公告)日：2003-07-01
申请号：US09892403
申请日：2001-06-26
申请人： Joseph H. Hassoun , F. Erich Goetting , John D. Logue
发明人： Joseph H. Hassoun , F. Erich Goetting , John D. Logue
IPC分类号： H03D324
CPC分类号： H03L7/0814 , G06F1/10 , H03L7/07
摘要： A delay lock loop uses a clock phase shifter with a delay line to synchronize a reference clock signal with a skewed clock signal. The delay line is coupled to a reference input terminal of the delay lock loop and generates a delayed clock signal that is provided to the clock phase shifter. The clock phase shifter generates one or more phase-shifted clock signals from the delayed clock signal. An output generator coupled to the delay line, the clock phase shifter, and an output terminal of the delay lock loop provides either the delayed clock signal or one of the phase-shifted clock signals as an output clock signal of the delayed lock loop. The propagation delay of the delay line is set to synchronize the reference clock signal with the skewed clock signal, which is received on a feedback input terminal of the delay lock loop. A phase detector compares the reference clock signal and the skewed clock signal to determine the appropriate propagation delay.
摘要翻译：延迟锁定环使用具有延迟线的时钟移相器来使参考时钟信号与偏斜时钟信号同步。延迟线耦合到延迟锁定环的参考输入端，并产生提供给时钟移相器的延迟时钟信号。时钟移相器从延迟的时钟信号产生一个或多个相移时钟信号。耦合到延迟线的输出发生器，时钟移相器和延迟锁定环路的输出端子提供延迟时钟信号或相移时钟信号中的一个作为延迟锁定环路的输出时钟信号。延迟线的传播延迟被设置为使参考时钟信号与延迟锁定环路的反馈输入端上接收到的偏斜时钟信号同步。相位检测器比较参考时钟信号和偏斜时钟信号以确定适当的传播延迟。

4. 发明授权

US07010014B1 Digital spread spectrum circuitry 有权
标题翻译：数字扩频电路
公开(公告)号：US07010014B1
公开(公告)日：2006-03-07
申请号：US09684528
申请日：2000-10-06
申请人： Andrew K. Percey , John D. Logue , F. Erich Goetting , Paul G. Hyland
发明人： Andrew K. Percey , John D. Logue , F. Erich Goetting , Paul G. Hyland
IPC分类号： H04B1/69 , H03D3/24 , H03L7/00 , H03L7/06
CPC分类号： H03L7/0814 , G06F1/10 , H03L7/07
摘要： The frequency of a skew clock signal is dithered around a base frequency, thereby enabling this clock signal to comply with FCC requirements for electromagnetic emissions within a specified window. Delay is introduced such that the clock signals exhibits slightly different frequencies in successive periods. For example, the frequency of a 100 MHz clock signal can be adjusted to have frequencies of approximately 98, 98.5, 99, 99.5, 100, 100.5, 101, 101.5, and 102 MHz during different periods. Because the frequencies are spread in 0.5 MHz increments, only three frequencies are included in any 1 MHz window. As a result, ⅔ of the energy of the clock signal is not included when determining whether the clock signal meets the FCC electromagnetic emission requirements. By spreading the frequencies above and below the base frequency in a regular manner, the average frequency of the clock signal becomes equal to the base frequency.
摘要翻译：偏移时钟信号的频率在基频周围抖动，从而使该时钟信号能够符合FCC在指定窗口内对电磁辐射的要求。引入延迟使得时钟信号在连续的周期中表现出稍微不同的频率。例如，100MHz时钟信号的频率可以在不同时段期间被调整为具有约98,98.5,99,99.5,100,150.5,101,101.5和102MHz的频率。由于频率以0.5 MHz为单位进行扩展，所以在1 MHz窗口中只能包含三个频率。因此，当确定时钟信号是否满足FCC电磁辐射要求时，不包括时钟信号的能量的2/3。通过以规则的方式扩展基频以上的频率，时钟信号的平均频率等于基频。

5. 发明授权

US07345507B1 Multi-product die configurable as two or more programmable integrated circuits of different logic capacities 有权
标题翻译：多产品管芯可配置为具有不同逻辑容量的两个或多个可编程集成电路
公开(公告)号：US07345507B1
公开(公告)日：2008-03-18
申请号：US11333991
申请日：2006-01-17
申请人： Steven P. Young , Trevor J. Bauer , F. Erich Goetting , P. Hugo Lamarche , Patrick J. McGuire , Kwansuhk Oh , Raymond C. Pang , Bruce E. Talley , Paul Ying-Fung Wu
发明人： Steven P. Young , Trevor J. Bauer , F. Erich Goetting , P. Hugo Lamarche , Patrick J. McGuire , Kwansuhk Oh , Raymond C. Pang , Bruce E. Talley , Paul Ying-Fung Wu
IPC分类号： H01L25/00
CPC分类号： H03K19/177
摘要： A multi-product integrated circuit die includes at least two different portions, of which at least one portion can be deliberately rendered non-operational in some manner (e.g., non-functional, inaccessible, and/or non-programmable) within the package. A selection code storage circuit stores a product selection code. A first value of the product selection code selects the option where both the first and second portions of the first die are operational. A second value of the product selection code selects the option where only the first portion of the first die is operational. The selection code storage circuit can include non-volatile memory or a fuse structure, or the product selection code can be configured as a package bonding option. The product selection code can also enable boundary scan for the operational portion of the die, and omit from the boundary scan chain any portions of the die that are deliberately rendered non-operational.
摘要翻译：多产品集成电路管芯包括至少两个不同的部分，其中至少一个部分可以以某种方式（例如，非功能的，不可访问的和/或不可编程的）被故意地变为不可操作的。选择码存储电路存储产品选择码。产品选择代码的第一个值选择第一模具的第一和第二部分都可操作的选项。产品选择代码的第二个值选择仅第一个模具的第一部分可操作的选项。选择代码存储电路可以包括非易失性存储器或熔丝结构，或者可以将产品选择代码配置为封装绑定选项。产品选择代码还可以为模具的操作部分启用边界扫描，并且从边界扫描链中省略故意使其不可操作的模具的任何部分。

6. 发明授权

US07230445B1 System monitor in a programmable logic device 有权
标题翻译：可编程逻辑器件中的系统监视器
公开(公告)号：US07230445B1
公开(公告)日：2007-06-12
申请号：US11590336
申请日：2006-10-31
申请人： F. Erich Goetting , John K. Jennings , Anthony J. Collins , Patrick J. Quinn
发明人： F. Erich Goetting , John K. Jennings , Anthony J. Collins , Patrick J. Quinn
IPC分类号： H03K19/003
CPC分类号： H03K19/17732 , G01R31/3167 , G01R31/318516
摘要： Method and apparatus for a system monitor embedded in a programmable logic device are described. The system monitor includes a dynamic reconfiguration port interface for configuring or reconfiguring the system monitor during operation thereof. The system monitor includes an analog-to-digital converter which is reconfigurable responsive to input via a dynamic reconfiguration port.
摘要翻译：描述嵌入可编程逻辑器件中的系统监视器的方法和装置。系统监视器包括用于在其操作期间配置或重新配置系统监视器的动态重新配置端口接口。系统监视器包括可经由动态重新配置端口响应于输入而重新配置的模数转换器。

7. 发明授权

US06204691B1 FPGA with a plurality of input reference voltage levels grouped into sets 有权
标题翻译： FPGA具有多个输入参考电压电平分组成组
公开(公告)号：US06204691B1
公开(公告)日：2001-03-20
申请号：US09569745
申请日：2000-05-11
申请人： F. Erich Goetting , Scott O. Frake , Venu M. Kondapalli , Steven P. Young
发明人： F. Erich Goetting , Scott O. Frake , Venu M. Kondapalli , Steven P. Young
IPC分类号： H03K19094
CPC分类号： H03K19/17744 , H03K19/00361 , H03K19/1778 , H03K19/17788
摘要： The invention comprises an FPGA having a plurality of input reference voltages and/or output voltage supplies. In one embodiment, two or more differential amplifiers in the same configurable input buffer use different input reference voltages. According to a second aspect of the invention, the I/O pad line is configurably connected to the input reference voltage line, so that any configurable Input/Output Block (IOB) can be used to supply the input reference voltage. According to a third aspect of the invention, the reference input of an I/O is configurably connected to any of two or more input reference voltage lines. According to another aspect of the invention, a single input reference voltage and/or a single output voltage supply is applied to each IOB, with the IOBs grouped into sets. Each set of IOBs has a separate input reference voltage and/or a separate output voltage supply.
摘要翻译：本发明包括具有多个输入参考电压和/或输出电压源的FPGA。在一个实施例中，同一可配置输入缓冲器中的两个或多个差分放大器使用不同的输入参考电压。根据本发明的第二方面，I / O焊盘线可配置地连接到输入参考电压线，使得可以使用任何可配置的输入/输出块（IOB）来提供输入参考电压。根据本发明的第三方面，I / O的参考输入可配置地连接到两个或更多个输入参考电压线中的任一个。根据本发明的另一方面，将单个输入参考电压和/或单个输出电压电源应用于每个IOB，其中IOB被分组成组。每组IOB具有单独的输入参考电压和/或单独的输出电压电源。

8. 发明授权

US5365125A Logic cell for field programmable gate array having optional internal feedback and optional cascade 失效
标题翻译：用于现场可编程门阵列的逻辑单元具有可选的内部反馈和可选级联
公开(公告)号：US5365125A
公开(公告)日：1994-11-15
申请号：US919658
申请日：1992-07-23
申请人： F. Erich Goetting , Stephen M. Trimberger
发明人： F. Erich Goetting , Stephen M. Trimberger
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： H03K19/17728 , H03K19/1736 , H03K19/17704
摘要： The logic cell of the current invention is useful in a field programmable logic device, particularly a device in which an interconnect structure is interconnected by antifuses, and logic cells are programmed using pass transistors. All input leads of the logic cell can be selectively inverted. The output signal from one logic cell can be cascaded as input to the adjacent cell for efficiently computing wide functions. An optional feedback path allows the cell to be optionally used for sequential functions without the delay caused by a feedback path through field programmed connections. Configuration units can serve the multiple purposes of selectively applying programming voltages to the interconnect structure, shifting in configuration information for configuring the interconnect structure, and capturing and shifting out states of the interconnect lines. A novel output buffer allows 3-state control from multiple sources. A novel reset circuit allows only the cells used as sequential elements to be reset, and only when reset would not cause contention with an input data signal.
摘要翻译：本发明的逻辑单元可用于现场可编程逻辑器件，特别是其中互连结构通过反熔丝互连的器件，并且使用传输晶体管对逻辑单元进行编程。可以选择性地反转逻辑单元的所有输入引线。来自一个逻辑单元的输出信号可以级联为相邻单元的输入，以有效地计算广泛的功能。可选的反馈路径允许单元可选地用于顺序功能，而没有由通过现场编程的连接的反馈路径引起的延迟。配置单元可以用于选择性地将编程电压施加到互连结构，移位用于配置互连结构的配置信息以及捕获和移出互连线的状态的多个目的。一个新颖的输出缓冲器允许来自多个源的3状态控制。一个新的复位电路只允许用作顺序元件的单元被复位，并且只有当复位不会引起与输入数据信号的争用时。

9. 发明授权

US06775342B1 Digital phase shifter 有权
标题翻译：数字移相器
公开(公告)号：US06775342B1
公开(公告)日：2004-08-10
申请号：US09684540
申请日：2000-10-06
申请人： Steven P. Young , John D. Logue , Andrew K. Percey , F. Erich Goetting , Alvin Y. Ching
发明人： Steven P. Young , John D. Logue , Andrew K. Percey , F. Erich Goetting , Alvin Y. Ching
IPC分类号： H04L2500
CPC分类号： H03L7/0814 , G06F1/10 , H03L7/07
摘要： After a delay lock loop synchronizes a reference clock signal with a skewed clock signal, a digital phase shifter can be used to shift the skewed clock signal by a small amount with respect to the reference clock signal. The tap/trim settings of a delay line in the main path of the delay lock loop can be transmitted to the digital phase shifter, thereby informing the digital phase shifter of the period of the reference clock signal. In response, the digital phase shifter provides a phase control signal that introduces a delay, which is referenced to the period of the reference clock signal, to either the reference clock signal or the skew clock signal. The phase control signal is proportional to a predetermined fraction of the period of the reference clock signal. The digital phase shifter can be controlled to operate in several modes. In a first fixed mode, the digital phase shifter introduces delay to the skew clock signal. In a second fixed mode, the digital phase shifter introduces delay to the reference clock signal. In a first variable mode, the digital phase shifter can cause the reference clock signal to lead or lag the skew clock signal by controlling the delay of the reference clock signal. In a second variable mode, the digital phase shifter can cause the reference clock signal to lead or lag the skew clock signal by controlling the delay of the skew clock signal.
摘要翻译：在延迟锁定环路使参考时钟信号与偏斜时钟信号同步之后，数字移相器可用于相对于参考时钟信号将偏斜的时钟信号移位一小段量。在延迟锁定环路的主路径上的延迟线的抽头/微调设置可被发送到数字移相器，由此通知数字移相器参考时钟信号的周期。作为响应，数字移相器提供相位控制信号，其将参考时钟信号的周期的延迟引入参考时钟信号或偏斜时钟信号。相位控制信号与参考时钟信号的周期的预定分数成比例。数字移相器可以控制在多种模式下工作。在第一固定模式中，数字移相器将延迟引入到偏斜时钟信号。在第二固定模式中，数字移相器将延迟引入参考时钟信号。在第一可变模式中，数字移相器可以通过控制参考时钟信号的延迟来引起参考时钟信号引导或延迟偏斜时钟信号。在第二可变模式中，数字移相器可以通过控制偏斜时钟信号的延迟来引起参考时钟信号引导或延迟偏斜时钟信号。

10. 发明授权

US06448809B2 FPGA with a plurality of input reference voltage levels 有权
标题翻译： FPGA具有多个输入参考电压电平
公开(公告)号：US06448809B2
公开(公告)日：2002-09-10
申请号：US09924356
申请日：2001-08-07
申请人： F. Erich Goetting , Scott O. Frake , Venu M. Kondapalli , Steven P. Young
发明人： F. Erich Goetting , Scott O. Frake , Venu M. Kondapalli , Steven P. Young
IPC分类号： G06F738
CPC分类号： H03K19/17744 , H03K19/00361 , H03K19/1778 , H03K19/17788
摘要： The invention comprises an FPGA having a plurality of input reference voltages and/or output voltage supplies. In one embodiment, two or more differential amplifiers in the same configurable input buffer use different input reference voltages. According to a second aspect of the invention, the I/O pad line is configurably connected to the input reference voltage line, so that any configurable Input/Output Block (IOB) can be used to supply the input reference voltage. According to a third aspect of the invention, the reference input of an I/O is configurably connected to any of two or more input reference voltage lines. According to another aspect of the invention, a single input reference voltage and/or a single output voltage supply is applied to each IOB, with the IOBs grouped into sets. Each set of IOBs has a separate input reference voltage and/or a separate output voltage supply.
摘要翻译：本发明包括具有多个输入参考电压和/或输出电压源的FPGA。在一个实施例中，同一可配置输入缓冲器中的两个或多个差分放大器使用不同的输入参考电压。根据本发明的第二方面，I / O焊盘线可配置地连接到输入参考电压线，使得可以使用任何可配置的输入/输出块（IOB）来提供输入参考电压。根据本发明的第三方面，I / O的参考输入可配置地连接到两个或更多个输入参考电压线中的任一个。根据本发明的另一方面，将单个输入参考电压和/或单个输出电压电源应用于每个IOB，其中IOB被分组成组。每组IOB具有单独的输入参考电压和/或单独的输出电压电源。

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