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1. 发明申请

US20100231276A1 DIGITAL ELECTRONIC DEVICE AND METHOD OF ALTERING CLOCK DELAYS IN A DIGITAL ELECTRONIC DEVICE 有权
标题翻译：数字电子设备及其在数字电子设备中改变时钟延迟的方法
公开(公告)号：US20100231276A1
公开(公告)日：2010-09-16
申请号：US12526503
申请日：2008-01-31
申请人： Vincent Huard
发明人： Vincent Huard
IPC分类号： H03L7/00
CPC分类号： H03K5/135 , G06F1/04 , H03K5/26 , H03K2005/00084 , H03L7/00
摘要： A digital electronic device is provided with a first and second sequential logic unit (SS1, SS2), each for receiving an input signal (D) and for outputting a first and second output signal (Q, QF), respectively. The electronic device furthermore comprises a comparator unit (C) for comparing the first and second output signals (Q, QF) and an adaptive clock generator unit (ACG) for generating a first and second internal clock (CK, CKF) for the first and second sequential logic unit (SS1, SS2), respectively. In a self-tuning mode, the adaptive clock generator unit (ACG) is adapted to delay the first and second internal clock signals (CK, CKF) with respect to the other internal clock signal (CKF). The delay induced by the adaptive control generator unit (ACG) is dependent on the result of the comparison unit (C). In a normal operation mode the adaptive control generator unit (ACG) is adapted to maintain the delay between the first and second internal clock signals constant.
摘要翻译：数字电子设备设置有第一和第二顺序逻辑单元（SS1，SS2），每个用于接收输入信号（D）并分别输出第一和第二输出信号（Q，QF）。电子设备还包括用于比较第一和第二输出信号（Q，QF）和自适应时钟发生器单元（ACG）的比较器单元（C），用于产生用于第一和第二输出信号的第一和第二内部时钟（CK，CKF）第二顺序逻辑单元（SS1，SS2）。在自调谐模式中，自适应时钟发生器单元（ACG）适于相对于另一个内部时钟信号（CKF）延迟第一和第二内部时钟信号（CK，CKF）。由自适应控制发生器单元（ACG）引起的延迟取决于比较单元（C）的结果。在正常操作模式中，自适应控制发生器单元（ACG）适于保持第一和第二内部时钟信号之间的延迟恒定。

2. 发明申请

US20060033583A1 Frequency adjustment circuit 有权
标题翻译：频率调节电路
公开(公告)号：US20060033583A1
公开(公告)日：2006-02-16
申请号：US11196512
申请日：2005-08-04
申请人： Tetsuya Tokunaga , Hiroyuki Arai , Takeshi Kimura , Ryouichi Ando , Mamoru Yamaguchi
发明人： Tetsuya Tokunaga , Hiroyuki Arai , Takeshi Kimura , Ryouichi Ando , Mamoru Yamaguchi
IPC分类号： H03L7/00
CPC分类号： H03K3/0231 , H03K2005/00084
摘要： A frequency adjustment circuit that maintains a target frequency even when frequency adjustment data of zapping circuit is changed by an external noise is offered. The frequency adjustment circuit includes a reset signal generation circuit, a frequency adjustment data latch circuit that latches and retains the frequency adjustment data ZP1 and ZP2 generated by a first zapping circuit and a second zapping circuit based on a latch clock ZCLK and a latch clock generation circuit that generates the latch clock ZCLK. The reset signal generation circuit generates a periodic reset signal ZRES that is synchronized with a rise of an enable signal EN generated from an interface circuit. The latch clock generation circuit generates the latch clock ZCLK that is synchronized with a fall of the enable signal EN.
摘要翻译：提供即使在由于外部噪声而使切换电路的频率调整数据变化的情况下也能够维持目标频率的频率调整电路。频率调整电路包括复位信号生成电路，频率调整数据锁存电路，其锁存并保持由第一切换电路产生的频率调整数据ZP 1和ZP 2，以及基于锁存时钟ZCLK和锁存器的第二切换电路时钟生成电路，生成锁存时钟ZCLK。复位信号产生电路产生与从接口电路产生的使能信号EN的上升同步的周期性复位信号ZRES。锁存时钟产生电路产生与使能信号EN的下降同步的锁存时钟ZCLK。

3. 发明申请

US20050246596A1 Auto-calibration method for delay circuit 有权
标题翻译：延迟电路的自动校准方法
公开(公告)号：US20050246596A1
公开(公告)日：2005-11-03
申请号：US10986030
申请日：2004-11-12
申请人： Lin Chen , Sou Chen
发明人： Lin Chen , Sou Chen
IPC分类号： G06K5/04 , G11B5/00 , G11B20/20 , H03H11/26 , H03K5/00 , H03K5/13 , H03L7/00
CPC分类号： H03K5/131 , H03K2005/00058 , H03K2005/00084 , H03K2005/00156
摘要： An auto-calibration method is applied to a delay circuit, which includes a plurality of delay chains. One of the delay chains is previously designated as the delay path where data output from the delay circuit passes through. The accumulative number of errors is continuously detected and counted during a unit of time when the delay circuit is in use. If the number of accumulative errors of the designated delay path is larger than a threshold value, the delay circuit scans all the delay chains and records their accumulative error numbers during a unit of time; otherwise, the designated delay path keeps what it do. Afterwards, the number of accumulative errors is compared between all the delay chains to find out which one of the delay chains has a minimum accumulative error number, and the delay chain with a minimum accumulative error number is designated as a new current delay path. Then, the number of accumulative errors of the new designated delay path is continuously observed on whether it is larger than the threshold value. The aforesaid steps are performed again according to the observation.
摘要翻译：自动校准方法被应用于包括多个延迟链的延迟电路。延迟链之一被预先指定为延迟电路输出的数据通过的延迟路径。在使用延迟电路的时间单位内，连续地检测和计数累积误差数。如果指定延迟路径的累积误差数大于阈值，则延迟电路扫描所有延迟链，并在一个时间单位内记录其累积误差数; 否则，指定的延迟路径保持它的作用。之后，在所有的延迟链之间比较累积误差的数量，找出延迟链中哪一个具有最小累积误差数，将具有最小累积误差数的延迟链指定为新的当前延迟路径。然后，连续观察新的指定延迟路径的累计误差的数量是否大于阈值。根据观察，再次进行上述步骤。

4. 发明申请

US20050001648A1 Timing generator and semiconductor test apparatus 失效
标题翻译：定时发生器和半导体测试装置
公开(公告)号：US20050001648A1
公开(公告)日：2005-01-06
申请号：US10484980
申请日：2002-07-26
申请人： Kazuhiro Yamamoto
发明人： Kazuhiro Yamamoto
IPC分类号： G01R31/319 , H03K5/00 , H03K5/13 , G01R31/34
CPC分类号： G01R31/31922 , H03K5/131 , H03K5/133 , H03K2005/00071 , H03K2005/00084
摘要： There is provided a timing generator capable of absorbing a delay time error of a variable delay circuit without increasing the number of bits of path data and suppressing deterioration of the timing accuracy from the designed value to the minimum. The timing generator is configured to include a selection unit 13 which assigns five-bit delay device candidates to a three-bit partial bit signal of all the bit signals constituting the path data outputted from a linearization memory 12 and selects three delay devices whose number is equal to the bit count of the partial bit signal.
摘要翻译：提供一种能够吸收可变延迟电路的延迟时间误差的定时发生器，而不增加路径数据的位数，并将定时精度的降低从设计值降低到最小。定时发生器被配置为包括：选择单元13，其向构成从线性化存储器12输出的路径数据的所有比特信号的三比特部分比特信号分配五比特延迟装置候选，并选择三个延迟装置，等于部分位信号的位计数。

5. 发明申请

US20030231038A1 Pulse shaping circuit and method 审中-公开
标题翻译：脉冲整形电路及方法
公开(公告)号：US20030231038A1
公开(公告)日：2003-12-18
申请号：US10167494
申请日：2002-06-13
发明人： Kenneth Koch II , John R. Spencer , Steven L. Jackson
IPC分类号： H03K005/12
CPC分类号： H03K5/12 , H03K5/133 , H03K2005/00084 , H03K2005/00195
摘要： A pulse shaping circuit includes a series resistor and shunt capacitor that is switched from a finite capacitance value to a substantially open circuit in response to the voltage across the capacitor being on opposite sides of a threshold. The capacitor comprises a MOSFET having a gate connected to the resistor and a source drain path, connected to ground and nullVdd in first and second embodiments, respectively.
摘要翻译：脉冲整形电路包括串联电阻器和并联电容器，该串联电阻器和并联电容器响应于在阈值的相对侧上的电容器两端的电压从有限电容值切换到基本上开路。电容器包括分别在第一和第二实施例中连接到电阻器的栅极和连接到地和+ Vdd的源极漏极路径的MOSFET。

6. 发明授权

US5933039A Programmable delay line 失效
标题翻译：可编程延时线
公开(公告)号：US5933039A
公开(公告)日：1999-08-03
申请号：US823708
申请日：1997-03-25
申请人： Titkwan Hui , Robert W. Mounger
发明人： Titkwan Hui , Robert W. Mounger
IPC分类号： H03K5/00 , H03K5/13 , H04L27/12 , H04L27/156 , H03K5/14
CPC分类号： H03K5/13 , H03K5/131 , H03K5/133 , H04L27/12 , H04L27/156 , H03K2005/00065 , H03K2005/00071 , H03K2005/00084 , H03K2005/00156
摘要： Digital signal delay lines with electrically programmable and trimmable delay times, including electrically erasable and reprogrammable delay times. Floating gate field effect transistors are programmed to select current, capacitance, and/or threshold and thereby set a delay time determined by acurrent charging of a capacitor up to a threshold voltage. Trimming after packaging avoids package offsets. Temperature and power supply voltage compensation by current combining gives compensation compatible with the electrical programming.
摘要翻译：具有电可编程和可调节延迟时间的数字信号延迟线，包括电可擦除和可重新编程的延迟时间。浮动栅场效应晶体管被编程为选择电流，电容和/或阈值，从而设置通过电容器的充电充电确定的延迟时间直到阈值电压。包装后修整避免包装抵消。温度和电源电压补偿通过电流组合给出与电气编程兼容的补偿。

7. 发明授权

US08278986B2 Trimming of a pseudo-closed loop programmable delay line 有权
标题翻译：微调闭环可编程延迟线
公开(公告)号：US08278986B2
公开(公告)日：2012-10-02
申请号：US12977093
申请日：2010-12-23
申请人： Luca Bettini , Guido De Sandre
发明人： Luca Bettini , Guido De Sandre
IPC分类号： H03L7/00
CPC分类号： H03K5/131 , H03K5/133 , H03K2005/00071 , H03K2005/00084 , H03K2005/00104 , H03K2005/00123 , H03K2005/00143 , H03L7/0814
摘要： An embodiment is proposed for trimming a programmable delay line in an integrated device, which delay line is adapted to delay an input signal being synchronous with a synchronization signal of the integrated device—by a total delay. An embodiment of a corresponding method includes the steps of: preliminary programming the delay line to provide a selected nominal value of the total delay equal to a period of the timing signal, and trimming the delay line to vary an actual value of the total delay until the actual value of the total delay matches the period of the synchronization signal.
摘要翻译：提出了一种用于修整集成器件中的可编程延迟线的实施例，该延迟线适于延迟与集成器件的同步信号同步的输入信号 - 总延迟。相应方法的实施例包括以下步骤：对延迟线进行初步编程以提供等于定时信号的周期的总延迟的选定标称值，以及修整延迟线以改变总延迟的实际值，直到总延迟的实际值与同步信号的周期匹配。

8. 发明授权

US07737750B2 Method and device for determining trim solution 失效
标题翻译：确定修剪液的方法和装置
公开(公告)号：US07737750B2
公开(公告)日：2010-06-15
申请号：US11653312
申请日：2007-01-16
申请人： Steffen Loeffler
发明人： Steffen Loeffler
IPC分类号： H03L7/06
CPC分类号： H03L7/08 , H03K5/133 , H03K2005/00058 , H03K2005/00084 , H03K2005/00104
摘要： A trimming system for determining a trim solution for a semiconductor device includes an internal value generating circuit for generating an internal value based upon a counter value. The relationship between the internal delay value and an external reference is compared to determine if the counter value is a possible trim solution, while predetermined counter values are excluded as a trim solution.
摘要翻译：一种用于确定半导体器件的修剪液的修整系统包括内部值产生电路，用于基于计数器值产生内部值。比较内部延迟值和外部参考之间的关系，以确定计数器值是否为可能的修正值解，同时将预定的计数器值作为修整方案排除。

9. 发明申请

US20090307516A1 Asynchronous circuit insensitive to delays with time delay insertion circuit 有权
标题翻译：异步电路对时延延迟插入电路不敏感
公开(公告)号：US20090307516A1
公开(公告)日：2009-12-10
申请号：US12453826
申请日：2009-05-22
申请人： Marc Renaudin , Ghislain Bouesse
发明人： Marc Renaudin , Ghislain Bouesse
IPC分类号： G06F1/12
CPC分类号： H03K19/00346 , H03K5/133 , H03K19/00323 , H03K2005/00058 , H03K2005/00084
摘要： The asynchronous circuit insensitive to delays comprises at least one time delay insertion circuit on the propagation path of a signal. The delay insertion circuit comprises, between an input and an output of the signal, a Muller C-element and a plurality of delay circuits connected in series to an output of the Muller C-element. The outputs of the delay circuits are connected to corresponding inputs of a multiplexing circuit having an output constituting the output of the delay insertion circuit. The Muller C-element comprises an input connected to the output of the last delay circuit via an inverter gate, and an input constituting the input of the signal to the delay insertion circuit. The multiplexing circuit control circuit preferably comprises a random generator.
摘要翻译：对延迟不敏感的异步电路包括在信号的传播路径上的至少一个时间延迟插入电路。延迟插入电路在信号的输入和输出之间包括与Muller C元件的输出串联连接的Muller C元件和多个延迟电路。延迟电路的输出连接到具有构成延迟插入电路的输出的输出的复用电路的相应输入。 Muller C元件包括通过反相器门连接到最后延迟电路的输出的输入，以及构成向延迟插入电路输入信号的输入。多路复用电路控制电路优选地包括随机发生器。

10. 发明申请

US20090212837A1 Circuit, apparatus and method of transmitting signal 有权
标题翻译：发送信号的电路，装置和方法
公开(公告)号：US20090212837A1
公开(公告)日：2009-08-27
申请号：US12320640
申请日：2009-01-30
申请人： Toshihiro Katoh
发明人： Toshihiro Katoh
IPC分类号： H03H11/26 , H05K9/00 , G06F17/50
CPC分类号： H03K5/14 , H01L23/5225 , H01L2924/0002 , H03K2005/00084 , H01L2924/00
摘要： A circuit includes a first wiring to transmit a first signal, an alteration element to adjust a delay amount being added to the first wiring, and a shield element to shield the alteration element from a second wiring, the second wiring transmitting a second signal.
摘要翻译：电路包括用于传输第一信号的第一布线，用于调整添加到第一布线的延迟量的改变元件，以及屏蔽元件，用于屏蔽来自第二布线的改变元件，第二布线传输第二信号。

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