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    • 3. 发明授权
      US06275068B1 Programmable clock delay 有权
    • Programmable clock delay
    • 可编程时钟延迟
    • US06275068B1
    • 2001-08-14
    • US09469905
    • 1999-12-22
    • Bahram Ghaffarzadeh Kermani , Clinton Hays Holder, Jr.
    • Bahram Ghaffarzadeh Kermani , Clinton Hays Holder, Jr.
    • H03K513
    • H03K5/135 , H03K5/133
    • In an integrated circuit, a system and method of programmably controlling the delay between a second clock signal with respect to a first clock signal after fabricating the integrated circuit. Prior to fabrication, a programmable delay group is formed and will be included in the integrated circuit. The programmable delay group includes a plurality of parallel coupled sets of delay stages. Each set having at least one delay stage. For the sets having more than one delay stage, the delay stages are serially coupled. After fabrication of the integrated circuit and in operation, the first clock signal is applied to one end of each of the sets of delay stages. The enable signals are generated and applied to the programmable delay group in order to enable one of the sets of delay stages. The enabled set delays the first clock signal, thereby producing the second clock signal at the other end of the enabled set and hereby controlling the delay of the second clock signal.
    • 在集成电路中，一种可编程地控制在制造集成电路之后相对于第一时钟信号的第二时钟信号之间的延迟的系统和方法。 在制造之前，形成可编程延迟组并将其包含在集成电路中。 可编程延迟组包括多个并联耦合的延迟级组。 每组具有至少一个延迟阶段。 对于具有多于一个延迟级的组，延迟级串联耦合。 在制造集成电路并且在工作之后，第一时钟信号被施加到每组延迟级的一端。 产生使能信号并将其施加到可编程延迟组，以便使能延迟级组中的一个。 使能的设置延迟第一时钟信号，从而在使能集合的另一端产生第二时钟信号，从而控制第二时钟信号的延迟。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 4. 发明授权
      US06271696B1 Phase adjustment circuit 失效
    • Phase adjustment circuit
    • 相位调整电路
    • US06271696B1
    • 2001-08-07
    • US09440155
    • 1999-11-15
    • Naoki Kobayashi
    • Naoki Kobayashi
    • H03K513
    • H03L7/0805 , G06F1/10 , H03K5/131 , H03K5/133 , H03K2005/00104 , H03K2005/00247 , H03L7/0814
    • A phase adjustment circuit of the present invention includes a plurality of input terminals which input a plurality of clock signals, respectively, and a plurality of first elements which input the clock signals, respectively, and adjust the clock signals, respectively. The phase adjustment circuit has a second element which compares the phase of a reference clock signal and the phase of an output signal from one of the first elements and outputs a compared result. A third element inputs the compared result and controls each of the first elements based on the compared result. Another phase adjustment circuit of the present invention includes a plurality of input terminals, which input a plurality of clock signals, respectively; a plurality of first elements, which input the clock signals, respectively, and oscillates the clock signals, respectively; and a second element which compares the phase of a reference clock signal and the phase of an output signal from one of the first elements and outputs a compared result. The first elements input the compared result and oscillate the clock signals, respectively, based on the compared result. A method of the present invention for adjusting the phase between a plurality of clock signals includes delaying each of the clock signals by a delay amount; comparing the phase of a reference clock signal and the phase of one of the delayed clock signals which is delayed during the delaying step; and controlling the delay amount based on the compared result which is compared during the comparing step.
    • 本发明的相位调整电路包括分别输入多个时钟信号的多个输入端子和分别输入时钟信号的多个第一元件，并分别调整时钟信号。 相位调整电路具有第二元件，其将参考时钟信号的相位与来自第一元件之一的输出信号的相位进行比较，并输出比较结果。 第三个元素输入比较结果，并根据比较结果控制每个第一个元素。 本发明的另一个相位调整电路包括分别输入多个时钟信号的多个输入端子; 分别输入时钟信号并振荡时钟信号的多个第一元件; 以及第二元件，其比较参考时钟信号的相位和来自所述第一元件之一的输出信号的相位，并输出比较结果。 第一个元素输入比较结果，并根据比较结果分别振荡时钟信号。 用于调整多个时钟信号之间的相位的本发明的方法包括延迟每个时钟信号延迟量; 比较参考时钟信号的相位和在延迟步骤期间延迟的延迟时钟信号之一的相位; 以及基于在比较步骤期间比较的比较结果来控制延迟量。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 10. 发明授权
      US06275086B1 Clock signal generator for an integrated circuit 有权
    • Clock signal generator for an integrated circuit
    • 用于集成电路的时钟信号发生器
    • US06275086B1
    • 2001-08-14
    • US09385007
    • 1999-08-27
    • Hiroko Douchi , Hiroyoshi Tomita
    • Hiroko Douchi , Hiroyoshi Tomita
    • H03K513
    • G11C7/1066 , G11C7/1072 , G11C7/222 , H03K5/2481
    • A clock signal generator which is particularly useful for a double data rate SDRAM (DDR-SDRAM) includes two or more clock signal input buffers and an enable signal input buffer. The clock signal generator generates internal clock signals that fluctuate at substantially different timings, yet the relationship between the internal clock signals with respect to validation and invalidation timing is constant. A latch circuit latches an enable signal from the enable signal buffer in accordance with a first internal clock signal from a first one of the clock signal buffers. A first enable signal connected to the latch circuit holds the latched enable signal in accordance with the first internal clock signal. A second enable circuit receives the first enable signal and the first internal clock signal and generates a second enable signal used to activate the clock signal buffers. A logic gate receives the first enable signal and the first internal clock signal and controls the output of the first internal clock signal.
    • 对双倍数据速率SDRAM（DDR-SDRAM）特别有用的时钟信号发生器包括两个或更多个时钟信号输入缓冲器和使能信号输入缓冲器。 时钟信号发生器产生以基本上不同的定时波动的内部时钟信号，但是内部时钟信号相对于验证和无效定时的关系是恒定的。 锁存电路根据来自第一个时钟信号缓冲器的第一内部时钟信号来锁存来自使能信号缓冲器的使能信号。 连接到锁存电路的第一使能信号根据第一内部时钟信号保持锁存使能信号。 第二使能电路接收第一使能信号和第一内部时钟信号，并产生用于激活时钟信号缓冲器的第二使能信号。 逻辑门接收第一使能信号和第一内部时钟信号并控制第一内部时钟信号的输出。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
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