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1. 发明授权

US08361904B2 Semiconductor device having fine pattern wiring lines integrally formed with contact plug and method of manufacturing same 有权
标题翻译：具有与接触插塞一体形成的精细图案布线的半导体器件及其制造方法
公开(公告)号：US08361904B2
公开(公告)日：2013-01-29
申请号：US12966110
申请日：2010-12-13
申请人： Dong-seok Lee , Seung-pil Chung , Ji-young Lee
发明人： Dong-seok Lee , Seung-pil Chung , Ji-young Lee
IPC分类号： H01L21/311
CPC分类号： H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L21/32139 , H01L21/76804 , H01L21/76811 , H01L21/76813 , H01L21/76816 , H01L27/105 , H01L27/1052 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device and method are disclosed in which an interlayer insulating layer is patterned using multiple overlaying masks to define the geometry of contact plugs and corresponding wiring layers separated by fine pitches.
摘要翻译：公开了一种半导体器件和方法，其中使用多个覆盖掩模来图案化层间绝缘层，以限定接触插塞的几何形状和由细间距分开的对应的布线层。

2. 发明申请

US20120049377A1 SEMICONDUCTOR DEVICE AND METHOD OF DOUBLE PHOTOLITHOGRAPHY PROCESS FOR FORMING PATTERNS OF THE SEMICONDUCTOR DEVICE 有权
标题翻译：用于形成半导体器件的图案的双光刻机工艺的半导体器件和方法
公开(公告)号：US20120049377A1
公开(公告)日：2012-03-01
申请号：US12983478
申请日：2011-01-03
申请人： Song-Yi Yang , Seung-pil Chung , Dong-hyun Kim , O-ik Kwon , Hong Cho
发明人： Song-Yi Yang , Seung-pil Chung , Dong-hyun Kim , O-ik Kwon , Hong Cho
IPC分类号： H01L23/52 , H01L21/302 , H01L21/768
CPC分类号： H01L27/11519 , H01L21/0337 , H01L21/0338 , H01L21/32139 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device and a method of forming patterns on a semiconductor device are disclosed. The semiconductor device may include high-density patterns with a minimum size that may be less the resolution limit of a photolithography process, and may have a substrate including a memory cell region and an adjacent connection region, a plurality of first conductive lines extending from the memory cell region to the connection region in a first direction, a plurality of second conductive lines connected from respective first conductive lines to a plurality of pads having a width equal to twice the width of each of the first conductive lines. The method may include two levels of spacer formation to provide sub resolution line widths and spaces as well as selected multiples of the minimum line widths and spaces.
摘要翻译：公开了一种在半导体器件上形成图案的半导体器件和方法。半导体器件可以包括具有最小尺寸的高密度图案，其可以小于光刻工艺的分辨率极限，并且可以具有包括存储单元区域和相邻连接区域的基板，从第一导电线延伸的多个第一导电线存储单元区域连接到第一方向上的连接区域;多个第二导线，其从相应的第一导线连接到宽度等于每个第一导电线宽度的两倍的多个焊盘。该方法可以包括两个级别的间隔物形成以提供子分辨率线宽度和空间以及最小线宽和空间的选定倍数。

3. 发明申请

US20050087893A1 Method of removing oxide layer and semiconductor manufacturing apparatus for removing oxide layer 有权
标题翻译：去除氧化物层的方法和用于去除氧化物层的半导体制造装置
公开(公告)号：US20050087893A1
公开(公告)日：2005-04-28
申请号：US10997902
申请日：2004-11-29
申请人： Seung-pil Chung , Kyu-whan Chang , Sun-jung Lee , Kun-tack Lee , Im-soo Park , Kwang-wook Lee , Moon-hee Lee
发明人： Seung-pil Chung , Kyu-whan Chang , Sun-jung Lee , Kun-tack Lee , Im-soo Park , Kwang-wook Lee , Moon-hee Lee
IPC分类号： H01L21/302 , H01L21/306 , H01L21/3065 , H01L21/31 , H01L21/311 , H01L21/3213
CPC分类号： H01L21/02057 , H01L21/31116
摘要： A method for removing an oxide layer such as a natural oxide layer and a semiconductor manufacturing apparatus which uses the method to remove the oxide layer. A vertically movable susceptor is installed at the lower portion in a processing chamber and a silicon wafer is loaded onto the susceptor when it is at the lower portion of the processing chamber. The air is exhausted from the processing chamber to form a vacuum condition therein. A hydrogen gas in a plasma state and a fluorine-containing gas are supplied into the processing chamber to induce a chemical reaction with the oxide layer on the silicon wafer, resulting in a reaction layer. Then, the susceptor is moved up to the upper portion of the processing chamber, to anneal the silicon wafer on the susceptor with a heater installed at the upper portion of the processing chamber, thus vaporizing the reaction layer. The vaporized reaction layer is exhausted out of the chamber. The oxide layer can be removed with a high selectivity while avoiding damage or contamination of the underlying layer.
摘要翻译：用于除去氧化物层的方法，例如天然氧化物层和使用该方法去除氧化物层的半导体制造装置。垂直移动的基座安装在处理室的下部处，并且当硅晶片位于处理室的下部时，将硅晶片装载到基座上。空气从处理室排出，在其中形成真空条件。将等离子体状态的氢气和含氟气体供给到处理室，以引起与硅晶片上的氧化物层的化学反应，产生反应层。然后，将基座向上移动到处理室的上部，通过安装在处理室上部的加热器对基座上的硅晶片退火，从而使反应层蒸发。蒸发的反应层被排出室外。可以以高选择性去除氧化物层，同时避免下层的损坏或污染。

4. 发明授权

US06537876B2 Method of manufacturing a semiconductor capacitor having a hemispherical grain layer using a dry cleaning process 失效
标题翻译：使用干洗方法制造具有半球形晶粒层的半导体电容器的方法
公开(公告)号：US06537876B2
公开(公告)日：2003-03-25
申请号：US09799033
申请日：2001-03-06
申请人： Seung-pil Chung , Kyu-hwan Chang , Young-min Kwon , Sang-lock Hah
发明人： Seung-pil Chung , Kyu-hwan Chang , Young-min Kwon , Sang-lock Hah
IPC分类号： H01L218242
CPC分类号： H01L28/84 , H01L21/02046 , Y10S438/906 , Y10S438/964
摘要： A method of manufacturing a semiconductor device having a hemispherical grain (HSG) layer employs a dry cleaning process. A polysilicon layer is formed on a specific material layer on a semiconductor substrate. Next, a polysilicon pattern, at least a portion of which is exposed, is formed by etching the polysilicon layer. The exposed surface of the polysilicon pattern is then dry cleaned by supplying hydrogen in a plasma state and a fluorine-based gas toward the exposed surface. The exposed surface of the polysilicon pattern may also be wet cleaned before being dry cleaned to wash away pollutants which may have been left thereon. An HSG layer is then formed on the cleaned surface of the polysilicon pattern. After the HSG layer is formed, the surface of the HSG layer may be dry cleaned again by supplying hydrogen in a plasma state and a fluorine-based gas toward the surface of the HSG layer. The surface of the HSG layer may also be further wet cleaned before being dry cleaned. Accordingly, the HSG layer is effectively cleaned without damaging or contaminating the HSG layer, thereby improving the reliability of the semiconductor device.
摘要翻译：制造具有半球形颗粒（HSG）层的半导体器件的方法采用干法处理。在半导体衬底上的特定材料层上形成多晶硅层。接下来，通过蚀刻多晶硅层形成其至少一部分露出的多晶硅图案。然后通过以等离子体状态供给氢气和将氟基气体朝向暴露的表面进行干式清洗。多晶硅图案的暴露表面也可以在干燥清洁之前被湿清洗以洗去可能留在其上的污染物。然后在多晶硅图案的清洁表面上形成HSG层。在形成HSG层之后，可以通过以等离子体状态供给氢，并将氟基气体朝向HSG层的表面再次干燥HSG层的表面。 HSG层的表面也可以在干洗之前进一步湿清洗。因此，HSG层被有效地清洁而不损坏或污染HSG层，从而提高半导体器件的可靠性。

5. 发明申请

US20060284277A1 Semiconductor device including bit line formed using damascene technique and method of fabricating the same 审中-公开
标题翻译：包括使用镶嵌技术形成的位线的半导体器件及其制造方法
公开(公告)号：US20060284277A1
公开(公告)日：2006-12-21
申请号：US11510349
申请日：2006-08-25
申请人： Seung-pil Chung , Chang-jin Kang , Jeong-sic Jeon , Kyeong-koo Chi , Seung-young Son , Sang-yong Kim
发明人： Seung-pil Chung , Chang-jin Kang , Jeong-sic Jeon , Kyeong-koo Chi , Seung-young Son , Sang-yong Kim
IPC分类号： H01L29/00
CPC分类号： H01L27/10885 , H01L21/31116 , H01L21/76816 , H01L21/76831 , H01L27/10888 , H01L27/10891
摘要： A semiconductor device includes an insulating layer having a T-shaped groove formed by a wide opening overlapping a narrow opening, a bit line conductive layer that at least partially fills the narrow opening, and a bit line capping layer that fills the groove so that its top surface is as high as that of the insulating layer. Spacers are formed on the inner walls of the wide opening.
摘要翻译：半导体器件包括：绝缘层，其具有由窄开口重叠的宽开口形成的T形槽，至少部分填充窄开口的位线导电层和填充槽的位线封盖层，使得其顶表面与绝缘层一样高。隔板形成在宽开口的内壁上。

6. 发明申请

US20050287738A1 Method of manufacturing a semiconductor memory device 有权
标题翻译：制造半导体存储器件的方法
公开(公告)号：US20050287738A1
公开(公告)日：2005-12-29
申请号：US11159130
申请日：2005-06-23
申请人： Sung-il Cho , Kyeong-koo Chi , Seung-pil Chung , Chang-jin Kang , Cheol-kyu Lee
发明人： Sung-il Cho , Kyeong-koo Chi , Seung-pil Chung , Chang-jin Kang , Cheol-kyu Lee
IPC分类号： H01L21/8242 , H01L21/02 , H01L21/311
CPC分类号： H01L21/31116 , H01L21/31122 , H01L21/31138 , H01L27/10852 , H01L28/91
摘要： A method of manufacturing a semiconductor memory device includes forming a carbon-containing layer on a semiconductor substrate, forming an insulating layer pattern on the carbon-containing layer, the insulating layer pattern partially exposing an upper surface of the carbon-containing layer, dry-etching the exposed portion of the carbon-containing layer, to form a carbon-containing layer pattern for defining a storage node hole, forming a bottom electrode inside the storage node hole, forming a dielectric layer on the bottom electrode inside the storage node hole, the dielectric layer covering the bottom electrode, and forming an upper electrode on the dielectric layer inside the storage node hole, the upper electrode covering the dielectric layer.
摘要翻译：半导体存储器件的制造方法包括在半导体衬底上形成含碳层，在含碳层上形成绝缘层图案，将含碳层的上表面部分地露出的绝缘层图案，蚀刻含碳层的暴露部分，形成用于限定存储节点孔的含碳层图案，在存储节点孔内部形成底部电极，在存储节点孔内部的底部电极上形成电介质层，所述介电层覆盖所述底部电极，并且在所述存储节点孔内部的所述电介质层上形成上部电极，所述上部电极覆盖所述电介质层。

7. 发明授权

US06562651B2 Method of manufacturing a semiconductor device having contact pads 有权
公开(公告)号：US06562651B2
公开(公告)日：2003-05-13
申请号：US09916319
申请日：2001-07-30
申请人： Seung-pil Chung , Kyeong-Koo Chi , Jung-Sik Jeon
发明人： Seung-pil Chung , Kyeong-Koo Chi , Jung-Sik Jeon
IPC分类号： H01L2100
CPC分类号： H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a semiconductor device includes forming an insulated wiring pattern on a semiconductor substrate, and forming a lower interlayer insulating layer on the wiring pattern. A hard mask is formed on the lower insulating layer. Self-aligned contact holes are formed to expose the substrate under openings or gaps of the wiring pattern by partially etching the lower interlayer insulating layer be using the hard mask as an etch mask. A surface treatment process is carried out against surface of the substrate exposed through the self-aligned contact holes. Then, a first conductive layer is conformably formed over the whole surface of the substrate over which the surface treatment process is finished. At this time, projections are formed on sidewalls of the self-aligned contact holes. The first conductive layer is anisotropically etched to remove the projection. A second conductive layer fills completely the self-aligned contact holes.

8. 发明授权

US08765572B2 Method of fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08765572B2
公开(公告)日：2014-07-01
申请号：US13168312
申请日：2011-06-24
申请人： Yong-lack Choi , Chang-hyun Cho , Seung-pil Chung , Hyun-seok Jang , Du-heon Song , Jung-dal Choi
发明人： Yong-lack Choi , Chang-hyun Cho , Seung-pil Chung , Hyun-seok Jang , Du-heon Song , Jung-dal Choi
IPC分类号： H01L21/764
CPC分类号： H01L21/7682 , H01L27/11521 , H01L27/11526
摘要： A method of fabricating a semiconductor device, in which an interference effect between word lines is substantially reduced or eliminated, includes forming a plurality of gate patterns on a substrate; forming a first insulating layer between the gate patterns, the first insulating layer filling a region between the gate patterns; etching the first insulating layer to remove a portion of the first insulating layer to a predetermined depth; and forming a second insulating layer on the gate patterns and the first insulating layer. A low-dielectric-constant material is formed between the gate patterns.
摘要翻译：一种制造半导体器件的方法，其中字线之间的干涉效应被显着地减少或消除，包括在衬底上形成多个栅极图案; 在所述栅极图案之间形成第一绝缘层，所述第一绝缘层填充所述栅极图案之间的区域; 蚀刻第一绝缘层以将第一绝缘层的一部分去除到预定深度; 以及在栅极图案和第一绝缘层上形成第二绝缘层。在栅极图案之间形成低介电常数材料。

9. 发明授权

US07488688B2 Method of removing oxide layer and semiconductor manufacturing apparatus for removing oxide layer 有权
标题翻译：去除氧化物层的方法和用于去除氧化物层的半导体制造装置
公开(公告)号：US07488688B2
公开(公告)日：2009-02-10
申请号：US10997902
申请日：2004-11-29
申请人： Seung-pil Chung , Kyu-whan Chang , Sun-jung Lee , Kun-tack Lee , Im-soo Park , Kwang-wook Lee , Moon-hee Lee
发明人： Seung-pil Chung , Kyu-whan Chang , Sun-jung Lee , Kun-tack Lee , Im-soo Park , Kwang-wook Lee , Moon-hee Lee
IPC分类号： H01L21/302
CPC分类号： H01L21/02057 , H01L21/31116
摘要： A method for removing an oxide layer such as a natural oxide layer and a semiconductor manufacturing apparatus which uses the method to remove the oxide layer. A vertically movable susceptor is installed at the lower portion in a processing chamber and a silicon wafer is loaded onto the susceptor when it is at the lower portion of the processing chamber. The air is exhausted from the processing chamber to form a vacuum condition therein. A hydrogen gas in a plasma state and a fluorine-containing gas are supplied into the processing chamber to induce a chemical reaction with the oxide layer on the silicon wafer, resulting in a reaction layer. Then, the susceptor is moved up to the upper portion of the processing chamber, to anneal the silicon wafer on the susceptor with a heater installed at the upper portion of the processing chamber, thus vaporizing the reaction layer. The vaporized reaction layer is exhausted out of the chamber. The oxide layer can be removed with a high selectivity while avoiding damage or contamination of the underlying layer.
摘要翻译：用于除去氧化物层的方法，例如天然氧化物层和使用该方法去除氧化物层的半导体制造装置。垂直移动的基座安装在处理室的下部处，并且当硅晶片位于处理室的下部时，将硅晶片装载到基座上。空气从处理室排出，在其中形成真空条件。将等离子体状态的氢气和含氟气体供给到处理室，以引起与硅晶片上的氧化物层的化学反应，产生反应层。然后，将基座向上移动到处理室的上部，通过安装在处理室上部的加热器对基座上的硅晶片退火，从而使反应层蒸发。蒸发的反应层被排出室外。可以以高选择性去除氧化物层，同时避免下层的损坏或污染。

10. 发明授权

US06513538B2 Method of removing contaminants from integrated circuit substrates using cleaning solutions 有权
公开(公告)号：US06513538B2
公开(公告)日：2003-02-04
申请号：US09862525
申请日：2001-05-22
申请人： Seung-pil Chung , Kyu-hwan Chang , Young-min Kwon , Sang-lock Hah
发明人： Seung-pil Chung , Kyu-hwan Chang , Young-min Kwon , Sang-lock Hah
IPC分类号： B08B600
CPC分类号： H01L21/02063 , C11D3/3947 , C11D7/265 , C11D7/36 , C11D11/0047 , H01L21/02046 , Y10S134/902 , Y10S438/906
摘要： A method for removing contaminants from an integrated circuit substrate include treating the substrate with a hydrogen peroxide cleaning solution containing a chelating agent, and treating the substrate with hydrogen gas and fluorine-containing gas, and annealing the substrate. Cleaning solutions includes ammonium, hydrogen peroxide, deionized water, and chelating agent. The chelating agent includes one to three compounds selected from the group consisting of carboxylic acid compounds, phosphonic acid compounds, and hydroxyl aromatic compounds. The fluorine-containing gas is a gas selected from the group consisting of nitrogen trifluoride (NF3), hexafluorosulphur (SF6), and trifluorochlorine (ClF3).

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