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1. 发明授权

US08765572B2 Method of fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08765572B2
公开(公告)日：2014-07-01
申请号：US13168312
申请日：2011-06-24
申请人： Yong-lack Choi , Chang-hyun Cho , Seung-pil Chung , Hyun-seok Jang , Du-heon Song , Jung-dal Choi
发明人： Yong-lack Choi , Chang-hyun Cho , Seung-pil Chung , Hyun-seok Jang , Du-heon Song , Jung-dal Choi
IPC分类号： H01L21/764
CPC分类号： H01L21/7682 , H01L27/11521 , H01L27/11526
摘要： A method of fabricating a semiconductor device, in which an interference effect between word lines is substantially reduced or eliminated, includes forming a plurality of gate patterns on a substrate; forming a first insulating layer between the gate patterns, the first insulating layer filling a region between the gate patterns; etching the first insulating layer to remove a portion of the first insulating layer to a predetermined depth; and forming a second insulating layer on the gate patterns and the first insulating layer. A low-dielectric-constant material is formed between the gate patterns.
摘要翻译：一种制造半导体器件的方法，其中字线之间的干涉效应被显着地减少或消除，包括在衬底上形成多个栅极图案; 在所述栅极图案之间形成第一绝缘层，所述第一绝缘层填充所述栅极图案之间的区域; 蚀刻第一绝缘层以将第一绝缘层的一部分去除到预定深度; 以及在栅极图案和第一绝缘层上形成第二绝缘层。在栅极图案之间形成低介电常数材料。

2. 发明申请

US20110318914A1 METHOD OF FABRICATING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20110318914A1
公开(公告)日：2011-12-29
申请号：US13168312
申请日：2011-06-24
申请人： Yong-lack Choi , Chang-hyun Cho , Seung-pil Chung , Hyun-seok Jang , Du-heon Song , Jung-dal Choi
发明人： Yong-lack Choi , Chang-hyun Cho , Seung-pil Chung , Hyun-seok Jang , Du-heon Song , Jung-dal Choi
IPC分类号： H01L21/283
CPC分类号： H01L21/7682 , H01L27/11521 , H01L27/11526
摘要： A method of fabricating a semiconductor device, in which an interference effect between word lines is substantially reduced or eliminated, includes forming a plurality of gate patterns on a substrate; forming a first insulating layer between the gate patterns, the first insulating layer filling a region between the gate patterns; etching the first insulating layer to remove a portion of the first insulating layer to a predetermined depth; and forming a second insulating layer on the gate patterns and the first insulating layer. A low-dielectric-constant material is formed between the gate patterns.
摘要翻译：一种制造半导体器件的方法，其中字线之间的干涉效应被显着地减少或消除，包括在衬底上形成多个栅极图案; 在所述栅极图案之间形成第一绝缘层，所述第一绝缘层填充所述栅极图案之间的区域; 蚀刻第一绝缘层以将第一绝缘层的一部分去除到预定深度; 以及在栅极图案和第一绝缘层上形成第二绝缘层。在栅极图案之间形成低介电常数材料。

3. 发明申请

US20050156272A1 Semiconductor devices having storage nodes 有权
标题翻译：具有存储节点的半导体器件
公开(公告)号：US20050156272A1
公开(公告)日：2005-07-21
申请号：US11077838
申请日：2005-03-11
申请人： Sang-hyeon Lee , Chang-hyun Cho , Yang-keun Park
发明人： Sang-hyeon Lee , Chang-hyun Cho , Yang-keun Park
IPC分类号： H01L27/108 , H01L21/02 , H01L21/44 , H01L21/8242 , H01L29/00 , H01L29/02
CPC分类号： H01L28/91 , H01L27/10814 , H01L27/10855 , H01L27/10885
摘要： A semiconductor device is manufactured by forming a first insulating layer on a semiconductor substrate. First contact pads and second contact pads are formed that penetrate through the first insulating layer and are electrically connected to the semiconductor substrate. A second insulating layer is formed that has guide contact holes that expose upper surfaces of the first contact pads. An etch stopper is formed on bottoms and sidewalls of the guide contact holes of the second insulating layer. Bit lines are formed that are electrically connected to the semiconductor substrate by the second contact pads. The bit lines are electrically isolated from the first contact pads.
摘要翻译：通过在半导体衬底上形成第一绝缘层来制造半导体器件。形成穿过第一绝缘层并与半导体衬底电连接的第一接触焊盘和第二接触焊盘。形成具有暴露第一接触垫的上表面的引导接触孔的第二绝缘层。在第二绝缘层的引导接触孔的底部和侧壁上形成蚀刻停止层。形成通过第二接触焊盘电连接到半导体衬底的位线。位线与第一接触焊盘电隔离。

4. 发明申请

US20110088496A1 HARMONIC DRIVE USING PROFILE SHIFTED GEAR 有权
标题翻译：谐波驱动使用轮廓变速齿轮
公开(公告)号：US20110088496A1
公开(公告)日：2011-04-21
申请号：US12991887
申请日：2008-07-03
申请人： Chang-hyun Cho , Munsang Kim
发明人： Chang-hyun Cho , Munsang Kim
IPC分类号： F16H55/14 , F16H1/32
CPC分类号： F16H49/001
摘要： A harmonic drive according to the present invention comprises a plurality of internal gears; a band type of flexible gear provided with teeth engaged with each of the internal gears on its outer circumferential surface, the flexible gear having a pitch circumference length shorter than that of said internal gears; and a wave generating part disposed on an inner side of said flexible gear, the wave generating part generating a plurality of harmonic motions by deforming said flexible gear as the wave generating part rotates. Further, said flexible gear is formed integrally to engage with said plurality of internal gears so that the plurality of harmonic motions are overlapped, and one or more of said plurality of internal gears and said flexible gear are formed of profile shifted gears.
摘要翻译：根据本发明的谐波驱动器包括多个内齿轮; 带状的柔性齿轮具有与其外圆周表面上的每个内齿轮啮合的齿，所述柔性齿轮具有比所述内齿轮短的节圆周长; 以及波形产生部，其设置在所述柔性齿轮的内侧，所述波发生部通过使波动发生部旋转而使所述柔性齿轮变形而产生多次谐波运动。此外，所述柔性齿轮一体地形成为与所述多个内齿轮啮合，使得多个谐波运动重叠，并且所述多个内齿轮和所述柔性齿轮中的一个或多个由轮廓移位齿轮形成。

5. 发明授权

US06902998B2 Methods of manufacturing semiconductor devices having storage nodes 失效
标题翻译：制造具有存储节点的半导体器件的方法
公开(公告)号：US06902998B2
公开(公告)日：2005-06-07
申请号：US10404401
申请日：2003-04-01
申请人： Sang-hyeon Lee , Chang-hyun Cho , Yang-keun Park
发明人： Sang-hyeon Lee , Chang-hyun Cho , Yang-keun Park
IPC分类号： H01L27/108 , H01L21/02 , H01L21/44 , H01L21/8242 , H01L29/00 , H01L29/02
CPC分类号： H01L28/91 , H01L27/10814 , H01L27/10855 , H01L27/10885
摘要： A semiconductor device is manufactured by forming a first insulating layer on a semiconductor substrate. First contact pads and second contact pads are formed that penetrate through the first insulating layer and are electrically connected to the semiconductor substrate. A second insulating layer is formed that has guide contact holes that expose upper surfaces of the first contact pads. An etch stopper is formed on bottoms and sidewalls of the guide contact holes of the second insulating layer. Bit lines are formed that are electrically connected to the semiconductor substrate by the second contact pads. The bit lines are electrically isolated from the first contact pads.
摘要翻译：通过在半导体衬底上形成第一绝缘层来制造半导体器件。形成穿过第一绝缘层并与半导体衬底电连接的第一接触焊盘和第二接触焊盘。形成具有暴露第一接触垫的上表面的引导接触孔的第二绝缘层。在第二绝缘层的引导接触孔的底部和侧壁上形成蚀刻停止层。形成通过第二接触焊盘电连接到半导体衬底的位线。位线与第一接触焊盘电隔离。

6. 发明授权

US08656800B2 Harmonic drive using profile shifted gear 有权
标题翻译：谐波驱动使用轮廓切换齿轮
公开(公告)号：US08656800B2
公开(公告)日：2014-02-25
申请号：US12991887
申请日：2008-07-03
申请人： Chang-hyun Cho , Munsang Kim
发明人： Chang-hyun Cho , Munsang Kim
IPC分类号： F16H57/00
CPC分类号： F16H49/001
摘要： A harmonic drive according to the present invention comprises a plurality of internal gears; a band type of flexible gear provided with teeth engaged with each of the internal gears on its outer circumferential surface, the flexible gear having a pitch circumference length shorter than that of said internal gears; and a wave generating part disposed on an inner side of said flexible gear, the wave generating part generating a plurality of harmonic motions by deforming said flexible gear as the wave generating part rotates. Further, said flexible gear is formed integrally to engage with said plurality of internal gears so that the plurality of harmonic motions are overlapped, and one or more of said plurality of internal gears and said flexible gear are formed of profile shifted gears.
摘要翻译：根据本发明的谐波驱动器包括多个内齿轮; 带状的柔性齿轮具有与其外圆周表面上的每个内齿轮啮合的齿，所述柔性齿轮具有比所述内齿轮短的节圆周长; 以及波形产生部，其设置在所述柔性齿轮的内侧，所述波发生部通过使波动发生部旋转而使所述柔性齿轮变形而产生多次谐波运动。此外，所述柔性齿轮一体地形成为与所述多个内齿轮啮合，使得多个谐波运动重叠，并且所述多个内齿轮和所述柔性齿轮中的一个或多个由轮廓移位齿轮形成。

7. 发明申请

US20070035318A1 Donut-type parallel probe card and method of testing semiconductor wafer using same 审中-公开
标题翻译：甜甜圈型并联探针卡和使用其测试半导体晶片的方法
公开(公告)号：US20070035318A1
公开(公告)日：2007-02-15
申请号：US11500466
申请日：2006-08-08
申请人： Sang-kyu Yoo , Sung-mo Kang , Chang-hyun Cho
发明人： Sang-kyu Yoo , Sung-mo Kang , Chang-hyun Cho
IPC分类号： G01R31/02
CPC分类号： G01R1/073
摘要： A donut-type parallel probe card comprises a main substrate and a plurality of probing blocks installed on a surface of the main substrate, wherein each probe block comprises a plurality of probes. The probing blocks are arranged to fill a first region having an oval shape and surrounding a second region, and no probing blocks are arranged within the second region.
摘要翻译：环形平行探针卡包括主衬底和安装在主衬底的表面上的多个探测块，其中每个探针块包括多个探针。探测块被布置成填充具有椭圆形并且围绕第二区域的第一区域，并且在第二区域内不布置探测块。

8. 发明授权

US5706293A Method of testing single-order address memory 失效
标题翻译：测试单次地址存储器的方法
公开(公告)号：US5706293A
公开(公告)日：1998-01-06
申请号：US650936
申请日：1996-05-17
申请人： Heon-cheol Kim , Ho-ryong Kim , Sang-hyeon Baeg , Chang-hyun Cho
发明人： Heon-cheol Kim , Ho-ryong Kim , Sang-hyeon Baeg , Chang-hyun Cho
IPC分类号： G06F11/22 , G11C29/10 , G06F11/00
CPC分类号： G11C29/10
摘要： The present invention provides a test method of SOA (Single-Order Addressed) memory utilizing address data backgrounds applied to memory circuits. A memory test operation is performed using a total of (log.sub.2 N+1) address data backgrounds on an SOA memory having N mutually different addresses. Each address data background is written and read, then the inversion is written and read. Finally the address data background is again written and read for a total of 6 N(log.sub.2 N+1) operations.
摘要翻译：本发明提供了利用应用于存储器电路的地址数据背景的SOA（单次寻址）存储器的测试方法。在具有N个相互不同的地址的SOA存储器上使用总共（log2N + 1）地址数据背景来执行存储器测试操作。写入和读取每个地址数据背景，然后写入和读取反转。最后，地址数据背景再次写入和读取总共6 N（log2N + 1）操作。

9. 发明授权

US06822335B2 Method for arranging wiring line including power reinforcing line and semiconductor device having power reinforcing line 有权
标题翻译：用于布置包括电力加强线的布线和具有电力加强线的半导体器件的方法
公开(公告)号：US06822335B2
公开(公告)日：2004-11-23
申请号：US10452096
申请日：2003-05-30
申请人： Won-suk Yang , Jae-young Lee , Chang-hyun Cho , Ki-nam Kim
发明人： Won-suk Yang , Jae-young Lee , Chang-hyun Cho , Ki-nam Kim
IPC分类号： H01L2131
CPC分类号： G11C7/06 , G11C5/14 , G11C11/4091
摘要： A method for arranging a power supply line in a semiconductor device including a plurality of memory cell array blocks and a semiconductor device are provided in order to supply stable operating voltages, such as a power supply voltage and a ground voltage, to a sense amplifier allocated to each of the plurality of memory cell array blocks. The method includes the steps of arranging a plurality of first interconnections that extend in one direction and are spaced apart from one another on a semiconductor substrate on which the plurality of memory cell array blocks are formed, forming a first insulating layer on the plurality of first interconnections, arranging a plurality of power reinforcing lines that extends in one direction and are spaced apart from one another on the plurality of first interconnections on the first insulating layer, forming a second insulating layer on the plurality of power reinforcing lines, and arranging a plurality of second interconnections that intersect the plurality of first interconnections and the plurality of power reinforcing lines on the second insulating layer. The plurality of second interconnections include a first group and a second group, and the second interconnections in the second group are electrically connected to the plurality of power reinforcing lines on the plurality of memory cell array blocks via contact plugs formed in the second insulating layer.
摘要翻译：提供了一种用于在包括多个存储单元阵列块和半导体器件的半导体器件中布置电源线的方法，以便向分配的读出放大器提供诸如电源电压和接地电压的稳定工作电压到多个存储单元阵列块中的每一个。该方法包括以下步骤：在形成有多个存储单元阵列块的半导体衬底上布置在一个方向上延伸并且彼此间隔开的多个第一互连，在多个第一绝缘层上形成第一绝缘层布置多个在一个方向上延伸并且在第一绝缘层上的多个第一互连上彼此间隔开的功率增强线，在多个功率增强线上形成第二绝缘层，并且布置多个的第二互连，其与第二绝缘层上的多个第一互连和多个功率增强线相交。多个第二互连包括第一组和第二组，并且第二组中的第二互连通过形成在第二绝缘层中的接触插塞电连接到多个存储单元阵列块上的多个功率增强线。

10. 发明授权

US06720276B2 Methods of forming spin on glass layers by curing remaining portions thereof 有权
标题翻译：通过固化其余部分在玻璃层上形成自旋的方法
公开(公告)号：US06720276B2
公开(公告)日：2004-04-13
申请号：US10060486
申请日：2002-01-30
申请人： Min-hee Cho , Chang-hyun Cho , Soo-ho Shin , Hong-sik Jeong
发明人： Min-hee Cho , Chang-hyun Cho , Soo-ho Shin , Hong-sik Jeong
IPC分类号： H01L2131
CPC分类号： H01L21/31144 , H01L21/31138 , H01L21/316 , H01L21/76802 , H01L21/76814 , H01L21/76826 , H01L21/76828 , H01L21/76829
摘要： Methods of forming a spin-on-glass (SOG) layer are disclosed. An SOG layer is formed on an integrated circuit substrate. A first curing process is performed on the SOG layer. Less than all of the SOG layer is removed from the integrated circuit substrate through a mask pattern on the SOG layer to provide a remaining portion of the SOG layer on the integrated circuit substrate. A second curing process is performed on the SOG layer. The remaining portion of the SOG layer is removed to expose the integrated circuit substrate.
摘要翻译：公开了形成旋涂玻璃（SOG）层的方法。在集成电路基板上形成SOG层。在SOG层上进行第一固化过程。通过SOG层上的掩模图案，从集成电路衬底去除少于所有的SOG层，以在集成电路衬底上提供SOG层的剩余部分。在SOG层上进行第二次固化处理。去除SOG层的剩余部分以暴露集成电路基板。

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