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1. 发明授权

US06951787B2 Capacitor with stoichiometrically adjusted dielectric and method of fabricating same 失效
公开(公告)号：US06951787B2
公开(公告)日：2005-10-04
申请号：US10382709
申请日：2003-03-06
申请人： Derryl D. J. Allman , Nabil Mansour , Ponce Saopraseuth
发明人： Derryl D. J. Allman , Nabil Mansour , Ponce Saopraseuth
IPC分类号： C23C16/34 , C23C16/52 , H01L21/02 , H01L21/318 , H01L21/8242 , H01L21/31
CPC分类号： H01L21/3185 , C23C16/345 , C23C16/52 , H01L28/40
摘要： A capacitor and a capacitor dielectric material are fabricated by adjusting the amount of an ionic conductive species, such as hydrogen, contained in the capacitor dielectric material to obtain predetermined electrical or functional characteristics. Forming the capacitor dielectric material from silicon, nitrogen and hydrogen allows a stoichiometric ratio control of silicon to nitrogen to limit the amount of hydrogen. Forming the capacitor by dielectric material plasma enhanced chemical vapor deposition (PECVD) allows hydrogen bonds to be broken by ionic bombardment, so that stoichiometric control is achieved by controlling the power of the PECVD. Applying a predetermined number of thermal cycles of temperature elevation and temperature reduction also breaks the hydrogen bonds to control the amount of the hydrogen in the formed capacitor dielectric material.

2. 发明授权

US06566186B1 Capacitor with stoichiometrically adjusted dielectric and method of fabricating same 有权
公开(公告)号：US06566186B1
公开(公告)日：2003-05-20
申请号：US09573137
申请日：2000-05-17
申请人： Derryl D. J. Allman , Nabil Mansour , Ponce Saopraseuth
发明人： Derryl D. J. Allman , Nabil Mansour , Ponce Saopraseuth
IPC分类号： H01L2131
CPC分类号： H01L21/3185 , C23C16/345 , C23C16/52 , H01L28/40
摘要： A capacitor and a capacitor dielectric material are fabricated by adjusting the amount of an ionic conductive species, such as hydrogen, contained in the capacitor dielectric material to obtain predetermined electrical or functional characteristics. Forming the capacitor dielectric material from silicon, nitrogen and hydrogen allows a stoichiometric ratio control of silicon to nitrogen to limit the amount of hydrogen. Forming the capacitor by dielectric material plasma enhanced chemical vapor deposition (PECVD) allows hydrogen bonds to be broken by ionic bombardment, so that stoichiometric control is achieved by controlling the power of the PECVD. Applying a predetermined number of thermal cycles of temperature elevation and temperature reduction also breaks the hydrogen bonds to control the amount of the hydrogen in the formed capacitor dielectric material.

3. 发明授权

US06583026B1 Process for forming a low k carbon-doped silicon oxide dielectric material on an integrated circuit structure 有权
标题翻译：在集成电路结构上形成低k碳掺杂氧化硅介电材料的工艺
公开(公告)号：US06583026B1
公开(公告)日：2003-06-24
申请号：US09872058
申请日：2001-05-31
申请人： Derryl D. J. Allman , Ponce Saopraseuth , Hemanshu D. Bhatt
发明人： Derryl D. J. Allman , Ponce Saopraseuth , Hemanshu D. Bhatt
IPC分类号： H01L2176
CPC分类号： H01L21/02126 , C23C16/401 , H01L21/02211 , H01L21/0228 , H01L21/02304 , H01L21/0234 , H01L21/31633
摘要： A process for forming a low k carbon-doped silicon oxide dielectric material (lkc-dsodm) on an integrated circuit structure is characterized by improved planarity and good gap fill in high aspect ratio regions of the integrated circuit structure, as well as improved film strength and adherence, and less byproducts trapped in the film. The process comprises: depositing a plurality of layers of lkc-dsodm on an integrated circuit structure in a reactor; and pausing after depositing each layer of lkc-dsodm and before depositing a further layer of lkc-dsodm. The process can further include first forming a base or barrier layer of a silicon-rich and nitrogen-rich dielectric material over the integrated circuit structure, plasma etching the upper surface of the barrier layer to facilitate adhesion of the subsequently deposited lkc-dsodm to the barrier layer, and then, before depositing the first layer of lkc-dsodm, cooling the etched barrier layer down to within 10° C. or less of the subsequent deposition temperature used for formation of the film of lkc-dsodm. In another aspect of the invention the pausing step further includes, before deposition of the next layer of lkc-dsodm, flowing a source of non-reactive gas over the surface of the newly deposited layer of lkc-dsodm to facilitate outgassing and removal of byproducts resulting from the preceding formation and deposition of lkc-dsodm.
摘要翻译：在集成电路结构上形成低k碳掺杂氧化硅电介质材料（lkc-dsodm）的方法的特征在于集成电路结构的高纵横比区域中的平坦度和良好的间隙填充，以及改进的膜强度和坚持，更少的副产品被困在电影中。该方法包括：在反应器中的集成电路结构上沉积多层lkc-dsodm; 并且在沉积每层lkc-dsodm之后并在沉积另外一层lkc-dsodm之前暂停。该方法还可以包括首先在集成电路结构上形成富硅和富氮介电材料的基底或阻挡层，等离子体蚀刻阻挡层的上表面，以便于随后沉积的lkc-dsodm粘附到然后在沉积第一层lkc-dsodm之前，将蚀刻的阻挡层冷却到用于形成lkc-dsodm膜的后续沉积温度的10℃以内。在本发明的另一方面，暂停步骤还包括在沉积下一层lkc-dsodm之前，将非反应性气体源流过新沉积的lkc-dsodm层的表面以便于除气和除去副产物由于以前的lkc-dsodm的形成和沉积而产生。

4. 发明授权

US06562735B1 Control of reaction rate in formation of low k carbon-containing silicon oxide dielectric material using organosilane, unsubstituted silane, and hydrogen peroxide reactants 有权
标题翻译：使用有机硅烷，未取代的硅烷和过氧化氢反应物控制形成低k含碳氧化硅电介质材料的反应速率
公开(公告)号：US06562735B1
公开(公告)日：2003-05-13
申请号：US10015255
申请日：2001-12-11
申请人： Derryl D. J. Allman , Ponce Saopraseuth
发明人： Derryl D. J. Allman , Ponce Saopraseuth
IPC分类号： H01L2131
CPC分类号： H01L21/02126 , C23C16/401 , H01L21/02211 , H01L21/02271 , H01L21/31633
摘要： Control of a reaction between a peroxide oxidizing agent and a carbon-substituted silane to form a low k carbon-containing silicon oxide dielectric material is achieved, in a first embodiment, by adding, to the carbon-substituted silane reactant, silane (SiH4), to accelerate the process for forming a low k carbon-containing silicon oxide dielectric material by reaction of the carbon-substituted silane/silane mixture with hydrogen peroxide. Also, control of a reaction between a peroxide oxidizing agent and a carbon-substituted silane to form a low k carbon-containing silicon oxide dielectric material is achieved by controlling the ratio of the flow of the hydrogen peroxide reactant and the flow of the reactant mixture of carbon-substituted silane and unsubstituted silane into the reaction chamber though structural modification of the faceplate (showerhead) through which the reactants flow into the chamber.
摘要翻译：在第一实施方案中，通过向碳取代的硅烷反应物中加入硅烷（SiH 4），可以控制过氧化物氧化剂和碳取代的硅烷反应形成低k碳氧化硅介电材料，，通过碳取代的硅烷/硅烷混合物与过氧化氢的反应来加速形成低k碳氧化硅电介质材料的工艺。另外，通过控制过氧化氢反应物的流量和反应物混合物的流量来控制过氧化物氧化剂和碳取代的硅烷之间的反应以形成低k碳氧化硅电介质材料的碳取代的硅烷和未取代的硅烷通过面板（喷头）的结构改性而进入反应室，反应物通过这些结构改变流入室中。

5. 发明授权

US06562700B1 Process for removal of resist mask over low k carbon-doped silicon oxide dielectric material of an integrated circuit structure, and removal of residues from via etch and resist mask removal 有权
标题翻译：用于在集成电路结构的低k碳掺杂氧化硅介电材料上去除抗蚀剂掩模的工艺，以及从通孔蚀刻和抗蚀剂掩模去除中除去残余物
公开(公告)号：US06562700B1
公开(公告)日：2003-05-13
申请号：US09873043
申请日：2001-05-31
申请人： Sam Gu , David Pritchard , Derryl D. J. Allman , Ponce Saopraseuth , Steve Reder
发明人： Sam Gu , David Pritchard , Derryl D. J. Allman , Ponce Saopraseuth , Steve Reder
IPC分类号： H01L21322
CPC分类号： H01L21/31138 , H01L21/02052 , H01L21/31633
摘要： A process is disclosed for removing a photoresist mask used to form openings in an underlying layer of low k carbon-doped silicon oxide dielectric material of an integrated circuit structure formed on a semiconductor substrate, which comprises exposing the photoresist mask in a plasma reactor to a plasma formed using a reducing gas until the photoresist mask is removed. In a preferred embodiment the reducing gas is selected from the group consisting of NH3, H2, forming gas, and a mixture of NH3 and H2. The process further provides for the removal of etch residues by first contacting the low k carbon-doped silicon oxide dielectric material with a solvent capable of dissolving and/or removing etch residues left from forming the openings in the low k dielectric material, and from removing the photoresist mask used to form the openings in the low k carbon-doped silicon oxide dielectric material; and then annealing the substrate in an annealing chamber at a temperature sufficient to remove liquid and gaseous byproducts from the low k carbon-doped silicon oxide dielectric material.
摘要翻译：公开了一种用于去除在半导体衬底上形成的集成电路结构的低k碳掺杂氧化硅介电材料的下层中形成开口的光刻胶掩模的方法，其包括将等离子体反应器中的光刻胶掩模曝光于使用还原气体形成的等离子体直到除去光致抗蚀剂掩模。在优选的实施方案中，还原气体选自NH 3，H 2，形成气体和NH 3和H 2的混合物。该方法还通过首先使低k碳掺杂的氧化硅介电材料与能够溶解和/或去除在低k电介质材料中形成开口所留下的蚀刻残留物的溶剂和除去用于在低k碳掺杂氧化硅电介质材料中形成开口的光致抗蚀剂掩模; 然后在退火室中以足以从低k碳掺杂的氧化硅介电材料除去液体和气体副产物的温度退火衬底。

6. 发明申请

US20080132065A1 METHOD FOR REDIRECTING VOID DIFFUSION AWAY FROM VIAS IN AN INTEGRATED CIRCUIT DESIGN 失效
标题翻译：在集成电路设计中从VIAS重新排列无声扩散的方法
公开(公告)号：US20080132065A1
公开(公告)日：2008-06-05
申请号：US12018849
申请日：2008-01-24
申请人： Derryl D. J. Allman , Hemanshu D. Bhatt , Charles E. May , Peter Austin Burke , Byung-Sung Kwak , Sey-Shing Sun , David T. Price , David Pritchard
发明人： Derryl D. J. Allman , Hemanshu D. Bhatt , Charles E. May , Peter Austin Burke , Byung-Sung Kwak , Sey-Shing Sun , David T. Price , David Pritchard
IPC分类号： H01L21/44
CPC分类号： H01L21/76838 , H01L24/02 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/14
摘要： A method for redirecting void diffusion away from vias in an integrated circuit design includes steps of forming an electrical conductor in a first electrically conductive layer of an integrated circuit design, forming a via between a distal end of the electrical conductor and a second electrically conductive layer of the integrated circuit design, and reducing tensile stress in the electrical conductor to divert void diffusion away from the via.
摘要翻译：在集成电路设计中将空隙扩散转向远离通孔的方法包括在集成电路设计的第一导电层中形成电导体的步骤，在电导体的远端和第二导电层之间形成通孔的集成电路设计，并且减小电导体中的拉伸应力以将空隙扩散转移离开通孔。

7. 发明授权

US06504250B1 Integrated circuit device with reduced cross talk 失效
公开(公告)号：US06504250B1
公开(公告)日：2003-01-07
申请号：US09695598
申请日：2000-10-23
申请人： Derryl D. J. Allman , Kenneth P. Fuchs , Gayle W. Miller , Samuel C. Gioia
发明人： Derryl D. J. Allman , Kenneth P. Fuchs , Gayle W. Miller , Samuel C. Gioia
IPC分类号： H01L2348
CPC分类号： H01L23/3171 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： A low dielectric material is applied, as by spinning on, over the passivation layer of a semiconductor chip to fill the gaps which may exist between the top layer metal lines, and thereby minimize the possibility of cross talk which might otherwise be present between those lines.

8. 发明授权

US06504202B1 Interconnect-embedded metal-insulator-metal capacitor 有权
标题翻译：互连嵌入式金属 - 绝缘体 - 金属电容器
公开(公告)号：US06504202B1
公开(公告)日：2003-01-07
申请号：US09496971
申请日：2000-02-02
申请人： Derryl D. J. Allman , Kenneth Fuchs
发明人： Derryl D. J. Allman , Kenneth Fuchs
IPC分类号： H01L2976
CPC分类号： H01L28/40 , H01L21/768 , H01L28/75
摘要： A metal-insulator-metal capacitor is embedded in an interconnect layer of an integrated circuit (IC). The interconnect layer has a cavity, and the capacitor is formed in the cavity with one of the plates of the capacitor integral with a conductive layer of the interconnect layer, so the capacitor plate electrically communicates with the interconnect layer. The interconnect layer has multiple conductive layers, including a layer, such as aluminum, that is subject to deformation at certain temperatures during fabrication of the IC, and the cavity extends through this layer. A remaining conductive layer of the interconnect layer defines one of the capacitor plates, and a dielectric layer and another capacitor plate are formed thereon within the cavity. Via interconnects of about the same length electrically connect to the top plate and through the interconnect layer to the bottom plate.
摘要翻译：金属 - 绝缘体 - 金属电容器嵌入在集成电路（IC）的互连层中。互连层具有空腔，并且电容器形成在空腔中，电容器的一个板与互连层的导电层成一体，因此电容器板与互连层电连通。互连层具有多个导电层，包括在制造IC期间在特定温度下经受变形的诸如铝的层，并且空腔延伸穿过该层。互连层的剩余导电层限定电容器板中的一个，并且在腔内形成介电层和另一电容器板。通过大致相同长度的互连电连接到顶板并且通过互连层连接到底板。

9. 发明授权

US06448653B1 Method for using low dielectric constant material in integrated circuit fabrication 失效
标题翻译：在集成电路制造中使用低介电常数材料的方法
公开(公告)号：US06448653B1
公开(公告)日：2002-09-10
申请号：US09694993
申请日：2000-10-23
申请人： Derryl D. J. Allman , Kenneth P. Fuchs , Gayle W. Miller , Samuel C. Gioia
发明人： Derryl D. J. Allman , Kenneth P. Fuchs , Gayle W. Miller , Samuel C. Gioia
IPC分类号： H01L2348
CPC分类号： H01L23/3171 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： A low dielectric material is applied, as by spinning on, over the passivation layer of a semiconductor chip to fill the gaps which may exist between the top layer metal lines, and thereby minimize the possibility of cross talk which might otherwise be present between those lines.
摘要翻译：通过旋转在半导体芯片的钝化层上施加低电介质材料以填充可能存在于顶层金属线之间的间隙，从而最小化可能存在于这些线之间的串扰的可能性。

10. 发明授权

US6136662A Semiconductor wafer having a layer-to-layer alignment mark and method for fabricating the same 有权
标题翻译：具有层间对准标记的半导体晶片及其制造方法
公开(公告)号：US6136662A
公开(公告)日：2000-10-24
申请号：US311253
申请日：1999-05-13
申请人： Derryl D. J. Allman , Curtis C. Hainds , Charles W. Jurgensen , Brian R. Lee
发明人： Derryl D. J. Allman , Curtis C. Hainds , Charles W. Jurgensen , Brian R. Lee
IPC分类号： G03F9/00 , H01L23/544 , H01L21/76 , H01L21/302 , H01L21/4763
CPC分类号： G03F9/708 , G03F9/7084 , H01L23/544 , H01L2223/5442 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , Y10S438/975
摘要： A method of creating a layer-to-layer alignment mark in a semiconductor wafer includes the step of depositing a first conductor layer on a substrate associated with the semiconductor wafer. The method also includes the step of fabricating a number of alignment trenches in the first conductor layer. Moreover, the method includes the step of depositing a first insulator layer on the first conductor layer so as to fill the number of alignment trenches. Yet further, the method includes the step of removing material associated with the first insulator layer from the number of alignment trenches such that an upper surface of the first conductor layer and an upper surface of the first insulator layer define a first alignment step feature which possesses a predetermined height. The method also includes the step of depositing a second conductor layer on the semiconductor wafer subsequent to the removing step. A semiconductor wafer is also disclosed.
摘要翻译：在半导体晶片中形成层间对准标记的方法包括在与半导体晶片相关联的衬底上沉积第一导体层的步骤。该方法还包括在第一导体层中制造多个对准沟槽的步骤。此外，该方法包括在第一导体层上沉积第一绝缘体层以填充对准沟槽的数量的步骤。此外，该方法包括以下步骤：从对准沟槽的数量去除与第一绝缘体层相关联的材料，使得第一导体层的上表面和第一绝缘体层的上表面限定第一对准步骤特征，其具有一个预定的高度。该方法还包括在去除步骤之后在半导体晶片上沉积第二导体层的步骤。还公开了半导体晶片。

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