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1. 发明申请

US20080132065A1 METHOD FOR REDIRECTING VOID DIFFUSION AWAY FROM VIAS IN AN INTEGRATED CIRCUIT DESIGN 失效
标题翻译：在集成电路设计中从VIAS重新排列无声扩散的方法
公开(公告)号：US20080132065A1
公开(公告)日：2008-06-05
申请号：US12018849
申请日：2008-01-24
申请人： Derryl D. J. Allman , Hemanshu D. Bhatt , Charles E. May , Peter Austin Burke , Byung-Sung Kwak , Sey-Shing Sun , David T. Price , David Pritchard
发明人： Derryl D. J. Allman , Hemanshu D. Bhatt , Charles E. May , Peter Austin Burke , Byung-Sung Kwak , Sey-Shing Sun , David T. Price , David Pritchard
IPC分类号： H01L21/44
CPC分类号： H01L21/76838 , H01L24/02 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/14
摘要： A method for redirecting void diffusion away from vias in an integrated circuit design includes steps of forming an electrical conductor in a first electrically conductive layer of an integrated circuit design, forming a via between a distal end of the electrical conductor and a second electrically conductive layer of the integrated circuit design, and reducing tensile stress in the electrical conductor to divert void diffusion away from the via.
摘要翻译：在集成电路设计中将空隙扩散转向远离通孔的方法包括在集成电路设计的第一导电层中形成电导体的步骤，在电导体的远端和第二导电层之间形成通孔的集成电路设计，并且减小电导体中的拉伸应力以将空隙扩散转移离开通孔。

2. 发明授权

US07582566B2 Method for redirecting void diffusion away from vias in an integrated circuit design 失效
标题翻译：在集成电路设计中将空隙扩散远离过孔的方法
公开(公告)号：US07582566B2
公开(公告)日：2009-09-01
申请号：US12018849
申请日：2008-01-24
申请人： Derryl D. J. Allman , Hemanshu D. Bhatt , Charles E. May , Peter Austin Burke , Byung-Sung Kwak , Sey-Shing Sun , David T. Price , David Pritchard
发明人： Derryl D. J. Allman , Hemanshu D. Bhatt , Charles E. May , Peter Austin Burke , Byung-Sung Kwak , Sey-Shing Sun , David T. Price , David Pritchard
IPC分类号： H01L21/311
CPC分类号： H01L21/76838 , H01L24/02 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/14
摘要： A method for redirecting void diffusion away from vias in an integrated circuit design includes steps of forming an electrical conductor in a first electrically conductive layer of an integrated circuit design, forming a via between a distal end of the electrical conductor and a second electrically conductive layer of the integrated circuit design, and reducing tensile stress in the electrical conductor to divert void diffusion away from the via.
摘要翻译：在集成电路设计中将空隙扩散转向远离通孔的方法包括在集成电路设计的第一导电层中形成电导体的步骤，在电导体的远端和第二导电层之间形成通孔的集成电路设计，并且减小电导体中的拉伸应力以将空隙扩散转移离开通孔。

3. 发明授权

US07436040B2 Method and apparatus for diverting void diffusion in integrated circuit conductors 有权
标题翻译：用于在集成电路导体中转移空穴扩散的方法和装置
公开(公告)号：US07436040B2
公开(公告)日：2008-10-14
申请号：US11323398
申请日：2005-12-29
申请人： Derryl D. J. Allman , Hemanshu D. Bhatt , Charles E. May , Peter Austin Burke , Byung-Sung Kwak , Sey-Shing Sun , David T. Price , David Pritchard
发明人： Derryl D. J. Allman , Hemanshu D. Bhatt , Charles E. May , Peter Austin Burke , Byung-Sung Kwak , Sey-Shing Sun , David T. Price , David Pritchard
IPC分类号： H01L23/58
CPC分类号： H01L21/7682 , H01L21/76808 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A method of diverting void diffusion in an integrated circuit includes steps of forming an electrical conductor having a boundary in a first electrically conductive layer of an integrated circuit, forming a via inside the boundary of the electrical conductor in a dielectric layer between the first electrically conductive layer and a second electrically conductive layer of the integrated circuit, and forming a slot between the via and the boundary of the electrical conductor for diverting void diffusion in the electrical conductor away from the via.
摘要翻译：在集成电路中转移空穴扩散的方法包括以下步骤：在集成电路的第一导电层中形成具有边界的电导体，在电介质层的边界内在第一导电层和第二导电层，并且在电导体的通孔和边界之间形成槽，用于将电导体中的空隙扩散转移离开通孔。

4. 发明授权

US07361965B2 Method and apparatus for redirecting void diffusion away from vias in an integrated circuit design 有权
标题翻译：在集成电路设计中将空隙扩散远离过孔的方法和装置
公开(公告)号：US07361965B2
公开(公告)日：2008-04-22
申请号：US11323400
申请日：2005-12-29
申请人： Derryl D. J. Allman , Hemanshu D. Bhatt , Charles E. May , Peter Austin Burke , Byung-Sung Kwak , Sey-Shing Sun , David T. Price , David Pritchard
发明人： Derryl D. J. Allman , Hemanshu D. Bhatt , Charles E. May , Peter Austin Burke , Byung-Sung Kwak , Sey-Shing Sun , David T. Price , David Pritchard
IPC分类号： H01L23/58
CPC分类号： H01L21/76838 , H01L24/02 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/14
摘要： A method and apparatus for redirecting void diffusion away from vias in an integrated circuit design includes steps of forming an electrical conductor in a first electrically conductive layer of an integrated circuit design, forming a via between a distal end of the electrical conductor and a second electrically conductive layer of the integrated circuit design, and reducing tensile stress in the electrical conductor to divert void diffusion away from the via.
摘要翻译：用于在集成电路设计中将空隙扩散转向远离通孔的方法和装置包括在集成电路设计的第一导电层中形成电导体的步骤，在电导体的远端和第二电导体之间形成通孔集成电路设计的导电层，并且减小电导体中的拉伸应力以将空隙扩散转移离开通孔。

5. 发明授权

US07915122B2 Self-aligned cell integration scheme 失效
标题翻译：自对准单元集成方案
公开(公告)号：US07915122B2
公开(公告)日：2011-03-29
申请号：US11312849
申请日：2005-12-20
申请人： Richard J. Carter , Hemanshu D. Bhatt , Shiqun Gu , Peter A. Burke , James R. B. Elmer , Sey-Shing Sun , Byung-Sung Kwak , Verne Hornback
发明人： Richard J. Carter , Hemanshu D. Bhatt , Shiqun Gu , Peter A. Burke , James R. B. Elmer , Sey-Shing Sun , Byung-Sung Kwak , Verne Hornback
IPC分类号： H01L21/336
CPC分类号： H01L51/0018 , B82Y10/00 , H01L27/283 , H01L51/0048 , H01L51/0545 , Y10S977/742
摘要： A method of forming a self-aligned logic cell. A nanotube layer is formed over the bottom electrode. A clamp layer is formed over the nanotube layer. The clamp layer covers the nanotube layer, thereby protecting the nanotube layer. A dielectric layer is formed over the clamp layer. The dielectric layer is etched. The clamp layer provides an etch stop and protects the nanotube layer. The clamp layer is etched with an isotropic etchant that etches the clamp layer underneath the dielectric layer, creating an overlap of the dielectric layer, and causing a self-alignment between the clamp layer and the dielectric layer. A spacer layer is formed over the nanotube layer. The spacer layer is etched except for a ring portion around the edge of the dielectric layer. The nanotube layer is etched except for portions that are underlying at least one of the clamp layer, the dielectric layer, and the spacer layer, thereby causing a self-alignment between the clamp layer, the overlap to the dielectric layer, the spacer layer, and the nanotube layer.
摘要翻译：一种形成自对准逻辑单元的方法。在底部电极上形成纳米管层。在纳米管层上形成夹层。夹层覆盖纳米管层，从而保护纳米管层。在钳位层上形成电介质层。蚀刻介电层。钳位层提供蚀刻停止并保护纳米管层。用各向同性蚀刻剂蚀刻钳夹层，蚀刻介质层下方的夹层，产生电介质层的重叠，并引起钳位层和电介质层之间的自对准。在纳米管层上形成间隔层。除了围绕电介质层的边缘的环形部分之外，蚀刻间隔层。除了夹持层，电介质层和间隔层中的至少一个的部分以外，蚀刻纳米管层，从而导致夹紧层之间的自对准，与电介质层的重叠，间隔层，和纳米管层。

6. 发明申请

US20070259518A1 Method and apparatus for diverting void diffusion in integrated circuit conductors 有权
标题翻译：用于在集成电路导体中转移空穴扩散的方法和装置
公开(公告)号：US20070259518A1
公开(公告)日：2007-11-08
申请号：US11323398
申请日：2005-12-29
申请人： Derryl Allman , Hemanshu Bhatt , Charles May , Peter Burke , Byung-Sung Kwak , Sey-Shing Sun , David Price , David Pritchard
发明人： Derryl Allman , Hemanshu Bhatt , Charles May , Peter Burke , Byung-Sung Kwak , Sey-Shing Sun , David Price , David Pritchard
IPC分类号： H01L29/06 , H01L21/4763 , H01L21/768
CPC分类号： H01L21/7682 , H01L21/76808 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A method of diverting void diffusion in an integrated circuit includes steps of forming an electrical conductor having a boundary in a first electrically conductive layer of an integrated circuit, forming a via inside the boundary of the electrical conductor in a dielectric layer between the first electrically conductive layer and a second electrically conductive layer of the integrated circuit, and forming a slot between the via and the boundary of the electrical conductor for diverting void diffusion in the electrical conductor away from the via.
摘要翻译：在集成电路中转移空穴扩散的方法包括以下步骤：在集成电路的第一导电层中形成具有边界的电导体，在电介质层的边界内在第一导电层和第二导电层，并且在电导体的通孔和边界之间形成槽，用于将电导体中的空隙扩散转移离开通孔。

7. 发明申请

US20070155160A1 Method and apparatus for redirecting void diffusion away from vias in an integrated circuit design 有权
标题翻译：在集成电路设计中将空隙扩散远离过孔的方法和装置
公开(公告)号：US20070155160A1
公开(公告)日：2007-07-05
申请号：US11323400
申请日：2005-12-29
申请人： Derryl Allman , Hemanshu Bhatt , Charles May , Peter Burke , Byung-Sung Kwak , Sey-Shing Sun , David Price , David Pritchard
发明人： Derryl Allman , Hemanshu Bhatt , Charles May , Peter Burke , Byung-Sung Kwak , Sey-Shing Sun , David Price , David Pritchard
IPC分类号： H01L21/4763
CPC分类号： H01L21/76838 , H01L24/02 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/14
摘要： A method and apparatus for redirecting void diffusion away from vias in an integrated circuit design includes steps of forming an electrical conductor in a first electrically conductive layer of an integrated circuit design, forming a via between a distal end of the electrical conductor and a second electrically conductive layer of the integrated circuit design, and reducing tensile stress in the electrical conductor to divert void diffusion away from the via.
摘要翻译：用于在集成电路设计中将空隙扩散转向远离通孔的方法和装置包括在集成电路设计的第一导电层中形成电导体的步骤，在电导体的远端和第二电导体之间形成通孔集成电路设计的导电层，并且减小电导体中的拉伸应力以将空隙扩散转移离开通孔。

8. 发明申请

US20060281256A1 Self-aligned cell integration scheme 失效
标题翻译：自对准单元集成方案
公开(公告)号：US20060281256A1
公开(公告)日：2006-12-14
申请号：US11312849
申请日：2005-12-20
申请人： Richard Carter , Hemanshu Bhatt , Shiqun Gu , Peter Burke , James Elmer , Sey-Shing Sun , Byung-Sung Kwak , Verne Hornback
发明人： Richard Carter , Hemanshu Bhatt , Shiqun Gu , Peter Burke , James Elmer , Sey-Shing Sun , Byung-Sung Kwak , Verne Hornback
IPC分类号： H01L21/336
CPC分类号： H01L51/0018 , B82Y10/00 , H01L27/283 , H01L51/0048 , H01L51/0545 , Y10S977/742
摘要： A method of forming a self-aligned logic cell. A nanotube layer is formed over the bottom electrode. A clamp layer is formed over the nanotube layer. The clamp layer covers the nanotube layer, thereby protecting the nanotube layer. A dielectric layer is formed over the clamp layer. The dielectric layer is etched. The clamp layer provides an etch stop and protects the nanotube layer. The clamp layer is etched with an isotropic etchant that etches the clamp layer underneath the dielectric layer, creating an overlap of the dielectric layer, and causing a self-alignment between the clamp layer and the dielectric layer. A spacer layer is formed over the nanotube layer. The spacer layer is etched except for a ring portion around the edge of the dielectric layer. The nanotube layer is etched except for portions that are underlying at least one of the clamp layer, the dielectric layer, and the spacer layer, thereby causing a self-alignment between the clamp layer, the overlap to the dielectric layer, the spacer layer, and the nanotube layer.
摘要翻译：一种形成自对准逻辑单元的方法。在底部电极上形成纳米管层。在纳米管层上形成夹层。夹层覆盖纳米管层，从而保护纳米管层。在钳位层上形成电介质层。蚀刻介电层。钳位层提供蚀刻停止并保护纳米管层。用各向同性蚀刻剂蚀刻钳夹层，蚀刻介质层下方的夹层，产生电介质层的重叠，并引起钳位层和电介质层之间的自对准。在纳米管层上形成间隔层。除了围绕电介质层的边缘的环形部分之外，蚀刻间隔层。除了夹持层，电介质层和间隔层中的至少一个的部分以外，蚀刻纳米管层，从而导致夹紧层之间的自对准，与电介质层的重叠，间隔层，和纳米管层。

9. 发明申请

US20050224358A1 Method for improved local planarity control during electropolishing 审中-公开
标题翻译：在电抛光过程中改进局部平面度控制的方法
公开(公告)号：US20050224358A1
公开(公告)日：2005-10-13
申请号：US10814059
申请日：2004-03-30
申请人： Byung-Sung Kwak , Jayanthi Pallinti , Sey-Shing Sun , William Barth , Wilbur Catabay
发明人： Byung-Sung Kwak , Jayanthi Pallinti , Sey-Shing Sun , William Barth , Wilbur Catabay
IPC分类号： C25D3/02 , C25D5/02 , C25D5/18 , C25D7/12 , C25D17/00 , H01L21/288 , H01L21/321 , H01L21/768
CPC分类号： H01L21/7684 , C25D3/02 , C25D5/18 , C25D7/123 , C25D17/001 , H01L21/2885 , H01L21/32115 , H01L21/76877
摘要： A metal layer formed on a semiconductor wafer is planarized by applying sequentially a deplating step, a plating step, and a relaxation step in a removal cycle. A series of cycles are performed sequentially in one embodiment to comprise a pass. The removal cycle is repeated in sequence until the pass is completed. The respective deplating and plating rates are adjusted so that the ratios of deplating rates to plating rates progressively decrease from an initial pass to a final pass. Organic additives are added to the electrolytic plating solution to control the plating portion of the cycle in a topography dependant fashion.
摘要翻译：通过在去除循环中依次应用脱铝步骤，电镀步骤和弛豫步骤来平坦化在半导体晶片上形成的金属层。在一个实施例中，顺序执行一系列循环以包括通过。删除循环按顺序重复，直到通过完成。调整各自的脱镀和电镀速率，使得脱铝速率与电镀速率的比率从初始通过到最终通过逐渐降低。将有机添加剂添加到电解电镀溶液中以以地形依赖的方式控制循环的电镀部分。

10. 发明申请

US20060063375A1 Integrated barrier and seed layer for copper interconnect technology 有权
标题翻译：铜互连技术的集成屏障和种子层
公开(公告)号：US20060063375A1
公开(公告)日：2006-03-23
申请号：US10945777
申请日：2004-09-20
申请人： Sey-Shing Sun , Byung-Sung Kwak , Peter Burke
发明人： Sey-Shing Sun , Byung-Sung Kwak , Peter Burke
IPC分类号： H01L21/4763
CPC分类号： H01L21/76844 , H01L21/76843 , H01L21/76846 , H01L21/76871 , H01L21/76873 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An integrated barrier and seed layer that is useful for creating conductive pathways in semiconductor devices. The barrier portion of the integrated layer prevents diffusion of the conductive material into the underlying dielectric substrate while the seed portion provides an appropriate foundation upon which to deposit the conductive material. The barrier portion of the integrated layer is formed of a metal nitride, while the seed portion is formed of ruthenium or a ruthenium alloy. The metal nitride forms an effective barrier layer while the ruthenium or ruthenium alloy forms an effective seed layer for a metal such as copper. In some embodiments, the integrated layer is formed in a way so that its composition changes gradually from one region to the next.
摘要翻译：集成的屏障和种子层，可用于在半导体器件中产生导电通路。集成层的阻挡部分防止导电材料扩散到下面的电介质基底中，同时种子部分提供了沉积导电材料的适当基础。集成层的阻挡部分由金属氮化物形成，而种子部分由钌或钌合金形成。金属氮化物形成有效的阻挡层，而钌或钌合金形成金属如铜的有效晶种层。在一些实施例中，集成层以使其组成从一个区域逐渐变化到下一个区域的方式形成。

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