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1. 发明申请

US20140084363A1 MOS TRANSISTOR STRUCTURE 有权
标题翻译： MOS晶体管结构
公开(公告)号：US20140084363A1
公开(公告)日：2014-03-27
申请号：US13627912
申请日：2012-09-26
申请人： Jeffrey Pearse , Prasad Venkatraman , James Sellers , Hemanshu D. Bhatt
发明人： Jeffrey Pearse , Prasad Venkatraman , James Sellers , Hemanshu D. Bhatt
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/42372 , H01L29/4238 , H01L29/4933 , H01L29/66734 , H01L29/7811
摘要： In one embodiment, an MOS transistor is formed to have an active region and a termination region. Within the termination region a plurality of conductors are formed to make electrical contact to conductors that are within a plurality of trenches. The plurality of conductors in the termination region are formed to be substantially coplanar.
摘要翻译：在一个实施例中，MOS晶体管形成为具有有源区和端接区。在终止区域内，形成多个导体以与多个沟槽内的导体电接触。终端区域中的多个导体形成为基本共面。

2. 发明授权

US07384801B2 Integrated circuit with inductor having horizontal magnetic flux lines 有权
标题翻译：具有水平磁通线的电感的集成电路
公开(公告)号：US07384801B2
公开(公告)日：2008-06-10
申请号：US11811519
申请日：2007-06-11
申请人： Hemanshu D. Bhatt , Jan Fure , Derryl D. J. Allman
发明人： Hemanshu D. Bhatt , Jan Fure , Derryl D. J. Allman
IPC分类号： H01L21/00
CPC分类号： H01L28/10 , H01L23/5227 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit (IC) includes one or more inductors that have magnetic flux lines substantially parallel to a generally horizontal plane of the IC. The inductor is formed in a plurality of conductor layers separated by insulating layers of the IC. Regions of highest magnetic flux density of the inductor may preferably be located near the edge of the IC. Additionally, the inductor may preferably be segmented. The over-all inductance may preferably be controlled by turning on and off selected inductors or inductor segments.
摘要翻译：集成电路（IC）包括具有基本上平行于IC的大致水平面的磁通线的一个或多个电感器。电感器形成在由IC的绝缘层分离的多个导体层中。电感器的最大磁通密度的区域优选地位于IC边缘附近。另外，电感器可以优选地被分段。可以优选地通过接通和关断所选择的电感器或电感器段来控制全部电感。

3. 发明授权

US07582566B2 Method for redirecting void diffusion away from vias in an integrated circuit design 失效
标题翻译：在集成电路设计中将空隙扩散远离过孔的方法
公开(公告)号：US07582566B2
公开(公告)日：2009-09-01
申请号：US12018849
申请日：2008-01-24
申请人： Derryl D. J. Allman , Hemanshu D. Bhatt , Charles E. May , Peter Austin Burke , Byung-Sung Kwak , Sey-Shing Sun , David T. Price , David Pritchard
发明人： Derryl D. J. Allman , Hemanshu D. Bhatt , Charles E. May , Peter Austin Burke , Byung-Sung Kwak , Sey-Shing Sun , David T. Price , David Pritchard
IPC分类号： H01L21/311
CPC分类号： H01L21/76838 , H01L24/02 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/14
摘要： A method for redirecting void diffusion away from vias in an integrated circuit design includes steps of forming an electrical conductor in a first electrically conductive layer of an integrated circuit design, forming a via between a distal end of the electrical conductor and a second electrically conductive layer of the integrated circuit design, and reducing tensile stress in the electrical conductor to divert void diffusion away from the via.
摘要翻译：在集成电路设计中将空隙扩散转向远离通孔的方法包括在集成电路设计的第一导电层中形成电导体的步骤，在电导体的远端和第二导电层之间形成通孔的集成电路设计，并且减小电导体中的拉伸应力以将空隙扩散转移离开通孔。

4. 发明授权

US07253497B2 Integrated circuit with inductor having horizontal magnetic flux lines 有权
标题翻译：具有水平磁通线的电感的集成电路
公开(公告)号：US07253497B2
公开(公告)日：2007-08-07
申请号：US10614307
申请日：2003-07-02
申请人： Hemanshu D. Bhatt , Jan Fure , Derryl D. J. Allman
发明人： Hemanshu D. Bhatt , Jan Fure , Derryl D. J. Allman
IPC分类号： H01L29/00
CPC分类号： H01L28/10 , H01L23/5227 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit (IC) includes one or more inductors that have magnetic flux lines substantially parallel to a generally horizontal plane of the IC. The inductor is formed in a plurality of conductor layers separated by insulating layers of the IC. Regions of highest magnetic flux density of the inductor may preferably be located near the edge of the IC. Additionally, the inductor may preferably be segmented. The over-all inductance may preferably be controlled by turning on and off selected inductors or inductor segments.
摘要翻译：集成电路（IC）包括具有基本上平行于IC的大致水平面的磁通线的一个或多个电感器。电感器形成在由IC的绝缘层分离的多个导体层中。电感器的最大磁通密度的区域优选地位于IC边缘附近。另外，电感器可以优选地被分段。可以优选地通过接通和关断所选择的电感器或电感器段来控制全部电感。

5. 发明授权

US08940199B2 Method for producing fibers having optical effect-producing nanostructures 有权
标题翻译：制造具有光学效果的纳米结构的纤维的方法
公开(公告)号：US08940199B2
公开(公告)日：2015-01-27
申请号：US14129035
申请日：2011-10-17
申请人： Hemanshu D. Bhatt , Sunit D. Tyagi
发明人： Hemanshu D. Bhatt , Sunit D. Tyagi
IPC分类号： B29D11/00
CPC分类号： G02B6/0229 , B82Y20/00 , B82Y40/00 , G02B1/005 , G02B1/046 , G02B1/048 , G02B6/02033 , G02B6/02309 , G02B6/02319 , G02B6/02342 , G02B6/02376 , Y10S977/70 , Y10T428/249921
摘要： The present technology provides an illustrative method for preparing fibers with desirable optical characteristics. The method includes providing a fiber that comprises a core layer and a cladding layer located around the core layer. The method further includes applying a nanostructure template to the cladding layer to form one or more photonic nanostructures having nanostructure scales and compressing the core layer to cause the core layer to bulge and form air gaps between the core layer and the one or more photonic nanostructures.
摘要翻译：本技术提供了制备具有期望光学特性的纤维的说明性方法。该方法包括提供包括芯层和位于芯层周围的覆层的光纤。该方法还包括将纳米结构模板施加到包覆层以形成具有纳米结构尺度的一个或多个光子纳米结构，并压缩芯层以使芯层在芯层和一个或多个光子纳米结构之间凸起并形成气隙。

6. 发明授权

US08304314B2 Method of forming an MOS transistor 有权
标题翻译：形成MOS晶体管的方法
公开(公告)号：US08304314B2
公开(公告)日：2012-11-06
申请号：US12236718
申请日：2008-09-24
申请人： Jeffrey Pearse , Prasad Venkatraman , James Sellers , Hemanshu D. Bhatt
发明人： Jeffrey Pearse , Prasad Venkatraman , James Sellers , Hemanshu D. Bhatt
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/407 , H01L29/4238 , H01L29/66734 , H01L29/7811
摘要： In one embodiment, a method of forming an MOS transistor includes forming the MOS transistor to have an active region and a termination region. Within the termination region the method includes forming a plurality of trenches having a conductor within the plurality of trenches. The method also includes forming another conductor to make electrical contact to one of the conductors within the plurality of trenches.
摘要翻译：在一个实施例中，形成MOS晶体管的方法包括形成MOS晶体管以具有有源区和端接区。在终止区域内，该方法包括在多个沟槽内形成具有导体的多个沟槽。该方法还包括形成另一导体以与多个沟槽内的一个导体电接触。

7. 发明授权

US07915122B2 Self-aligned cell integration scheme 失效
标题翻译：自对准单元集成方案
公开(公告)号：US07915122B2
公开(公告)日：2011-03-29
申请号：US11312849
申请日：2005-12-20
申请人： Richard J. Carter , Hemanshu D. Bhatt , Shiqun Gu , Peter A. Burke , James R. B. Elmer , Sey-Shing Sun , Byung-Sung Kwak , Verne Hornback
发明人： Richard J. Carter , Hemanshu D. Bhatt , Shiqun Gu , Peter A. Burke , James R. B. Elmer , Sey-Shing Sun , Byung-Sung Kwak , Verne Hornback
IPC分类号： H01L21/336
CPC分类号： H01L51/0018 , B82Y10/00 , H01L27/283 , H01L51/0048 , H01L51/0545 , Y10S977/742
摘要： A method of forming a self-aligned logic cell. A nanotube layer is formed over the bottom electrode. A clamp layer is formed over the nanotube layer. The clamp layer covers the nanotube layer, thereby protecting the nanotube layer. A dielectric layer is formed over the clamp layer. The dielectric layer is etched. The clamp layer provides an etch stop and protects the nanotube layer. The clamp layer is etched with an isotropic etchant that etches the clamp layer underneath the dielectric layer, creating an overlap of the dielectric layer, and causing a self-alignment between the clamp layer and the dielectric layer. A spacer layer is formed over the nanotube layer. The spacer layer is etched except for a ring portion around the edge of the dielectric layer. The nanotube layer is etched except for portions that are underlying at least one of the clamp layer, the dielectric layer, and the spacer layer, thereby causing a self-alignment between the clamp layer, the overlap to the dielectric layer, the spacer layer, and the nanotube layer.
摘要翻译：一种形成自对准逻辑单元的方法。在底部电极上形成纳米管层。在纳米管层上形成夹层。夹层覆盖纳米管层，从而保护纳米管层。在钳位层上形成电介质层。蚀刻介电层。钳位层提供蚀刻停止并保护纳米管层。用各向同性蚀刻剂蚀刻钳夹层，蚀刻介质层下方的夹层，产生电介质层的重叠，并引起钳位层和电介质层之间的自对准。在纳米管层上形成间隔层。除了围绕电介质层的边缘的环形部分之外，蚀刻间隔层。除了夹持层，电介质层和间隔层中的至少一个的部分以外，蚀刻纳米管层，从而导致夹紧层之间的自对准，与电介质层的重叠，间隔层，和纳米管层。

8. 发明授权

US07122436B2 Techniques for forming passive devices during semiconductor back-end processing 有权
公开(公告)号：US07122436B2
公开(公告)日：2006-10-17
申请号：US10944373
申请日：2004-09-16
申请人： Santosh S. Menon , Hemanshu D. Bhatt
发明人： Santosh S. Menon , Hemanshu D. Bhatt
IPC分类号： H01L21/20
CPC分类号： H01L23/5228 , H01L21/3215 , H01L28/24 , H01L2924/0002 , H01L2924/00
摘要： Fabrication of electronic devices in the “metal layers” of semiconductor devices. Each metal layer includes a dielectric layer that supports a conductive layer, which includes electrically conductive pathways and electronic devices. The metal layers are stacked on top of each other such that the dielectric layers separate the adjacent conductive layers. The electronic devices may be passive devices such as resistors. The resistors are formed by depositing metal onto the dielectric layer and then implanting the metal with oxygen. The conductive layer may be formed of materials such as copper and aluminum.

9. 发明授权

US06649537B1 Intermittent pulsed oxidation process 有权
标题翻译：间歇脉冲氧化工艺
公开(公告)号：US06649537B1
公开(公告)日：2003-11-18
申请号：US10044215
申请日：2001-11-19
申请人： Steven E. Reder , Hemanshu D. Bhatt
发明人： Steven E. Reder , Hemanshu D. Bhatt
IPC分类号： H07L2131
CPC分类号： H01L21/0214 , H01L21/02238 , H01L21/02255 , H01L21/02332 , H01L21/02337 , H01L21/31662 , Y10S438/913
摘要： The present invention provides a method of forming a dielectric on a semiconductor substrate. A dielectric is grown at a substrate interface in a plurality of increments. Stress is relieved at the dielectric substrate interface between each increment. In another aspect, stress relief is performed by annealing the substrate. The annealing is performed by placing the substrate in an inert environment and by raising the temperature surrounding the substrate.
摘要翻译：本发明提供一种在半导体衬底上形成电介质的方法。电介质以多个增量在衬底界面处生长。在每个增量之间的电介质基板界面处，应力消除。另一方面，通过对衬底进行退火来进行应力释放。通过将衬底放置在惰性环境中并通过提高衬底周围的温度来进行退火。

10. 发明授权

US06495881B1 Programmable read only memory in CMOS process flow 有权
公开(公告)号：US06495881B1
公开(公告)日：2002-12-17
申请号：US10012835
申请日：2001-10-22
申请人： Shafqat Ahmed , Hemanshu D. Bhatt , Charles E. May , Robindranath Banerjee
发明人： Shafqat Ahmed , Hemanshu D. Bhatt , Charles E. May , Robindranath Banerjee
IPC分类号： H01L29788
CPC分类号： H01L27/112 , H01L21/8238
摘要： An improvement to a process for manufacturing complementary metal oxide semiconductor devices on a monolithic substrate, where the improved process forms nonvolatile memory devices and programmable logic devices. The improvement includes exposing gate electrodes of a selected portion of the complementary metal oxide semiconductor devices at a point in the process where the gate electrodes have been previously covered by a protective material layer. A capacitive material layer is deposited on the monolithic substrate, such that it contacts the exposed gate electrodes of the selected portion of the complementary metal oxide semiconductor devices. A top electrode material layer is deposited on the monolithic substrate, such that the top electrode material layer contacts the capacitive material layer in a region overlying the exposed gate electrodes of the selected portion of the complementary metal oxide semiconductor devices. The top electrode material layer and the capacitive material layer are removed to substantially the level of the upper surface of the protective material layer, thereby leaving the top electrode layer and the capacitive material layer overlying the gate electrodes for the selected portion of the complementary metal oxide semiconductor devices. In this manner, capacitors are formed from the top electrode material layer, the capacitive material layer, and the gate electrodes of the selected portion of the complementary metal oxide semiconductor devices. The improved process further includes forming nonvolatile memory devices from the selected portion of the complementary metal oxide semiconductor devices, and forming logic devices of the complementary metal oxide semiconductor devices that are not included in the selected portion of the complementary metal oxide semiconductor devices. Fuses are formed in associated with a portion of the nonvolatile memory devices to form read only memory devices of the fused portion of the nonvolatile memory devices.

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