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1. 发明授权

US06522005B1 Integrated circuit device comprising low dielectric constant material for reduced cross talk 失效
标题翻译：集成电路装置，包括用于减少串扰的低介电常数材料
公开(公告)号：US06522005B1
公开(公告)日：2003-02-18
申请号：US09618991
申请日：2000-07-18
申请人： Derryl D. J. Allman , Kenneth P. Fuchs , Gayle W. Miller , Samuel C. Gioia
发明人： Derryl D. J. Allman , Kenneth P. Fuchs , Gayle W. Miller , Samuel C. Gioia
IPC分类号： H01L2348
CPC分类号： H01L23/3171 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： A low dielectric material is applied, as by spinning on, over the passivation layer of a semiconductor chip to fill the gaps which may exist between the top layer metal lines, and thereby minimize the possibility of cross talk which might otherwise be present between those lines.
摘要翻译：通过旋转在半导体芯片的钝化层上施加低电介质材料以填充可能存在于顶层金属线之间的间隙，从而最小化可能存在于这些线之间的串扰的可能性。

2. 发明授权

US06504250B1 Integrated circuit device with reduced cross talk 失效
公开(公告)号：US06504250B1
公开(公告)日：2003-01-07
申请号：US09695598
申请日：2000-10-23
申请人： Derryl D. J. Allman , Kenneth P. Fuchs , Gayle W. Miller , Samuel C. Gioia
发明人： Derryl D. J. Allman , Kenneth P. Fuchs , Gayle W. Miller , Samuel C. Gioia
IPC分类号： H01L2348
CPC分类号： H01L23/3171 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： A low dielectric material is applied, as by spinning on, over the passivation layer of a semiconductor chip to fill the gaps which may exist between the top layer metal lines, and thereby minimize the possibility of cross talk which might otherwise be present between those lines.

3. 发明授权

US06448653B1 Method for using low dielectric constant material in integrated circuit fabrication 失效
标题翻译：在集成电路制造中使用低介电常数材料的方法
公开(公告)号：US06448653B1
公开(公告)日：2002-09-10
申请号：US09694993
申请日：2000-10-23
申请人： Derryl D. J. Allman , Kenneth P. Fuchs , Gayle W. Miller , Samuel C. Gioia
发明人： Derryl D. J. Allman , Kenneth P. Fuchs , Gayle W. Miller , Samuel C. Gioia
IPC分类号： H01L2348
CPC分类号： H01L23/3171 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： A low dielectric material is applied, as by spinning on, over the passivation layer of a semiconductor chip to fill the gaps which may exist between the top layer metal lines, and thereby minimize the possibility of cross talk which might otherwise be present between those lines.
摘要翻译：通过旋转在半导体芯片的钝化层上施加低电介质材料以填充可能存在于顶层金属线之间的间隙，从而最小化可能存在于这些线之间的串扰的可能性。

4. 发明授权

US06522006B1 Low dielectric constant material in integrated circuit 失效
标题翻译：集成电路中的低介电常数材料
公开(公告)号：US06522006B1
公开(公告)日：2003-02-18
申请号：US09695020
申请日：2000-10-23
申请人： Derryl D. J. Allman , Kenneth P. Fuchs , Gayle W. Miller , Samuel C. Gioia
发明人： Derryl D. J. Allman , Kenneth P. Fuchs , Gayle W. Miller , Samuel C. Gioia
IPC分类号： H01L2348
CPC分类号： H01L23/3171 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： A low dielectric material is applied, as by spinning on, over the passivation layer of a semiconductor chip to fill the gaps which may exist between the top layer metal lines, and thereby minimize the possibility of cross talk which might otherwise be present between those lines.
摘要翻译：通过旋转在半导体芯片的钝化层上施加低电介质材料以填充可能存在于顶层金属线之间的间隙，从而最小化可能存在于这些线之间的串扰的可能性。

5. 发明授权

US06504249B1 Integrated circuit device with reduced cross talk 失效
标题翻译：具有减少串扰的集成电路器件
公开(公告)号：US06504249B1
公开(公告)日：2003-01-07
申请号：US09558930
申请日：2000-04-26
申请人： Derryl D. J. Allman , Kenneth P. Fuchs , Gayle W. Miller , Samuel C. Gioia
发明人： Derryl D. J. Allman , Kenneth P. Fuchs , Gayle W. Miller , Samuel C. Gioia
IPC分类号： H01L2348
CPC分类号： H01L23/3171 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： A low dielectric material is applied, as by spinning on, over the passivation layer of a semiconductor chip to fill the gaps which may exist between the top layer metal lines, and thereby minimize the possibility of cross talk which might otherwise be present between those lines.
摘要翻译：通过旋转在半导体芯片的钝化层上施加低电介质材料以填充可能存在于顶层金属线之间的间隙，从而最小化可能存在于这些线之间的串扰的可能性。

6. 发明授权

US06208029B1 Integrated circuit device with reduced cross talk 失效
标题翻译：具有减少串扰的集成电路器件
公开(公告)号：US06208029B1
公开(公告)日：2001-03-27
申请号：US08829745
申请日：1997-03-31
申请人： Derryl D. J. Allman , Kenneth P. Fuchs , Gayle W. Miller , Samuel C. Gioia
发明人： Derryl D. J. Allman , Kenneth P. Fuchs , Gayle W. Miller , Samuel C. Gioia
IPC分类号： H01L2348
CPC分类号： H01L23/3171 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： A low dielectric material is applied, as by spinning on, over the passivation layer of a semiconductor chip to fill the gaps which may exist between the top layer metal lines, and thereby minimize the possibility of cross talk which might otherwise be present between those lines.
摘要翻译：通过旋转在半导体芯片的钝化层上施加低电介质材料以填充可能存在于顶层金属线之间的间隙，从而最小化可能存在于这些线之间的串扰的可能性。

7. 发明授权

US5438022A Method for using low dielectric constant material in integrated circuit fabrication 失效
公开(公告)号：US5438022A
公开(公告)日：1995-08-01
申请号：US165872
申请日：1993-12-14
申请人： Derryl D. J. Allman , Kenneth P. Fuchs , Gayle W. Miller , Samuel C. Gioia
发明人： Derryl D. J. Allman , Kenneth P. Fuchs , Gayle W. Miller , Samuel C. Gioia
IPC分类号： H01L21/768 , H01L21/316 , H01L21/324 , H01L21/822 , H01L23/14 , H01L23/31 , H01L23/522 , H01L27/04 , H01L21/00
CPC分类号： H01L23/3171 , H01L23/5222 , H01L2924/0002
摘要： A low dielectric material is applied, as by spinning on, over the passivation layer of a semiconductor chip to fill the gaps which may exist between the top layer metal lines, and thereby minimize the possibility of cross talk which might otherwise be present between those lines.

8. 发明授权

US06071817A Isolation method utilizing a high pressure oxidation 失效
标题翻译：采用高压氧化的隔离方法
公开(公告)号：US06071817A
公开(公告)日：2000-06-06
申请号：US046242
申请日：1998-03-23
申请人： Derryl D. J. Allman , Kenneth P. Fuchs
发明人： Derryl D. J. Allman , Kenneth P. Fuchs
IPC分类号： H01L21/316 , H01L21/762 , H01L21/00
CPC分类号： H01L21/02238 , H01L21/02255 , H01L21/31662 , H01L21/76202 , H01L21/76205
摘要： The present invention applies a silicon nitride or the like as a mask over portions of a substrate, such as an active region, where oxide growth is undesired. Thereafter, without the formation of a recess in the substrate, a high pressure oxidation process is used to grow an oxide, preferably in a furnace. The oxide thus grows into the non-masked areas of the substrate, as well as over the silicon nitride used as a mask. Thereafter, a chemical-mechanical polish is used to etch away undesired oxide, with the silicon nitride being used as an endpoint to terminate the polish operation.
摘要翻译：本发明将氮化硅等作为掩模应用于诸如活性区域的基底的不希望有氧化物生长的部分上。此后，在衬底中不形成凹陷的情况下，使用高压氧化工艺来生长氧化物，优选在炉中生长氧化物。因此，氧化物生长到衬底的非掩蔽区域中，以及用作掩模的氮化硅上方。此后，使用化学机械抛光剂来蚀刻掉不期望的氧化物，其中氮化硅用作端点终止抛光操作。

9. 发明授权

US6010963A Global planarization using SOG and CMP 失效
标题翻译：使用SOG和CMP的全局平面化
公开(公告)号：US6010963A
公开(公告)日：2000-01-04
申请号：US567504
申请日：1995-12-05
申请人： Derryl D. J. Allman , Kenneth P. Fuchs
发明人： Derryl D. J. Allman , Kenneth P. Fuchs
IPC分类号： H01L21/3105 , H01L21/316 , H01L21/768 , H01L21/20
CPC分类号： H01L21/76819 , H01L21/31053 , H01L21/31055 , H01L21/316
摘要： A method for planarizing the surface of a semiconductor device which employs spin on glass (SOG) and an etching operation to remove high portions of the SOG prior to a chemical metal polish (CMP) operation. The SOG is baked and cured before etching. Additional layers of SOG and etching operations may be employed as necessary. A thick encapsulating oxide layer is deposited over the SOG layer. For surface irregularities caused by metal lines, an insulating layer may be deposited over the surface before the SOG. Where an additional metal line is to be deposited on the surface, an additional insulating layer is deposited after the CMP operation. In the case of metal lines made of aluminum, provision is also made for preventing Hillock formations on the metal lines.
摘要翻译：在化学金属抛光（CMP）操作之前，使用旋涂玻璃（SOG）的半导体器件的表面平坦化的方法和蚀刻操作来去除SOG的高部分。 SOG在蚀刻前烘烤和固化。根据需要可以采用附加的SOG层和蚀刻操作。在SOG层上沉积厚的封装氧化物层。对于由金属线引起的表面凹凸，绝缘层可能沉积在SOG之前的表面上。在附加金属线要沉积在表面上的情况下，在CMP操作之后沉积附加的绝缘层。在由铝制成的金属线的情况下，还提供用于防止金属线上的小丘形成。

10. 发明授权

US5312512A Global planarization using SOG and CMP 失效
标题翻译：使用SOG和CMP的全局平面化
公开(公告)号：US5312512A
公开(公告)日：1994-05-17
申请号：US965309
申请日：1992-10-23
申请人： Derryl D. J. Allman , Kenneth P. Fuchs
发明人： Derryl D. J. Allman , Kenneth P. Fuchs
IPC分类号： H01L21/3105 , H01L21/316 , H01L21/768 , H01L21/306 , H01L21/465
CPC分类号： H01L21/76819 , H01L21/31053 , H01L21/31055 , H01L21/316
摘要： A method for planarizing the surface of a semiconductor device which employs spin on glass (SOG) and an etching operation to remove high portions of the SOG prior to a chemical metal polish (CMP) operation. The SOG is baked and cured before etching. Additional layers of SOG and etching operations may be employed as necessary. A thick encapsulating oxide layer is deposited over the SOG layer. For surface irregularities caused by metal lines, an insulating layer may be deposited over the surface before the SOG. Where an additional metal line is to be deposited on the surface, an additional insulating layer is deposited after the CMP operation. In the case of metal lines made of aluminum, provision is also made for preventing Hillock formations on the metal lines.
摘要翻译：在化学金属抛光（CMP）操作之前，使用旋涂玻璃（SOG）的半导体器件的表面平坦化的方法和蚀刻操作来去除SOG的高部分。 SOG在蚀刻前烘烤和固化。根据需要可以采用附加的SOG层和蚀刻操作。在SOG层上沉积厚的封装氧化物层。对于由金属线引起的表面凹凸，绝缘层可能沉积在SOG之前的表面上。在附加金属线要沉积在表面上的情况下，在CMP操作之后沉积附加的绝缘层。在由铝制成的金属线的情况下，还提供用于防止金属线上的小丘形成。

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