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1. 发明授权

US06522006B1 Low dielectric constant material in integrated circuit 失效
标题翻译：集成电路中的低介电常数材料
公开(公告)号：US06522006B1
公开(公告)日：2003-02-18
申请号：US09695020
申请日：2000-10-23
申请人： Derryl D. J. Allman , Kenneth P. Fuchs , Gayle W. Miller , Samuel C. Gioia
发明人： Derryl D. J. Allman , Kenneth P. Fuchs , Gayle W. Miller , Samuel C. Gioia
IPC分类号： H01L2348
CPC分类号： H01L23/3171 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： A low dielectric material is applied, as by spinning on, over the passivation layer of a semiconductor chip to fill the gaps which may exist between the top layer metal lines, and thereby minimize the possibility of cross talk which might otherwise be present between those lines.
摘要翻译：通过旋转在半导体芯片的钝化层上施加低电介质材料以填充可能存在于顶层金属线之间的间隙，从而最小化可能存在于这些线之间的串扰的可能性。

2. 发明授权

US06504249B1 Integrated circuit device with reduced cross talk 失效
标题翻译：具有减少串扰的集成电路器件
公开(公告)号：US06504249B1
公开(公告)日：2003-01-07
申请号：US09558930
申请日：2000-04-26
申请人： Derryl D. J. Allman , Kenneth P. Fuchs , Gayle W. Miller , Samuel C. Gioia
发明人： Derryl D. J. Allman , Kenneth P. Fuchs , Gayle W. Miller , Samuel C. Gioia
IPC分类号： H01L2348
CPC分类号： H01L23/3171 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： A low dielectric material is applied, as by spinning on, over the passivation layer of a semiconductor chip to fill the gaps which may exist between the top layer metal lines, and thereby minimize the possibility of cross talk which might otherwise be present between those lines.
摘要翻译：通过旋转在半导体芯片的钝化层上施加低电介质材料以填充可能存在于顶层金属线之间的间隙，从而最小化可能存在于这些线之间的串扰的可能性。

3. 发明授权

US6010963A Global planarization using SOG and CMP 失效
标题翻译：使用SOG和CMP的全局平面化
公开(公告)号：US6010963A
公开(公告)日：2000-01-04
申请号：US567504
申请日：1995-12-05
申请人： Derryl D. J. Allman , Kenneth P. Fuchs
发明人： Derryl D. J. Allman , Kenneth P. Fuchs
IPC分类号： H01L21/3105 , H01L21/316 , H01L21/768 , H01L21/20
CPC分类号： H01L21/76819 , H01L21/31053 , H01L21/31055 , H01L21/316
摘要： A method for planarizing the surface of a semiconductor device which employs spin on glass (SOG) and an etching operation to remove high portions of the SOG prior to a chemical metal polish (CMP) operation. The SOG is baked and cured before etching. Additional layers of SOG and etching operations may be employed as necessary. A thick encapsulating oxide layer is deposited over the SOG layer. For surface irregularities caused by metal lines, an insulating layer may be deposited over the surface before the SOG. Where an additional metal line is to be deposited on the surface, an additional insulating layer is deposited after the CMP operation. In the case of metal lines made of aluminum, provision is also made for preventing Hillock formations on the metal lines.
摘要翻译：在化学金属抛光（CMP）操作之前，使用旋涂玻璃（SOG）的半导体器件的表面平坦化的方法和蚀刻操作来去除SOG的高部分。 SOG在蚀刻前烘烤和固化。根据需要可以采用附加的SOG层和蚀刻操作。在SOG层上沉积厚的封装氧化物层。对于由金属线引起的表面凹凸，绝缘层可能沉积在SOG之前的表面上。在附加金属线要沉积在表面上的情况下，在CMP操作之后沉积附加的绝缘层。在由铝制成的金属线的情况下，还提供用于防止金属线上的小丘形成。

4. 发明授权

US5312512A Global planarization using SOG and CMP 失效
标题翻译：使用SOG和CMP的全局平面化
公开(公告)号：US5312512A
公开(公告)日：1994-05-17
申请号：US965309
申请日：1992-10-23
申请人： Derryl D. J. Allman , Kenneth P. Fuchs
发明人： Derryl D. J. Allman , Kenneth P. Fuchs
IPC分类号： H01L21/3105 , H01L21/316 , H01L21/768 , H01L21/306 , H01L21/465
CPC分类号： H01L21/76819 , H01L21/31053 , H01L21/31055 , H01L21/316
摘要： A method for planarizing the surface of a semiconductor device which employs spin on glass (SOG) and an etching operation to remove high portions of the SOG prior to a chemical metal polish (CMP) operation. The SOG is baked and cured before etching. Additional layers of SOG and etching operations may be employed as necessary. A thick encapsulating oxide layer is deposited over the SOG layer. For surface irregularities caused by metal lines, an insulating layer may be deposited over the surface before the SOG. Where an additional metal line is to be deposited on the surface, an additional insulating layer is deposited after the CMP operation. In the case of metal lines made of aluminum, provision is also made for preventing Hillock formations on the metal lines.
摘要翻译：在化学金属抛光（CMP）操作之前，使用旋涂玻璃（SOG）的半导体器件的表面平坦化的方法和蚀刻操作来去除SOG的高部分。 SOG在蚀刻前烘烤和固化。根据需要可以采用附加的SOG层和蚀刻操作。在SOG层上沉积厚的封装氧化物层。对于由金属线引起的表面凹凸，绝缘层可能沉积在SOG之前的表面上。在附加金属线要沉积在表面上的情况下，在CMP操作之后沉积附加的绝缘层。在由铝制成的金属线的情况下，还提供用于防止金属线上的小丘形成。

5. 发明授权

US07176082B2 Analog capacitor in dual damascene process 有权
标题翻译：双镶嵌工艺中的模拟电容器
公开(公告)号：US07176082B2
公开(公告)日：2007-02-13
申请号：US10959868
申请日：2004-10-06
申请人： Todd A. Randazzo , Kenneth P. Fuchs , John de Q. Walker
发明人： Todd A. Randazzo , Kenneth P. Fuchs , John de Q. Walker
IPC分类号： H01L21/8242
CPC分类号： H01L21/76807 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： A process for forming a capacitive structure that includes an upper layer having a first capacitor electrode section therein. A capacitor dielectric layer is formed adjacent the upper layer. The capacitor dielectric layer covers the first capacitor electrode section. A second capacitor electrode layer is formed adjacent the capacitor dielectric layer. The second capacitor electrode layer includes a second capacitor electrode section that at least partially covers the first capacitor electrode section, and which has an edge portion that extends beyond the underlying first capacitor electrode section. The capacitor dielectric layer being disposed between the first capacitor electrode section and the second capacitor electrode section. An upper dielectric layer is formed adjacent the second capacitor electrode section. Portions of the upper dielectric layer and the second capacitor electrode section are selectively removed to form a first via cavity that extends through the upper dielectric layer and the edge portion of the second capacitor electrode section. This exposes the edge portion of the second capacitor electrode section within the first via cavity. The first via cavity is filled with a via metal, which makes electrical connection with the edge portion of the second capacitor electrode section that is exposed within the first via cavity.
摘要翻译：一种用于形成电容结构的方法，其包括其中具有第一电容器电极部分的上层。在上层附近形成电容器电介质层。电容器电介质层覆盖第一电容器电极部分。在电容器电介质层附近形成第二电容器电极层。第二电容器电极层包括至少部分地覆盖第一电容器电极部分并且具有延伸超过下面的第一电容器电极部分的边缘部分的第二电容器电极部分。电容器电介质层设置在第一电容电极部分和第二电容器电极部分之间。在第二电容器电极部分附近形成上介电层。选择性地去除上电介质层和第二电容器电极部分的部分以形成延伸穿过上电介质层和第二电容器电极部分的边缘部分的第一通孔。这使第二电容电极部分的边缘部分暴露在第一通孔腔内。第一通孔腔填充有通孔金属，其与第一电容器电极部分的暴露在第一通孔腔内的边缘部分电连接。

6. 发明授权

US06596579B1 Method of forming analog capacitor dual damascene process 有权
标题翻译：形成模拟电容双镶嵌工艺的方法
公开(公告)号：US06596579B1
公开(公告)日：2003-07-22
申请号：US09844531
申请日：2001-04-27
申请人： Todd A. Randazzo , Kenneth P. Fuchs , John de Q. Walker
发明人： Todd A. Randazzo , Kenneth P. Fuchs , John de Q. Walker
IPC分类号： H01L218242
CPC分类号： H01L28/40 , H01L21/76807 , H01L21/76895 , H01L23/5223 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： A process for forming a capacitive structure that includes an upper layer having a first capacitor electrode section therein. A capacitor dielectric layer is formed adjacent the upper layer. The capacitor dielectric layer covers the first capacitor electrode section. A second capacitor electrode layer is formed adjacent the capacitor dielectric layer. The second capacitor electrode layer includes a second capacitor electrode section that at least partially covers the first capacitor electrode section, and which has an edge portion that extends beyond the underlying first capacitor electrode section. The capacitor dielectric layer being disposed between the first capacitor electrode section and the second capacitor electrode section. An upper dielectric layer is formed adjacent the second capacitor electrode section. Portions of the upper dielectric layer and the second capacitor electrode section are selectively removed to form a first via cavity that extends through the upper dielectric layer and the edge portion of the second capacitor electrode section. This exposes the edge portion of the second capacitor electrode section within the first via cavity. The first via cavity is filled with a via metal, which makes electrical connection with the edge portion of the second capacitor electrode section that is exposed within the first via cavity.
摘要翻译：一种用于形成电容结构的方法，其包括其中具有第一电容器电极部分的上层。在上层附近形成电容器电介质层。电容器电介质层覆盖第一电容器电极部分。在电容器电介质层附近形成第二电容器电极层。第二电容器电极层包括至少部分地覆盖第一电容器电极部分并且具有延伸超过下面的第一电容器电极部分的边缘部分的第二电容器电极部分。电容器电介质层设置在第一电容电极部分和第二电容器电极部分之间。在第二电容器电极部分附近形成上介电层。选择性地去除上电介质层和第二电容器电极部分的部分以形成延伸穿过上电介质层和第二电容器电极部分的边缘部分的第一通孔。这使第二电容电极部分的边缘部分暴露在第一通孔腔内。第一通孔腔填充有通孔金属，其与第一电容器电极部分的暴露在第一通孔腔内的边缘部分电连接。

7. 发明授权

US06208029B1 Integrated circuit device with reduced cross talk 失效
标题翻译：具有减少串扰的集成电路器件
公开(公告)号：US06208029B1
公开(公告)日：2001-03-27
申请号：US08829745
申请日：1997-03-31
申请人： Derryl D. J. Allman , Kenneth P. Fuchs , Gayle W. Miller , Samuel C. Gioia
发明人： Derryl D. J. Allman , Kenneth P. Fuchs , Gayle W. Miller , Samuel C. Gioia
IPC分类号： H01L2348
CPC分类号： H01L23/3171 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： A low dielectric material is applied, as by spinning on, over the passivation layer of a semiconductor chip to fill the gaps which may exist between the top layer metal lines, and thereby minimize the possibility of cross talk which might otherwise be present between those lines.
摘要翻译：通过旋转在半导体芯片的钝化层上施加低电介质材料以填充可能存在于顶层金属线之间的间隙，从而最小化可能存在于这些线之间的串扰的可能性。

8. 发明授权

US5447880A Method for forming an amorphous silicon programmable element 失效
标题翻译：用于形成非晶硅可编程元件的方法
公开(公告)号：US5447880A
公开(公告)日：1995-09-05
申请号：US224609
申请日：1994-04-05
申请人： Steven S. Lee , Kenneth P. Fuchs , Gayle W. Miller
发明人： Steven S. Lee , Kenneth P. Fuchs , Gayle W. Miller
IPC分类号： H01L23/525 , H01L21/70 , H01L27/00
CPC分类号： H01L23/5252 , H01L2924/0002
摘要： A method for forming an amorphous silicon programable element which requires less than about one square micron of area. The method includes the steps of forming a bottom conductor, depositing an interlayer dielectric above the bottom conductor, forming a via in the interlayer dielectric, depositing an anti-fuse layer above the bottom conductor within the via, and chemical vapor depositing a conductive plug above the anti-fuse layer and within the via. The method may additionally include the step of chemical vapor depositing a top conductor above the conductive plug.
摘要翻译：一种形成非晶硅可编程元件的方法，其需要小于约一平方微米的面积。该方法包括以下步骤：形成底部导体，在底部导体上沉积层间电介质，在层间电介质中形成通孔，在通孔内沉积底部导体上方的反熔丝层，以及化学气相沉积导电塞反熔丝层和通孔内。该方法可以另外包括化学气相沉积在导电插塞上方的顶部导体的步骤。

9. 发明授权

US5438022A Method for using low dielectric constant material in integrated circuit fabrication 失效
公开(公告)号：US5438022A
公开(公告)日：1995-08-01
申请号：US165872
申请日：1993-12-14
申请人： Derryl D. J. Allman , Kenneth P. Fuchs , Gayle W. Miller , Samuel C. Gioia
发明人： Derryl D. J. Allman , Kenneth P. Fuchs , Gayle W. Miller , Samuel C. Gioia
IPC分类号： H01L21/768 , H01L21/316 , H01L21/324 , H01L21/822 , H01L23/14 , H01L23/31 , H01L23/522 , H01L27/04 , H01L21/00
CPC分类号： H01L23/3171 , H01L23/5222 , H01L2924/0002
摘要： A low dielectric material is applied, as by spinning on, over the passivation layer of a semiconductor chip to fill the gaps which may exist between the top layer metal lines, and thereby minimize the possibility of cross talk which might otherwise be present between those lines.

10. 发明授权

US06504250B1 Integrated circuit device with reduced cross talk 失效
公开(公告)号：US06504250B1
公开(公告)日：2003-01-07
申请号：US09695598
申请日：2000-10-23
申请人： Derryl D. J. Allman , Kenneth P. Fuchs , Gayle W. Miller , Samuel C. Gioia
发明人： Derryl D. J. Allman , Kenneth P. Fuchs , Gayle W. Miller , Samuel C. Gioia
IPC分类号： H01L2348
CPC分类号： H01L23/3171 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： A low dielectric material is applied, as by spinning on, over the passivation layer of a semiconductor chip to fill the gaps which may exist between the top layer metal lines, and thereby minimize the possibility of cross talk which might otherwise be present between those lines.

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