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1. 发明授权

US08168318B2 Method for high volume manufacturing of thin film batteries 有权
标题翻译：薄膜电池大批量生产方法
公开(公告)号：US08168318B2
公开(公告)日：2012-05-01
申请号：US12257049
申请日：2008-10-23
申请人： Byung Sung Kwak , Nety M. Krishna , Kurt Eisenbeiser , William J. Dauksher , Jon Candelaria
发明人： Byung Sung Kwak , Nety M. Krishna , Kurt Eisenbeiser , William J. Dauksher , Jon Candelaria
IPC分类号： H01M6/16 , H01M6/18 , H01M6/46
CPC分类号： H01M10/0585 , H01M6/40 , H01M10/0436 , H01M10/052 , H01M2300/0068
摘要： Concepts and methods are provided to reduce the cost and complexity of thin film battery (TFB) high volume manufacturing by eliminating and/or minimizing the use of conventional physical (shadow) masks. Laser scribing and other alternative physical maskless patterning techniques meet certain or all of the patterning requirements. In one embodiment, a method of manufacturing thin film batteries comprises providing a substrate, depositing layers corresponding to a thin film battery structure on the substrate, the layers including, in order of deposition, a cathode, an electrolyte and an anode, wherein at least one of the deposited layers is unpatterned by a physical mask during deposition, depositing a protective coating, and scribing the layers and the protective coating. Further, the edges of the layers may be covered by an encapsulation layer. Furthermore, the layers may be deposited on two substrates and then laminated to form the thin film battery.
摘要翻译：提供了概念和方法，以通过消除和/或最小化常规物理（阴影）掩模的使用来降低薄膜电池（TFB）大批量制造的成本和复杂性。激光划线和其他可选的物理无掩模图案化技术满足某些或所有图案化要求。在一个实施例中，制造薄膜电池的方法包括提供衬底，在衬底上沉积与薄膜电池结构相对应的层，所述层按沉积顺序包括阴极，电解质和阳极，其中至少沉积层中的一个在沉积期间由物理掩模未图案化，沉积保护涂层，以及划刻层和保护涂层。此外，层的边缘可以被封装层覆盖。此外，可以将这些层沉积在两个基板上，然后层压以形成薄膜电池。

2. 发明授权

US08168265B2 Method for manufacturing electrochromic devices 有权
标题翻译：电致变色器件的制造方法
公开(公告)号：US08168265B2
公开(公告)日：2012-05-01
申请号：US12134437
申请日：2008-06-06
申请人： Byung Sung Kwak , Nety Krishna
发明人： Byung Sung Kwak , Nety Krishna
IPC分类号： C08J7/18 , B05D3/06 , B05D5/12 , B05D5/06 , G02F1/15
CPC分类号： G02F1/1533 , G02F1/1523 , G02F1/155 , G02F2001/1536
摘要： This invention contemplates the use of laser patterning/scribing in electrochromic device manufacture, anywhere during the manufacturing process as deemed appropriate and necessary for electrochromic device manufacturability, yield and functionality, while integrating the laser scribing so as to ensure the active layers of the device are protected to ensure long term reliability. It is envisaged that the laser is used to pattern the component layers of electrochromic devices by directly removing (ablating) the material of the component layers. The invention includes a manufacturing method for an electrochromic device comprising one or more focused laser patterning steps. To minimize redeposition of laser ablated material and particulate formation on device surfaces a number of approaches may be used: (1) ablated material generated by the focused laser patterning may be removed by vacuum suction and/or application of an inert gas jet in the vicinity of the laser ablation of device material; (2) spatial separation of the edges of layers and patterning of lower layers prior to deposition of upper layers; and (3) the laser patterning step may be performed by a laser beam focused directly on the deposited layers from above, by a laser beam directed through the transparent substrate, or by a combination of both.
摘要翻译：本发明考虑了在制造过程中的任何地方，在电致变色器件的可制造性，成品率和功能性中被认为是合适的和必要的，在电致变色器件制造中使用激光图案/划线，同时整合激光刻划以确保器件的有源层是保护以确保长期可靠性。可以设想，激光器用于通过直接去除（消融）组分层的材料来对电致变色器件的组件层进行图案化。本发明包括一种用于电致变色器件的制造方法，其包括一个或多个聚焦激光器图案化步骤。为了最小化激光烧蚀材料的再沉积和器件表面上的颗粒形成，可以使用许多方法：（1）通过聚焦激光图案形成产生的消融材料可以通过在附近的真空抽吸和/或施加惰性气体射流来去除的器件材料的激光烧蚀; （2）在沉积上层之前层的边缘的空间分离和下层的图案化; 和（3）激光图案化步骤可以通过从上方直接聚焦在沉积层上的激光束，通过引导通过透明衬底的激光束，或通过两者的组合进行。

3. 发明申请

US20100267191A1 PLASMA ENHANCED THERMAL EVAPORATOR 审中-公开
标题翻译：等离子体增强型热蒸发器
公开(公告)号：US20100267191A1
公开(公告)日：2010-10-21
申请号：US12763856
申请日：2010-04-20
申请人： Byung-Sung Kwak , Kaushal K. Singh , Stefan Bangert , Nety M. Krishna
发明人： Byung-Sung Kwak , Kaushal K. Singh , Stefan Bangert , Nety M. Krishna
IPC分类号： H01L31/18
CPC分类号： H01L31/18 , C23C16/4485 , C23C16/45565 , H01L31/03923
摘要： The present invention generally provides a method for forming a photovoltaic device including evaporating a source material to form a large molecule processing gas and flowing the large molecule processing gas through a gas distribution showerhead and into a processing area of a processing chamber having a substrate therein. The method includes generating a small molecule processing gas, and reacting the small molecule processing gas with a film already deposited on a substrate surface to form a semiconductor film. Additionally, apparatuses that may use the methods are also provided to enable continuous inline CIGS type solar cell formation.
摘要翻译：本发明通常提供一种形成光伏器件的方法，包括蒸发源材料以形成大分子加工气体，并使大分子处理气体通过气体分配喷头流入其中具有衬底的处理室的处理区域。该方法包括生成小分子处理气体，并使小分子处理气体与已沉积在基板表面上的膜反应形成半导体膜。此外，还可以使用可以使用这些方法的装置来实现连续的在线CIGS型太阳能电池的形成。

4. 发明授权

US07675177B1 Forming copper interconnects with Sn coatings 有权
标题翻译：与Sn涂层形成铜互连
公开(公告)号：US07675177B1
公开(公告)日：2010-03-09
申请号：US11074456
申请日：2005-03-07
申请人： Hongqiang Lu , Byung-Sung Kwak , Wilbur G. Catabay
发明人： Hongqiang Lu , Byung-Sung Kwak , Wilbur G. Catabay
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76849 , H01L21/2885 , H01L21/76867 , H01L21/76877
摘要： A copper interconnect with a Sn coating is formed in a damascene structure by forming a trench in a dielectric layer. The trench is formed by electroplating copper simultaneously with a metal dopant to form a doped copper layer. The top level of the doped copper layer is reduced to form a planarized surface level with the surface of the first dielectric layer. The doped copper is annealed to drive the metal dopants to form a metal dopant capping coating at the planarized top surface of the doped copper layer.
摘要翻译：通过在电介质层中形成沟槽，在镶嵌结构中形成具有Sn涂层的铜互连。沟槽通过同时与金属掺杂剂电镀铜形成掺杂的铜层而形成。掺杂铜层的顶层被还原成与第一介电层的表面形成平坦化的表面水平。将掺杂的铜退火以驱动金属掺杂剂，以在掺杂铜层的平坦化顶表面上形成金属掺杂物覆盖涂层。

5. 发明申请

US20090288943A1 THIN FILM BATTERIES AND METHODS FOR MANUFACTURING SAME 有权
标题翻译：薄膜电池及其制造方法
公开(公告)号：US20090288943A1
公开(公告)日：2009-11-26
申请号：US12124918
申请日：2008-05-21
申请人： Byung Sung Kwak , Michael Stowell , Nety Krishna
发明人： Byung Sung Kwak , Michael Stowell , Nety Krishna
IPC分类号： C23C14/34
CPC分类号： C23C14/088 , C23C14/3414 , H01M4/0426 , H01M4/1391 , H01M4/525 , H01M4/5825 , H01M6/40 , H01M10/052 , H01M10/0585
摘要： A method of fabricating a layer of a thin film battery comprises providing a sputtering target and depositing the layer on a substrate using a physical vapor deposition process enhanced by a combination of plasma processes. The deposition process may include: (1) generation of a plasma between the target and the substrate; (2) sputtering the target; (3) supplying microwave energy to the plasma; and (4) applying radio frequency power to the substrate. A sputtering target for a thin film battery cathode layer has an average composition of LiMaNbZc, wherein 0.20>{b/(a+b)}>0 and the ratio of a to c is approximately equal to the stoichiometric ratio of a desired crystalline structure of the cathode layer, N is an alkaline earth element, M is selected from the group consisting of Co, Mn, Al, Ni and V, and Z is selected from the group consisting of (PO4), O, F and N.
摘要翻译：制造薄膜电池层的方法包括提供溅射靶并使用通过等离子体处理的组合增强的物理气相沉积工艺将该层沉积在衬底上。沉积过程可以包括：（1）在靶和衬底之间产生等离子体; （2）溅射目标; （3）向等离子体提供微波能量; 和（4）向基板施加射频功率。用于薄膜电池阴极层的溅射靶具有LiMaNbZc的平均组成，其中0.20> {b /（a + b）}> 0，并且a与c的比值近似等于所需晶体结构的化学计量比的阴极层，N是碱土金属元素，M选自Co，Mn，Al，Ni和V，Z选自（PO4），O，F和N.

6. 发明授权

US07436040B2 Method and apparatus for diverting void diffusion in integrated circuit conductors 有权
标题翻译：用于在集成电路导体中转移空穴扩散的方法和装置
公开(公告)号：US07436040B2
公开(公告)日：2008-10-14
申请号：US11323398
申请日：2005-12-29
申请人： Derryl D. J. Allman , Hemanshu D. Bhatt , Charles E. May , Peter Austin Burke , Byung-Sung Kwak , Sey-Shing Sun , David T. Price , David Pritchard
发明人： Derryl D. J. Allman , Hemanshu D. Bhatt , Charles E. May , Peter Austin Burke , Byung-Sung Kwak , Sey-Shing Sun , David T. Price , David Pritchard
IPC分类号： H01L23/58
CPC分类号： H01L21/7682 , H01L21/76808 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A method of diverting void diffusion in an integrated circuit includes steps of forming an electrical conductor having a boundary in a first electrically conductive layer of an integrated circuit, forming a via inside the boundary of the electrical conductor in a dielectric layer between the first electrically conductive layer and a second electrically conductive layer of the integrated circuit, and forming a slot between the via and the boundary of the electrical conductor for diverting void diffusion in the electrical conductor away from the via.
摘要翻译：在集成电路中转移空穴扩散的方法包括以下步骤：在集成电路的第一导电层中形成具有边界的电导体，在电介质层的边界内在第一导电层和第二导电层，并且在电导体的通孔和边界之间形成槽，用于将电导体中的空隙扩散转移离开通孔。

7. 发明授权

US07361965B2 Method and apparatus for redirecting void diffusion away from vias in an integrated circuit design 有权
标题翻译：在集成电路设计中将空隙扩散远离过孔的方法和装置
公开(公告)号：US07361965B2
公开(公告)日：2008-04-22
申请号：US11323400
申请日：2005-12-29
申请人： Derryl D. J. Allman , Hemanshu D. Bhatt , Charles E. May , Peter Austin Burke , Byung-Sung Kwak , Sey-Shing Sun , David T. Price , David Pritchard
发明人： Derryl D. J. Allman , Hemanshu D. Bhatt , Charles E. May , Peter Austin Burke , Byung-Sung Kwak , Sey-Shing Sun , David T. Price , David Pritchard
IPC分类号： H01L23/58
CPC分类号： H01L21/76838 , H01L24/02 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/14
摘要： A method and apparatus for redirecting void diffusion away from vias in an integrated circuit design includes steps of forming an electrical conductor in a first electrically conductive layer of an integrated circuit design, forming a via between a distal end of the electrical conductor and a second electrically conductive layer of the integrated circuit design, and reducing tensile stress in the electrical conductor to divert void diffusion away from the via.
摘要翻译：用于在集成电路设计中将空隙扩散转向远离通孔的方法和装置包括在集成电路设计的第一导电层中形成电导体的步骤，在电导体的远端和第二电导体之间形成通孔集成电路设计的导电层，并且减小电导体中的拉伸应力以将空隙扩散转移离开通孔。

8. 发明申请

US20070155160A1 Method and apparatus for redirecting void diffusion away from vias in an integrated circuit design 有权
标题翻译：在集成电路设计中将空隙扩散远离过孔的方法和装置
公开(公告)号：US20070155160A1
公开(公告)日：2007-07-05
申请号：US11323400
申请日：2005-12-29
申请人： Derryl Allman , Hemanshu Bhatt , Charles May , Peter Burke , Byung-Sung Kwak , Sey-Shing Sun , David Price , David Pritchard
发明人： Derryl Allman , Hemanshu Bhatt , Charles May , Peter Burke , Byung-Sung Kwak , Sey-Shing Sun , David Price , David Pritchard
IPC分类号： H01L21/4763
CPC分类号： H01L21/76838 , H01L24/02 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/14
摘要： A method and apparatus for redirecting void diffusion away from vias in an integrated circuit design includes steps of forming an electrical conductor in a first electrically conductive layer of an integrated circuit design, forming a via between a distal end of the electrical conductor and a second electrically conductive layer of the integrated circuit design, and reducing tensile stress in the electrical conductor to divert void diffusion away from the via.
摘要翻译：用于在集成电路设计中将空隙扩散转向远离通孔的方法和装置包括在集成电路设计的第一导电层中形成电导体的步骤，在电导体的远端和第二电导体之间形成通孔集成电路设计的导电层，并且减小电导体中的拉伸应力以将空隙扩散转移离开通孔。

9. 发明申请

US20060084267A1 Method for fabricating planar semiconductor wafers 有权
标题翻译：制造平面半导体晶圆的方法
公开(公告)号：US20060084267A1
公开(公告)日：2006-04-20
申请号：US10966074
申请日：2004-10-14
申请人： Byung-Sung Kwak , Peter Burke , Sey-Shing Sun
发明人： Byung-Sung Kwak , Peter Burke , Sey-Shing Sun
IPC分类号： H01L21/44
CPC分类号： H01L21/76877 , C25D5/18 , C25D7/123 , H01L21/2885 , H01L21/7684
摘要： The present invention relates to a method of fabricating planar semiconductor wafers. The method comprises forming a dielectric layer on a semiconductor wafer surface, the semiconductor wafer surface having vias, trenches and planar regions. A barrier and seed metal layer is then formed on the dielectric layer. The wafer is next place in a plating bath that includes an accelerator, which tends to collect in the vias and trenches to accelerate the rate of plating in these areas relative to the planar regions of the wafer. After the gapfill point is reached, the plating is stopped by removing the plating bias on wafer. An equilibrium period is then introduced into the process, allowing higher concentrations of accelerator additives and other components of the bath)] above the via and trench regions to equilibrate in the plating bath. The bulk plating on the wafer is resumed after equilibration. Over-plating on the wafer in the areas of the vias and trenches is therefore avoided, resulting in a more planar metallization layer on the wafer, without the use of a leveler additive which adversely affects the gapfill capability.
摘要翻译：本发明涉及一种制造平面半导体晶片的方法。该方法包括在半导体晶片表面上形成电介质层，该半导体晶片表面具有通孔，沟槽和平面区域。然后在电介质层上形成阻挡层和种子金属层。晶片是包含加速器的镀液中的下一个位置，该加速器倾向于在通路和沟槽中收集，以加速相对于晶片的平面区域在这些区域中的电镀速率。达到间隙填充点后，通过去除晶片上的电镀偏压来停止电镀。然后在该过程中引入平衡时段，允许较高浓度的促进剂添加剂和浴中的其它组分）]在通孔和沟槽区域上方在电镀浴中平衡。平衡后恢复晶片上的块体电镀。因此避免了在通孔和沟槽区域上的晶片上的过电镀，导致晶片上更平面的金属化层，而不使用不利地影响间隙填充能力的矫直添加剂。

10. 发明授权

US06884720B1 Forming copper interconnects with Sn coatings 有权
标题翻译：与Sn涂层形成铜互连
公开(公告)号：US06884720B1
公开(公告)日：2005-04-26
申请号：US10648602
申请日：2003-08-25
申请人： Hongqiang Lu , Byung-Sung Kwak , Wilbur G. Catabay
发明人： Hongqiang Lu , Byung-Sung Kwak , Wilbur G. Catabay
IPC分类号： H01L21/288 , H01L21/44 , H01L21/768
CPC分类号： H01L21/76849 , H01L21/2885 , H01L21/76867 , H01L21/76877
摘要： A copper interconnect with a Sn coating is formed in a damascene structure by forming a trench in a dielectric layer. The trench is formed by electroplating copper simultaneously with a metal dopant to form a doped copper layer. The top level of the doped copper layer is reduced to form a planarized surface level with the surface of the first dielectric layer. The doped copper is annealed to drive the metal dopants to form a metal dopant capping coating at the planarized top surface of the doped copper layer.
摘要翻译：通过在电介质层中形成沟槽，在镶嵌结构中形成具有Sn涂层的铜互连。沟槽通过同时与金属掺杂剂电镀铜形成掺杂的铜层而形成。掺杂铜层的顶层被还原成与第一介电层的表面形成平坦化的表面水平。将掺杂的铜退火以驱动金属掺杂剂，以在掺杂铜层的平坦化顶表面上形成金属掺杂物覆盖涂层。

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