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1. 发明申请

US20080132065A1 METHOD FOR REDIRECTING VOID DIFFUSION AWAY FROM VIAS IN AN INTEGRATED CIRCUIT DESIGN 失效
标题翻译：在集成电路设计中从VIAS重新排列无声扩散的方法
公开(公告)号：US20080132065A1
公开(公告)日：2008-06-05
申请号：US12018849
申请日：2008-01-24
申请人： Derryl D. J. Allman , Hemanshu D. Bhatt , Charles E. May , Peter Austin Burke , Byung-Sung Kwak , Sey-Shing Sun , David T. Price , David Pritchard
发明人： Derryl D. J. Allman , Hemanshu D. Bhatt , Charles E. May , Peter Austin Burke , Byung-Sung Kwak , Sey-Shing Sun , David T. Price , David Pritchard
IPC分类号： H01L21/44
CPC分类号： H01L21/76838 , H01L24/02 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/14
摘要： A method for redirecting void diffusion away from vias in an integrated circuit design includes steps of forming an electrical conductor in a first electrically conductive layer of an integrated circuit design, forming a via between a distal end of the electrical conductor and a second electrically conductive layer of the integrated circuit design, and reducing tensile stress in the electrical conductor to divert void diffusion away from the via.
摘要翻译：在集成电路设计中将空隙扩散转向远离通孔的方法包括在集成电路设计的第一导电层中形成电导体的步骤，在电导体的远端和第二导电层之间形成通孔的集成电路设计，并且减小电导体中的拉伸应力以将空隙扩散转移离开通孔。

2. 发明授权

US07582566B2 Method for redirecting void diffusion away from vias in an integrated circuit design 失效
标题翻译：在集成电路设计中将空隙扩散远离过孔的方法
公开(公告)号：US07582566B2
公开(公告)日：2009-09-01
申请号：US12018849
申请日：2008-01-24
申请人： Derryl D. J. Allman , Hemanshu D. Bhatt , Charles E. May , Peter Austin Burke , Byung-Sung Kwak , Sey-Shing Sun , David T. Price , David Pritchard
发明人： Derryl D. J. Allman , Hemanshu D. Bhatt , Charles E. May , Peter Austin Burke , Byung-Sung Kwak , Sey-Shing Sun , David T. Price , David Pritchard
IPC分类号： H01L21/311
CPC分类号： H01L21/76838 , H01L24/02 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/14
摘要： A method for redirecting void diffusion away from vias in an integrated circuit design includes steps of forming an electrical conductor in a first electrically conductive layer of an integrated circuit design, forming a via between a distal end of the electrical conductor and a second electrically conductive layer of the integrated circuit design, and reducing tensile stress in the electrical conductor to divert void diffusion away from the via.
摘要翻译：在集成电路设计中将空隙扩散转向远离通孔的方法包括在集成电路设计的第一导电层中形成电导体的步骤，在电导体的远端和第二导电层之间形成通孔的集成电路设计，并且减小电导体中的拉伸应力以将空隙扩散转移离开通孔。

3. 发明授权

US07436040B2 Method and apparatus for diverting void diffusion in integrated circuit conductors 有权
标题翻译：用于在集成电路导体中转移空穴扩散的方法和装置
公开(公告)号：US07436040B2
公开(公告)日：2008-10-14
申请号：US11323398
申请日：2005-12-29
申请人： Derryl D. J. Allman , Hemanshu D. Bhatt , Charles E. May , Peter Austin Burke , Byung-Sung Kwak , Sey-Shing Sun , David T. Price , David Pritchard
发明人： Derryl D. J. Allman , Hemanshu D. Bhatt , Charles E. May , Peter Austin Burke , Byung-Sung Kwak , Sey-Shing Sun , David T. Price , David Pritchard
IPC分类号： H01L23/58
CPC分类号： H01L21/7682 , H01L21/76808 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A method of diverting void diffusion in an integrated circuit includes steps of forming an electrical conductor having a boundary in a first electrically conductive layer of an integrated circuit, forming a via inside the boundary of the electrical conductor in a dielectric layer between the first electrically conductive layer and a second electrically conductive layer of the integrated circuit, and forming a slot between the via and the boundary of the electrical conductor for diverting void diffusion in the electrical conductor away from the via.
摘要翻译：在集成电路中转移空穴扩散的方法包括以下步骤：在集成电路的第一导电层中形成具有边界的电导体，在电介质层的边界内在第一导电层和第二导电层，并且在电导体的通孔和边界之间形成槽，用于将电导体中的空隙扩散转移离开通孔。

4. 发明授权

US07361965B2 Method and apparatus for redirecting void diffusion away from vias in an integrated circuit design 有权
标题翻译：在集成电路设计中将空隙扩散远离过孔的方法和装置
公开(公告)号：US07361965B2
公开(公告)日：2008-04-22
申请号：US11323400
申请日：2005-12-29
申请人： Derryl D. J. Allman , Hemanshu D. Bhatt , Charles E. May , Peter Austin Burke , Byung-Sung Kwak , Sey-Shing Sun , David T. Price , David Pritchard
发明人： Derryl D. J. Allman , Hemanshu D. Bhatt , Charles E. May , Peter Austin Burke , Byung-Sung Kwak , Sey-Shing Sun , David T. Price , David Pritchard
IPC分类号： H01L23/58
CPC分类号： H01L21/76838 , H01L24/02 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/14
摘要： A method and apparatus for redirecting void diffusion away from vias in an integrated circuit design includes steps of forming an electrical conductor in a first electrically conductive layer of an integrated circuit design, forming a via between a distal end of the electrical conductor and a second electrically conductive layer of the integrated circuit design, and reducing tensile stress in the electrical conductor to divert void diffusion away from the via.
摘要翻译：用于在集成电路设计中将空隙扩散转向远离通孔的方法和装置包括在集成电路设计的第一导电层中形成电导体的步骤，在电导体的远端和第二电导体之间形成通孔集成电路设计的导电层，并且减小电导体中的拉伸应力以将空隙扩散转移离开通孔。

5. 发明授权

US06654226B2 Thermal low k dielectrics 失效
标题翻译：热低k电介质
公开(公告)号：US06654226B2
公开(公告)日：2003-11-25
申请号：US10094520
申请日：2002-03-08
申请人： Charles E. May , Derryl D. J. Allman
发明人： Charles E. May , Derryl D. J. Allman
IPC分类号： H01G406
CPC分类号： H01L21/02129 , H01L21/02203 , H01L21/02216 , H01L21/02282 , H01L21/3122 , H01L21/31625 , H01L21/76828
摘要： An integrated circuit having an electrically insulating layer of an electrically nonconductive material, where the electrically insulating layer is disposed between at least two electrically conductive elements. The electrically nonconductive material is selected from a group of materials having a k value that decreases when subjected to thermal treatment. The electrically nonconductive material is most preferably a boro siloxane.
摘要翻译：一种具有非绝缘材料的电绝缘层的集成电路，其中所述电绝缘层设置在至少两个导电元件之间。非导电材料选自具有在经受热处理时降低的k值的材料组。非导电材料最优选为硼硅氧烷。

6. 发明授权

US07023067B2 Bond pad design 失效
标题翻译：焊盘设计
公开(公告)号：US07023067B2
公开(公告)日：2006-04-04
申请号：US10341082
申请日：2003-01-13
申请人： Derryl D. J. Allman , Charles E. May
发明人： Derryl D. J. Allman , Charles E. May
IPC分类号： H01L31/10
CPC分类号： H01L24/05 , H01L24/48 , H01L2224/04042 , H01L2224/05082 , H01L2224/05093 , H01L2224/05095 , H01L2224/05187 , H01L2224/05556 , H01L2224/05599 , H01L2224/05624 , H01L2224/05647 , H01L2224/4807 , H01L2224/4845 , H01L2224/48463 , H01L2224/85399 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01073 , H01L2924/01074 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , H01L2924/181 , H01L2924/30105 , H01L2224/45099 , H01L2924/00
摘要： A bonding pad for an integrated circuit, where the bonding pad overlies a fragile dielectric layer. A lower metal layer stack overlies the fragile dielectric layer, and a hard dielectric layer overlies the lower metal layer stack. An upper metal layer stack overlies the hard dielectric layer, where the upper metal layer stack forms voids extending into the upper metal layer stack from an exposed upper surface of the upper metal layer stack. The voids define deformable protrusions in the upper surface of the upper metal layer stack, for at least partially absorbing forces applied to the bonding pad during a bonding operation. Electrically conductive vias extend from the lower metal layer stack through the hard dielectric layer to the upper metal layer stack, and electrically connect the lower metal layer stack to the upper metal layer stack.
摘要翻译：一种用于集成电路的焊盘，其中所述焊盘覆盖在脆性介电层上。下部金属层堆叠在脆性介电层之上，并且硬介电层覆盖在下部金属层堆叠上。上部金属层堆叠在硬介电层之上，其中上部金属层堆叠形成从上部金属层堆叠的暴露的上表面延伸到上部金属层堆叠中的空隙。空隙限定上金属层堆叠的上表面中的可变形突起，用于在粘合操作期间至少部分地吸收施加到接合焊盘的力。导电通孔从下金属层堆叠穿过硬介电层延伸到上金属层堆叠，并将下金属层堆叠电连接到上金属层堆叠。

7. 发明授权

US06566244B1 Process for improving mechanical strength of layers of low k dielectric material 有权
标题翻译：用于提高低k介电材料层的机械强度的方法
公开(公告)号：US06566244B1
公开(公告)日：2003-05-20
申请号：US10138609
申请日：2002-05-03
申请人： Charles E. May , Venkatesh P. Gopinath , Peter J. Wright
发明人： Charles E. May , Venkatesh P. Gopinath , Peter J. Wright
IPC分类号： H01L214763
CPC分类号： H01L23/562 , H01L21/76801 , H01L21/76829 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A process for selectively reinforcing portions of a low k dielectric material which comprises first forming a low k dielectric layer, then forming openings in the low k layer in portions of the low k layer needing reinforcement, and then filling the openings with reinforcing material, preferably reinforcing material having a higher Young's modulus of elasticity than the low k dielectric material. Such selective reinforcement of certain portions of low k dielectric material may comprise selectively reinforcing the low k dielectric material beneath the bonding pads, with reinforcing material. The low k dielectric material may be reinforced by openings in the low k dielectric material formed beneath portions of the low k dielectric layer where a capping layer will be formed over the low k dielectric material. Subsequent formation of the capping layer will simultaneously fill the openings with capping material, which may then also function as reinforcement material in the openings.
摘要翻译：一种用于选择性地增强低k介电材料的部分的方法，其包括首先形成低k电介质层，然后在需要加强的低k层的部分中在低k层中形成开口，然后用增强材料填充开口，优选地具有比低k介电材料更高的杨氏弹性模量的增强材料。低k电介质材料的某些部分的这种选择性增强可以包括用增强材料选择性地增强接合焊盘下面的低k电介质材料。低k电介质材料可以通过在低k电介质层的下部形成的低k电介质材料中的开口加强，其中覆盖层将形成在低k电介质材料上。覆盖层的随后的形成将同时用封盖材料填充开口，该封盖材料然后也可以用作开口中的增强材料。

8. 发明授权

US06362510B1 Semiconductor topography having improved active device isolation and reduced dopant migration 有权
标题翻译：半导体形貌具有改进的有源器件隔离和减少掺杂剂迁移
公开(公告)号：US06362510B1
公开(公告)日：2002-03-26
申请号：US09206550
申请日：1998-12-07
申请人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
发明人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
IPC分类号： H01L2976
CPC分类号： H01L21/28202 , H01L21/02381 , H01L21/02532 , H01L21/02573 , H01L21/0262 , H01L21/02639 , H01L21/2822 , H01L21/762 , H01L29/1083 , H01L29/36 , H01L29/518 , H01L29/6659 , H01L29/66651
摘要： A method for fabricating an integrated circuit is presented wherein a semiconductor substrate is provided having a dielectric layer formed on its upper surface. A groove is formed in the dielectric layer that extends from the upper surface of the semiconductor substrate to the upper surface of the dielectric layer. A silicon epitaxial layer is then grown within the groove. Barrier atoms are incorporated into the silicon epitaxial layer concurrently with the epitaxial growth process.
摘要翻译：提出一种用于制造集成电路的方法，其中提供了在其上表面上形成有电介质层的半导体衬底。在从半导体衬底的上表面延伸到电介质层的上表面的电介质层中形成凹槽。然后在沟槽内生长硅外延层。阻挡原子与外延生长工艺同时并入硅外延层。

9. 发明授权

US06348413B1 High pressure N2 RTA process for TiS2 formation 有权
标题翻译：用于TiS2形成的高压N2 RTA工艺
公开(公告)号：US06348413B1
公开(公告)日：2002-02-19
申请号：US09157855
申请日：1998-09-21
申请人： Timothy Z. Hossain , Charles E. May
发明人： Timothy Z. Hossain , Charles E. May
IPC分类号： H01L2144
CPC分类号： H01L29/665 , H01L21/28518 , H01L21/324
摘要： In one aspect of the present invention, a method of forming a layer of silicide on a surface of a silicon-containing structure surface that is separated from a first structure by a second structure is provided. The method includes the steps of forming a layer of silicide-forming material on the surface of the silicon-containing structure, and the first and second structures. The layer of silicide-forming material is annealed in an ambient containing a nitrogen bearing species at a pressure greater than about one atmosphere to form the layer of silicide on the surface of the silicon-containing structure. The nitrogen bearing species reacts with the silicide-forming material to retard the formation of silicide on the third structure. The method reduces the potential for silicide bridging between, for example, the gate and source/drain regions of a transistor during silicide contact formation.
摘要翻译：在本发明的一个方面中，提供了在通过第二结构与第一结构分离的含硅结构表面的表面上形成硅化物层的方法。该方法包括以下步骤：在含硅结构的表面上形成硅化物形成层，以及第一和第二结构。硅化物形成材料层在含有含氮物质的环境中在大于约一个大气压的温度下退火，以在含硅结构的表面上形成硅化物层。含氮物质与硅化物形成材料反应以阻止第三结构上的硅化物的形成。该方法在硅化物接触形成期间降低例如晶体管的栅极和源极/漏极区域之间的硅化物桥接的可能性。

10. 发明授权

US06338992B1 Programmable read only memory in CMOS process flow 有权
公开(公告)号：US06338992B1
公开(公告)日：2002-01-15
申请号：US09726107
申请日：2000-11-29
申请人： Shafqat Ahmed , Hemanshu D. Bhatt , Charles E. May , Robindranath Banerjee
发明人： Shafqat Ahmed , Hemanshu D. Bhatt , Charles E. May , Robindranath Banerjee
IPC分类号： H01L218238
CPC分类号： H01L27/112 , H01L21/8238
摘要： An improvement to a process for manufacturing complementary metal oxide semiconductor devices on a monolithic substrate, where the improved process forms nonvolatile memory devices and programmable logic devices. The improvement includes exposing gate electrodes of a selected portion of the complementary metal oxide semiconductor devices at a point in the process where the gate electrodes have been previously covered by a protective material layer. A capacitive material layer is deposited on the monolithic substrate, such that it contacts the exposed gate electrodes of the selected portion of the complementary metal oxide semiconductor devices. A top electrode material layer is deposited on the monolithic substrate, such that the top electrode material layer contacts the capacitive material layer in a region overlying the exposed gate electrodes of the selected portion of the complementary metal oxide semiconductor devices. The top electrode material layer and the capacitive material layer are removed to substantially the level of the upper surface of the protective material layer, thereby leaving the top electrode layer and the capacitive material layer overlying the gate electrodes for the selected portion of the complementary metal oxide semiconductor devices. In this manner, capacitors are formed from the top electrode material layer, the capacitive material layer, and the gate electrodes of the selected portion of the complementary metal oxide semiconductor devices. The improved process further includes forming nonvolatile memory devices from the selected portion of the complementary metal oxide semiconductor devices, and forming logic devices of the complementary metal oxide semiconductor devices that are not included in the selected portion of the complementary metal oxide semiconductor devices. Fuses are formed in associated with a portion of the nonvolatile memory devices to form read only memory devices of the fused portion of the nonvolatile memory devices.

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