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1. 发明授权

US06566244B1 Process for improving mechanical strength of layers of low k dielectric material 有权
标题翻译：用于提高低k介电材料层的机械强度的方法
公开(公告)号：US06566244B1
公开(公告)日：2003-05-20
申请号：US10138609
申请日：2002-05-03
申请人： Charles E. May , Venkatesh P. Gopinath , Peter J. Wright
发明人： Charles E. May , Venkatesh P. Gopinath , Peter J. Wright
IPC分类号： H01L214763
CPC分类号： H01L23/562 , H01L21/76801 , H01L21/76829 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A process for selectively reinforcing portions of a low k dielectric material which comprises first forming a low k dielectric layer, then forming openings in the low k layer in portions of the low k layer needing reinforcement, and then filling the openings with reinforcing material, preferably reinforcing material having a higher Young's modulus of elasticity than the low k dielectric material. Such selective reinforcement of certain portions of low k dielectric material may comprise selectively reinforcing the low k dielectric material beneath the bonding pads, with reinforcing material. The low k dielectric material may be reinforced by openings in the low k dielectric material formed beneath portions of the low k dielectric layer where a capping layer will be formed over the low k dielectric material. Subsequent formation of the capping layer will simultaneously fill the openings with capping material, which may then also function as reinforcement material in the openings.
摘要翻译：一种用于选择性地增强低k介电材料的部分的方法，其包括首先形成低k电介质层，然后在需要加强的低k层的部分中在低k层中形成开口，然后用增强材料填充开口，优选地具有比低k介电材料更高的杨氏弹性模量的增强材料。低k电介质材料的某些部分的这种选择性增强可以包括用增强材料选择性地增强接合焊盘下面的低k电介质材料。低k电介质材料可以通过在低k电介质层的下部形成的低k电介质材料中的开口加强，其中覆盖层将形成在低k电介质材料上。覆盖层的随后的形成将同时用封盖材料填充开口，该封盖材料然后也可以用作开口中的增强材料。

2. 发明授权

US07026217B1 Method of forming an antifuse on a semiconductor substrate using wet oxidation of a nitrided substrate 失效
标题翻译：在氮化衬底的湿氧化下在半导体衬底上形成反熔丝的方法
公开(公告)号：US07026217B1
公开(公告)日：2006-04-11
申请号：US10697446
申请日：2003-10-29
申请人： Arvind Kamath , Venkatesh P. Gopinath , Wen-Chin Yeh , David Pachura
发明人： Arvind Kamath , Venkatesh P. Gopinath , Wen-Chin Yeh , David Pachura
IPC分类号： H01L21/336
CPC分类号： H01L21/31662 , H01L21/02238 , H01L21/02255 , H01L21/02299 , H01L21/28211 , H01L21/2822 , H01L21/28238 , H01L21/76224 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： A method of producing an antifuse includes introducing nitrogen by ion implantation means into the substrate. An oxide dielectric layer is then formed on the nitrided substrate in a wet oxidation ambient. The conditions of the ion implantation and the oxidation are controlled to generate a dielectric with uniform thickness and a low breakdown voltage when subjected to a high electric field.
摘要翻译：制造反熔丝的方法包括通过离子注入装置将氮引入衬底。然后在湿氧化环境中在氮化衬底上形成氧化物介电层。控制离子注入和氧化的条件以产生具有均匀厚度的电介质和当受到高电场时的低击穿电压。

3. 发明授权

US07001823B1 Method of manufacturing a shallow trench isolation structure with low trench parasitic capacitance 有权
标题翻译：制造具有低沟槽寄生电容的浅沟槽隔离结构的方法
公开(公告)号：US07001823B1
公开(公告)日：2006-02-21
申请号：US09991202
申请日：2001-11-14
申请人： Venkatesh P. Gopinath , Arvind Kamath , Mohammad R. Mirabedini , Ming-Yi Lee
发明人： Venkatesh P. Gopinath , Arvind Kamath , Mohammad R. Mirabedini , Ming-Yi Lee
IPC分类号： H01L21/76
CPC分类号： H01L21/76224
摘要： Provided are methods and composition for forming an isolation structure on an integrated circuit substrate. First, a trench is etched in the integrated circuit substrate. A lower dielectric layer is then formed in the trench such that the lower dielectric layer at least partially fills the trench. An upper dielectric layer is then formed over the lower dielectric layer to create an isolation structure, the upper dielectric layer and the lower dielectric layer together having an effective dielectric constant that is less than that of silicon dioxide, thereby enabling capacitance associated with the isolation structure to be reduced.
摘要翻译：提供了用于在集成电路基板上形成隔离结构的方法和组合物。首先，在集成电路基板中蚀刻沟槽。然后在沟槽中形成下介电层，使得下电介质层至少部分地填充沟槽。然后在下介电层上形成上电介质层以产生隔离结构，上电介质层和下电介质层一起具有小于二氧化硅的有效介电常数，从而实现与隔离结构相关联的电容要减少

4. 发明授权

US07189628B1 Fabrication of trenches with multiple depths on the same substrate 有权
标题翻译：在同一基板上制作具有多个深度的沟槽
公开(公告)号：US07189628B1
公开(公告)日：2007-03-13
申请号：US10931605
申请日：2004-08-31
申请人： Mohammad R. Mirbedini , Venkatesh P. Gopinath , Hong Lin , Verne Hornback , Dodd Defibaugh , Ynhi Le
发明人： Mohammad R. Mirbedini , Venkatesh P. Gopinath , Hong Lin , Verne Hornback , Dodd Defibaugh , Ynhi Le
IPC分类号： H01L21/461
CPC分类号： H01L21/76232 , H01L21/76229 , H01L21/76283
摘要： Dual trench depths are achieved on the same wafer by forming an initial trench having a depth corresponding to the difference in final depths of the shallow and deep trenches. A second mask is used to open areas for the deep trenches over the preliminary trenches and for the shallow trenches at additional locations. Etching of the shallow and deep trenches then proceeds simultaneously.
摘要翻译：通过形成具有对应于浅沟槽和深沟槽的最终深度的差的深度的初始沟槽，在同一晶片上实现双沟槽深度。第二个掩模用于打开初步沟槽上的深沟槽的区域，并在另外的位置打开浅沟槽。浅沟和深沟的蚀刻然后同时进行。

5. 发明授权

US06734081B1 Shallow trench isolation structure for laser thermal processing 有权
标题翻译：浅沟槽隔离结构，用于激光热处理
公开(公告)号：US06734081B1
公开(公告)日：2004-05-11
申请号：US09999848
申请日：2001-10-24
申请人： Helmut Puchner , Venkatesh P. Gopinath
发明人： Helmut Puchner , Venkatesh P. Gopinath
IPC分类号： H01L2176
CPC分类号： H01L21/76224 , H01L21/268 , H01L21/823878
摘要： Provided are methods and composition for forming an isolation structure on an integrated circuit substrate. A trench is etched in the integrated circuit substrate. A light barrier layer is then formed in the trench such that the light barrier layer at least partially fills the trench to create an isolation structure, the light barrier layer being adapted for absorbing laser light applied during laser thermal processing, thereby preventing damage to the integrated circuit substrate. For instance, the light barrier layer may be a conductive layer such as polysilicon. A dielectric layer is then formed over the isolation structure. The dielectric layer may be adapted for transferring heat generated by the laser thermal processing to the light barrier layer. For instance, the dielectric layer may be formed through oxidation of a top surface of the light barrier layer.
摘要翻译：提供了用于在集成电路基板上形成隔离结构的方法和组合物。在集成电路基板中蚀刻沟槽。然后在沟槽中形成光阻挡层，使得光阻层至少部分地填充沟槽以产生隔离结构，光阻层适于吸收在激光热处理期间施加的激光，从而防止对集成电路基板。例如，光阻挡层可以是诸如多晶硅的导电层。然后在隔离结构上形成介电层。电介质层可以适于将由激光热处理产生的热量传递到光阻挡层。例如，可以通过氧化遮光层的顶表面来形成电介质层。

6. 发明授权

US08021955B1 Method characterizing materials for a trench isolation structure having low trench parasitic capacitance 有权
标题翻译：用于具有低沟槽寄生电容的沟槽隔离结构的方法表征材料
公开(公告)号：US08021955B1
公开(公告)日：2011-09-20
申请号：US12574426
申请日：2009-10-06
申请人： Venkatesh P. Gopinath , Arvind Kamath , Mohammad R. Mirabedini , Ming-Yi Lee
发明人： Venkatesh P. Gopinath , Arvind Kamath , Mohammad R. Mirabedini , Ming-Yi Lee
IPC分类号： H01L21/76
CPC分类号： H01L21/76224
摘要： Provided are methods and composition for forming a multi-layer isolation structure on an integrated circuit substrate. A process can include selecting a lower dielectric material for the lower dielectric layer and selecting an upper dielectric material for the upper dielectric layer. A range of effective dielectric constants that correspond to the thicknesses the lower and upper dielectric materials are selected. A range of thicknesses for each of the lower and upper dielectric layers are determined from a range of acceptable dielectric constants using information indicating an effective dielectric constant corresponding to thicknesses of the materials for both the lower upper dielectric layers, enabling the formation of the multi-layer isolation structure.
摘要翻译：提供了用于在集成电路基板上形成多层隔离结构的方法和组合物。工艺可以包括为下电介质层选择下电介质材料，并选择用于上电介质层的上电介质材料。选择对应于下部和上部介电材料的厚度的一系列有效介电常数。下介电层和上电介质层中的每一个的厚度范围由可接受的介电常数的范围决定，使用表示与下部上部电介质层的材料的厚度对应的有效介电常数的信息，能够形成多层电介质层，层隔离结构。

7. 发明申请

US20100281442A1 TECHNIQUE FOR DETERMINING CIRCUIT INTERDEPENDENCIES 有权
标题翻译：确定电路间接性的技术
公开(公告)号：US20100281442A1
公开(公告)日：2010-11-04
申请号：US12432002
申请日：2009-04-29
申请人： Paul J. Dickinson , Venkatesh P. Gopinath , Karl P. Dahlgren , Liang-Chi Chen
发明人： Paul J. Dickinson , Venkatesh P. Gopinath , Karl P. Dahlgren , Liang-Chi Chen
IPC分类号： G06F17/50
CPC分类号： G01R31/31835
摘要： Embodiments of a device (such as a computer system or a circuit tester), a method, and a computer-program product (i.e., software) for use with the device are described. These systems and processes may be used to statistically characterize interdependencies between sub-circuits in an integrated circuit (which are referred to as ‘aggressor-victim relationships’). In particular, statistical relationships between the aggressors and victims are determined from values of a performance metric (such as clock speed) when the integrated circuit fails for a group of state-change difference vectors. Using these statistical relationships, a worst-case sub-group of the state-change difference vectors, such as the worst-case sub-group, is selected. This sub-group can be used to accurately test the integrated circuit.
摘要翻译：描述了与设备一起使用的设备（例如计算机系统或电路测试器），方法和计算机程序产品（即，软件）的实施例。这些系统和过程可以用于统计学地表征集成电路中的子电路之间的相互依赖性（被称为“侵略者 - 受害者关系”）。特别地，当集成电路针对一组状态变化差矢量失效时，侵略者和受害者之间的统计关系由性能度量（例如时钟速度）的值确定。使用这些统计关系，选择状态变化差向量的最坏情况子组，例如最坏情况子组。该子组可用于准确测试集成电路。

8. 发明授权

US06864152B1 Fabrication of trenches with multiple depths on the same substrate 有权
标题翻译：在同一基板上制作具有多个深度的沟槽
公开(公告)号：US06864152B1
公开(公告)日：2005-03-08
申请号：US10442533
申请日：2003-05-20
申请人： Mohammad R. Mirbedini , Venkatesh P. Gopinath , Hong Lin , Verne Hornback , Dodd Defibaugh , Ynhi Le
发明人： Mohammad R. Mirbedini , Venkatesh P. Gopinath , Hong Lin , Verne Hornback , Dodd Defibaugh , Ynhi Le
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76232 , H01L21/76229 , H01L21/76283
摘要： Dual trench depths are achieved on the same wafer by forming an initial trench having a depth corresponding to the difference in final depths of the shallow and deep trenches. A second mask is used to open areas for the deep trenches over the preliminary trenches and for the shallow trenches at additional locations. Etching of the shallow and deep trenches then proceeds simultaneously.
摘要翻译：通过形成具有对应于浅沟槽和深沟槽的最终深度的差的深度的初始沟槽，在同一晶片上实现双沟槽深度。第二个掩模用于打开初步沟槽上的深沟槽的区域，并在另外的位置打开浅沟槽。浅沟和深沟的蚀刻然后同时进行。

9. 发明授权

US09368198B1 Circuits and methods for placing programmable impedance memory elements in high impedance states 有权
标题翻译：将可编程阻抗存储器元件置于高阻态中的电路和方法
公开(公告)号：US09368198B1
公开(公告)日：2016-06-14
申请号：US14281830
申请日：2014-05-19
申请人： Deepak Kamalanathan , Juan Pablo Saenz Echeverry , Venkatesh P. Gopinath
发明人： Deepak Kamalanathan , Juan Pablo Saenz Echeverry , Venkatesh P. Gopinath
IPC分类号： G11C11/00 , G11C13/00
CPC分类号： G11C13/0011 , G11C13/0038 , G11C13/0069 , G11C13/0097 , G11C2013/0073
摘要： A memory device can include a plurality of two terminal conductive bridging random access memory (CBRAM) type memory elements; at least one program transistor configured to enable a program current to flow through at least one memory element in response to the application of a program signal at its control terminal and a program bias voltage to the memory element; and an erase load circuit that includes at least one two-terminal diode-like load element, the erase load circuit configured to enable an erase current to flow through the load element and at least one memory element in a direction opposite to that of the program current.
摘要翻译：存储器件可以包括多个两端导电桥接随机存取存储器（CBRAM）型存储器元件; 至少一个程序晶体管被配置为响应于在其控制端处应用程序信号而使程序电流流过至少一个存储器元件，并且将程序偏置电压提供给存储器元件; 以及擦除负载电路，其包括至少一个二端二极管状负载元件，所述擦除负载电路被配置为使得擦除电流能够以与所述程序相反的方向流过所述负载元件和至少一个存储元件当前。

10. 发明授权

US07619294B1 Shallow trench isolation structure with low trench parasitic capacitance 失效
标题翻译：浅沟槽隔离结构具有低沟槽寄生电容
公开(公告)号：US07619294B1
公开(公告)日：2009-11-17
申请号：US11262173
申请日：2005-10-28
申请人： Venkatesh P. Gopinath , Arvind Kamath , Mohammad R. Mirabedini , Ming-Yi Lee
发明人： Venkatesh P. Gopinath , Arvind Kamath , Mohammad R. Mirabedini , Ming-Yi Lee
IPC分类号： H01L21/76
CPC分类号： H01L21/76224
摘要： Provided are methods and composition for forming an isolation structure on an integrated circuit substrate. First, a trench is etched in the integrated circuit substrate. A lower dielectric layer is then formed in the trench such that the lower dielectric layer at least partially fills the trench. An upper dielectric layer is then formed over the lower dielectric layer to create an isolation structure, the upper dielectric layer and the lower dielectric layer together having an effective dielectric constant that is less than that of silicon dioxide, thereby enabling capacitance associated with the isolation structure to be reduced.
摘要翻译：提供了用于在集成电路基板上形成隔离结构的方法和组合物。首先，在集成电路基板中蚀刻沟槽。然后在沟槽中形成下介电层，使得下电介质层至少部分地填充沟槽。然后在下介电层上形成上电介质层以产生隔离结构，上电介质层和下电介质层一起具有小于二氧化硅的有效介电常数，从而实现与隔离结构相关联的电容要减少

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