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1. 发明授权

US06495881B1 Programmable read only memory in CMOS process flow 有权
公开(公告)号：US06495881B1
公开(公告)日：2002-12-17
申请号：US10012835
申请日：2001-10-22
申请人： Shafqat Ahmed , Hemanshu D. Bhatt , Charles E. May , Robindranath Banerjee
发明人： Shafqat Ahmed , Hemanshu D. Bhatt , Charles E. May , Robindranath Banerjee
IPC分类号： H01L29788
CPC分类号： H01L27/112 , H01L21/8238
摘要： An improvement to a process for manufacturing complementary metal oxide semiconductor devices on a monolithic substrate, where the improved process forms nonvolatile memory devices and programmable logic devices. The improvement includes exposing gate electrodes of a selected portion of the complementary metal oxide semiconductor devices at a point in the process where the gate electrodes have been previously covered by a protective material layer. A capacitive material layer is deposited on the monolithic substrate, such that it contacts the exposed gate electrodes of the selected portion of the complementary metal oxide semiconductor devices. A top electrode material layer is deposited on the monolithic substrate, such that the top electrode material layer contacts the capacitive material layer in a region overlying the exposed gate electrodes of the selected portion of the complementary metal oxide semiconductor devices. The top electrode material layer and the capacitive material layer are removed to substantially the level of the upper surface of the protective material layer, thereby leaving the top electrode layer and the capacitive material layer overlying the gate electrodes for the selected portion of the complementary metal oxide semiconductor devices. In this manner, capacitors are formed from the top electrode material layer, the capacitive material layer, and the gate electrodes of the selected portion of the complementary metal oxide semiconductor devices. The improved process further includes forming nonvolatile memory devices from the selected portion of the complementary metal oxide semiconductor devices, and forming logic devices of the complementary metal oxide semiconductor devices that are not included in the selected portion of the complementary metal oxide semiconductor devices. Fuses are formed in associated with a portion of the nonvolatile memory devices to form read only memory devices of the fused portion of the nonvolatile memory devices.

2. 发明授权

US06482075B1 Process for planarizing an isolation structure in a substrate 有权
标题翻译：用于平坦化衬底中的隔离结构的方法
公开(公告)号：US06482075B1
公开(公告)日：2002-11-19
申请号：US09670998
申请日：2000-09-27
申请人： Hemanshu D. Bhatt , Shafqat Ahmed , Robindranath Banerjee , Charles E. May
发明人： Hemanshu D. Bhatt , Shafqat Ahmed , Robindranath Banerjee , Charles E. May
IPC分类号： B24B100
CPC分类号： H01L21/76232 , H01L21/76229
摘要： A process is described for planarizing an isolation structure in a substrate. The process includes depositing a pad protective material over an upper surface of the substrate, and selectively removing portions of the pad protective material to expose portions of the substrate and to form sidewalls in the pad protective material. A trench is formed in the exposed portions of the substrate, and a trench fill material is deposited in the trench and over the pad protective material. A trench protective material is deposited over the trench fill material and in contact with the sidewalls of the pad protective material, such that the pad protective material and portions of the trench protective material together form a continuous protective material layer. Portions of the trench protective material and the trench fill material are selectively removed down to the level of the upper surface of the pad protective material. Finally, the pad protective material and any remaining trench protective material is removed, leaving the trench filled with trench fill material that is planarized at the upper surface of the substrate. By forming a continuous protective material layer that completely covers the trench fill material in the trench, that material is protected during later process steps that nonselectively remove trench fill material lying outside the trench. In this manner, the trench fill material lying outside the trench may be removed without photolithographic masking and patterning steps. Thus, the process according to the invention reduces the cost and complexity of planarizing the trench fill material.
摘要翻译：描述了用于平坦化衬底中的隔离结构的过程。该方法包括在衬底的上表面上沉积衬垫保护材料，以及选择性地去除衬垫保护材料的部分以暴露衬底的部分并在衬垫保护材料中形成侧壁。在衬底的暴露部分中形成沟槽，并且沟槽填充材料沉积在沟槽中并在衬垫保护材料上方。沟槽保护材料沉积在沟槽填充材料上并与衬垫保护材料的侧壁接触，使得衬垫保护材料和沟槽保护材料的一部分一起形成连续的保护材料层。选择性地将沟槽保护材料和沟槽填充材料的部分向下移动到焊盘保护材料的上表面的高度。最后，去除衬垫保护材料和任何剩余的沟槽保护材料，留下填充沟槽填充材料的沟槽，其在衬底的上表面处被平坦化。通过形成完全覆盖沟槽中的沟槽填充材料的连续保护材料层，该材料在后续工艺步骤期间受到保护，非选择性地去除位于沟槽外部的沟槽填充材料。以这种方式，可以在没有光刻掩模和图案化步骤的情况下去除位于沟槽外部的沟槽填充材料。因此，根据本发明的方法降低了沟槽填充材料的平面化的成本和复杂性。

3. 发明授权

US06338992B1 Programmable read only memory in CMOS process flow 有权
公开(公告)号：US06338992B1
公开(公告)日：2002-01-15
申请号：US09726107
申请日：2000-11-29
申请人： Shafqat Ahmed , Hemanshu D. Bhatt , Charles E. May , Robindranath Banerjee
发明人： Shafqat Ahmed , Hemanshu D. Bhatt , Charles E. May , Robindranath Banerjee
IPC分类号： H01L218238
CPC分类号： H01L27/112 , H01L21/8238
摘要： An improvement to a process for manufacturing complementary metal oxide semiconductor devices on a monolithic substrate, where the improved process forms nonvolatile memory devices and programmable logic devices. The improvement includes exposing gate electrodes of a selected portion of the complementary metal oxide semiconductor devices at a point in the process where the gate electrodes have been previously covered by a protective material layer. A capacitive material layer is deposited on the monolithic substrate, such that it contacts the exposed gate electrodes of the selected portion of the complementary metal oxide semiconductor devices. A top electrode material layer is deposited on the monolithic substrate, such that the top electrode material layer contacts the capacitive material layer in a region overlying the exposed gate electrodes of the selected portion of the complementary metal oxide semiconductor devices. The top electrode material layer and the capacitive material layer are removed to substantially the level of the upper surface of the protective material layer, thereby leaving the top electrode layer and the capacitive material layer overlying the gate electrodes for the selected portion of the complementary metal oxide semiconductor devices. In this manner, capacitors are formed from the top electrode material layer, the capacitive material layer, and the gate electrodes of the selected portion of the complementary metal oxide semiconductor devices. The improved process further includes forming nonvolatile memory devices from the selected portion of the complementary metal oxide semiconductor devices, and forming logic devices of the complementary metal oxide semiconductor devices that are not included in the selected portion of the complementary metal oxide semiconductor devices. Fuses are formed in associated with a portion of the nonvolatile memory devices to form read only memory devices of the fused portion of the nonvolatile memory devices.

4. 发明授权

US06495419B1 Nonvolatile memory in CMOS process flow 有权
标题翻译： CMOS工艺流程中的非易失性存储器
公开(公告)号：US06495419B1
公开(公告)日：2002-12-17
申请号：US09670997
申请日：2000-09-27
申请人： Shafqat Ahmed , Hemanshu D. Bhatt , Robindranath Banerjee
发明人： Shafqat Ahmed , Hemanshu D. Bhatt , Robindranath Banerjee
IPC分类号： H01L21336
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11546
摘要： An improvement to a process for manufacturing complementary metal oxide semiconductor devices on a monolithic substrate, where the improved process forms nonvolatile memory devices and programmable logic devices. The improvement includes exposing gate electrodes of a selected portion of the complementary metal oxide semiconductor devices at a point in the process where the gate electrodes have been previously covered by a protective material layer. A capacitive material layer is deposited on the monolithic substrate, such that it contacts the exposed gate electrodes of the selected portion of the complementary metal oxide semiconductor devices. A top electrode material layer is deposited on the monolithic substrate, such that the top electrode material layer contacts the capacitive material layer in a region overlying the exposed gate electrodes of the selected portion of the complementary metal oxide semiconductor devices. The top electrode material layer and the capacitive material layer are removed to substantially the level of the upper surface of the protective material layer, thereby leaving the top electrode layer and the capacitive material layer overlying the gate electrodes for the selected portion of the complementary metal oxide semiconductor devices. In this manner, capacitors are formed from the top electrode material layer, the capacitive material layer, and the gate electrodes of the selected portion of the complementary metal oxide semiconductor devices. The improved process further includes forming nonvolatile memory devices from the selected portion of the complementary metal oxide semiconductor devices, and forming logic devices of the complementary metal oxide semiconductor devices that are not included in the selected portion of the complementary metal oxide semiconductor devices.
摘要翻译：在单片基板上制造互补金属氧化物半导体器件的方法的改进，其中改进的工艺形成非易失性存储器件和可编程逻辑器件。该改进包括在栅电极预先被保护材料层覆盖的工艺中的一点处暴露互补金属氧化物半导体器件的选定部分的栅电极。电容材料层沉积在整体式衬底上，使得它与互补金属氧化物半导体器件的所选部分的暴露的栅电极接触。顶部电极材料层沉积在单片基板上，使得顶部电极材料层在覆盖互补金属氧化物半导体器件的选定部分的暴露的栅电极的区域中接触电容材料层。顶部电极材料层和电容材料层被去除到保护材料层的上表面的基本水平，从而使顶部电极层和电容材料层覆盖在栅电极上用于互补金属氧化物的选定部分半导体器件。以这种方式，从互补金属氧化物半导体器件的选定部分的顶部电极材料层，电容材料层和栅电极形成电容器。改进的方法还包括从互补金属氧化物半导体器件的选定部分形成非易失性存储器件，以及形成不包括在互补金属氧化物半导体器件的选定部分中的互补金属氧化物半导体器件的逻辑器件。

5. 发明授权

US06537923B1 Process for forming integrated circuit structure with low dielectric constant material between closely spaced apart metal lines 有权
公开(公告)号：US06537923B1
公开(公告)日：2003-03-25
申请号：US09704200
申请日：2000-10-31
申请人： Hemanshu D. Bhatt , Shafqat Ahmed , Robindranath Banerjee
发明人： Hemanshu D. Bhatt , Shafqat Ahmed , Robindranath Banerjee
IPC分类号： H01L2131
CPC分类号： H01L21/76819 , H01L21/31053 , H01L21/31116 , H01L21/76802 , H01L21/76828 , H01L21/76831 , H01L21/76834 , H01L21/76837 , H01L23/5222 , H01L23/53223 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A capping layer of an insulator such as silicon nitride is formed over horizontally closely spaced apart metal lines on an oxide layer of an integrated circuit structure formed on a semiconductor substrate. Low k silicon oxide dielectric material which exhibits void-free deposition properties in high aspect ratio regions between the closely spaced apart metal lines is then deposited over and between the metal lines and over the silicon nitride caps on the metal lines. After the formation of such low k silicon oxide dielectric material between the closely spaced apart metal lines and the over silicon nitride caps thereon, a second layer of silicon nitride is deposited over the layer of low k silicon oxide dielectric material. This second silicon nitride layer acts as a protective layer over portions of the layer of low k silicon oxide dielectric material between the metal lines which may be lower that the top surface of the silicon nitride caps on the metal lines to prevent further etching or dishing of those portions of the layer of low k silicon oxide dielectric material during the planarizing step. The structure is then planarized to bring the level of the low k silicon oxide dielectric material down to the level of the tops of the silicon nitride caps on the metal lines. A further layer of standard k silicon oxide dielectric material is then formed over the planarized void-free low k silicon oxide dielectric layer and the silicon nitride caps. Vias are then formed through the standard k silicon oxide dielectric layer and the silicon nitride caps down to the metal lines. Since the vias are not formed through the low k silicon oxide dielectric material, formation of the vias does not contribute to poisoning of the vias. However, the presence of the low k silicon oxide dielectric material between the horizontally closely spaced apart metal lines reduces the horizontal capacitance between such metal lines.

6. 发明授权

US09950404B1 High throughput polishing system for workpieces 有权
公开(公告)号：US09950404B1
公开(公告)日：2018-04-24
申请号：US13434726
申请日：2012-03-29
申请人： Stephen M. Fisher , Robindranath Banerjee , Christopher L. Beaudry , Brian J. Brown
发明人： Stephen M. Fisher , Robindranath Banerjee , Christopher L. Beaudry , Brian J. Brown
IPC分类号： B24B37/04 , B24B7/22
CPC分类号： B24B7/228 , B24B7/224 , B24B27/0023 , B24B27/0069 , B24B27/0076 , B24B37/105 , B24B37/345 , B24B41/005 , H01L21/67173 , H01L21/67219 , H01L21/6776 , H01L31/00
摘要： A method and system for polishing a plurality of workpieces is disclosed. The method and system comprises providing a polishing tool with multiple polishing heads; and providing a substrate tray that can hold the plurality of work pieces in a fixed position on a tray underneath the polishing heads. The system and method includes moving the tray within the polisher. Finally, the method and system includes configuring the multiple polishing heads with the appropriate pad/slurry combinations to polish the workpieces and to create a finished polished surface on the plurality of work pieces.

7. 发明授权

US06960979B2 Low temperature coefficient resistor 失效
标题翻译：低温系数电阻
公开(公告)号：US06960979B2
公开(公告)日：2005-11-01
申请号：US10615039
申请日：2003-07-08
申请人： Robindranath Banerjee
发明人： Robindranath Banerjee
IPC分类号： H01C7/00 , H01L21/02 , H01L27/08 , H01C7/06
CPC分类号： H01L28/20 , H01C7/006 , H01C7/008 , H01L27/0802
摘要： A resistor having a desired temperature coefficient of resistance and a total electrical resistance. A first resistor segment has a first temperature coefficient of resistance and a first electrical resistance. A second resistor segment has a second temperature coefficient of resistance and a second electrical resistance. The first resistor segment is electrically connected in series with the second resistor segment, and the total electrical resistance equals a sum of the first electrical resistance and the second electrical resistance. The desired temperature coefficient of resistance is determined at least in part by the first temperature coefficient of resistance and the first electrical resistance of the first resistor and the second temperature coefficient of resistance and the second electrical resistance of the second resistor. Thus, in this manner the desired temperature coefficient of resistance of the resistor can be tailored to a desired value by selecting the resistance and temperature coefficients of resistance of the first and second resistor segments that are connected in series. The desired temperature coefficient of resistance can selectively be a positive value, a negative value, or a zero value, depending upon the selection of the material and the resulting resistance values and temperature coefficient of resistance values for the first and second resistor segments.
摘要翻译：具有期望的电阻温度系数和总电阻的电阻器。第一电阻器段具有第一温度系数电阻和第一电阻。第二电阻器段具有第二电阻温度系数和第二电阻。第一电阻器段与第二电阻器段串联电连接，总电阻等于第一电阻和第二电阻之和。期望的电阻温度系数至少部分地由第一电阻温度系数和第一电阻器的第一电阻以及第二电阻温度系数和第二电阻器的第二电阻确定。因此，以这种方式，通过选择串联连接的第一和第二电阻器段的电阻和电阻温度系数，可以将电阻器的期望温度系数调整到期望值。取决于材料的选择和所得到的电阻值和第一和第二电阻器段的电阻值的温度系数，所需的电阻温度系数可以选择性地为正值，负值或零值。

8. 发明授权

US06621404B1 Low temperature coefficient resistor 有权
标题翻译：低温系数电阻
公开(公告)号：US06621404B1
公开(公告)日：2003-09-16
申请号：US10002413
申请日：2001-10-23
申请人： Robindranath Banerjee
发明人： Robindranath Banerjee
IPC分类号： H01C706
CPC分类号： H01L28/20 , H01C7/006 , H01C7/008 , H01L27/0802
摘要： A resistor having a desired temperature coefficient of resistance and a total electrical resistance. A first resistor segment has a first temperature coefficient of resistance and a first electrical resistance. A second resistor segment has a second temperature coefficient of resistance and a second electrical resistance. The first resistor segment is electrically connected in series with the second resistor segment, and the total electrical resistance equals a sum of the first electrical resistance and the second electrical resistance. The desired temperature coefficient of resistance is determined at least in part by the first temperature coefficient of resistance and the first electrical resistance of the first resistor and the second temperature coefficient of resistance and the second electrical resistance of the second resistor. Thus, in this manner the desired temperature coefficient of resistance of the resistor can be tailored to a desired value by selecting the resistance and temperature coefficients of resistance of the first and second resistor segments that are connected in series. The desired temperature coefficient of resistance can selectively be a positive value, a negative value, or a zero value, depending upon the selection of the material and the resulting resistance values and temperature coefficient of resistance values for the first and second resistor segments.
摘要翻译：具有期望的电阻温度系数和总电阻的电阻器。第一电阻器段具有第一温度系数电阻和第一电阻。第二电阻器段具有第二电阻温度系数和第二电阻。第一电阻器段与第二电阻器段串联电连接，总电阻等于第一电阻和第二电阻之和。期望的电阻温度系数至少部分地由第一电阻温度系数和第一电阻器的第一电阻以及第二电阻温度系数和第二电阻器的第二电阻确定。因此，以这种方式，通过选择串联连接的第一和第二电阻器段的电阻和电阻温度系数，可以将电阻器的期望温度系数调整到期望值。取决于材料的选择和所得到的电阻值和第一和第二电阻器段的电阻值的温度系数，所需的电阻温度系数可以选择性地为正值，负值或零值。

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