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1. 发明申请

US20120120577A1 REDUNDANT CLOCK CHANNEL FOR HIGH RELIABILITY CONNECTORS 失效
标题翻译：用于高可靠性连接器的冗余时钟通道
公开(公告)号：US20120120577A1
公开(公告)日：2012-05-17
申请号：US12946328
申请日：2010-11-15
申请人： Sungjun Chun , Daniel M. Dreps , Dierk Kaller , Rohan U. Mandrekar , Lei Shan
发明人： Sungjun Chun , Daniel M. Dreps , Dierk Kaller , Rohan U. Mandrekar , Lei Shan
IPC分类号： G06F1/16
CPC分类号： G06F1/185 , G06F1/10
摘要： A memory module configured to connect to a slot of a data processing system. A set of tabs is connected to the module and configured to electrically connect the module to the slot and to electrically connect the module to a clock of the data processing system. The set of tabs includes a first tab, a second tab, a third tab, and a fourth tab. The first tab and the second tab are opposite the third tab and the fourth tab. The first tab comprises a positive type tab, the second tab comprises a negative type tab, the third tab comprises a positive type tab, and the fourth tab comprises a negative type tab. The first and third tabs are configured to provide a first electrical connection to the clock. The second and fourth tabs are configured to provide a second electrical connection to the clock. Together, the first, second, third, and fourth tabs comprise two dual tabs.
摘要翻译：配置为连接到数据处理系统的时隙的存储器模块。一组标签连接到模块并且被配置为将模块电连接到插槽并且将模块电连接到数据处理系统的时钟。该组标签包括第一标签，第二标签，第三标签和第四标签。第一个选项卡和第二个选项卡与第三个选项卡和第四个选项卡相对。第一标签包括一个正型标签，该第二标签包括一个负型标签，该第三标签包括一个正型标签，该第四标签包括一个负型标签。第一和第三选项卡被配置为提供到时钟的第一电连接。第二和第四选项卡被配置为提供与时钟的第二电连接。一起，第一，第二，第三和第四标签包括两个双标签。

2. 发明授权

US08257092B2 Redundant clock channel for high reliability connectors 失效
标题翻译：冗余时钟通道，用于高可靠性连接器
公开(公告)号：US08257092B2
公开(公告)日：2012-09-04
申请号：US12946328
申请日：2010-11-15
申请人： Sungjun Chun , Daniel M. Dreps , Dierk Kaller , Rohan U. Mandrekar , Lei Shan
发明人： Sungjun Chun , Daniel M. Dreps , Dierk Kaller , Rohan U. Mandrekar , Lei Shan
IPC分类号： H01R12/00
CPC分类号： G06F1/185 , G06F1/10
摘要： A memory module configured to connect to a slot of a data processing system. A set of tabs is connected to the module and configured to electrically connect the module to the slot and to electrically connect the module to a clock of the data processing system. The set of tabs includes a first tab, a second tab, a third tab, and a fourth tab. The first tab and the second tab are opposite the third tab and the fourth tab. The first tab comprises a positive type tab, the second tab comprises a negative type tab, the third tab comprises a positive type tab, and the fourth tab comprises a negative type tab. The first and third tabs are configured to provide a first electrical connection to the clock. The second and fourth tabs are configured to provide a second electrical connection to the clock. Together, the first, second, third, and fourth tabs comprise two dual tabs.
摘要翻译：配置为连接到数据处理系统的时隙的存储器模块。一组标签连接到模块并且被配置为将模块电连接到插槽并且将模块电连接到数据处理系统的时钟。该组标签包括第一标签，第二标签，第三标签和第四标签。第一个选项卡和第二个选项卡与第三个选项卡和第四个选项卡相对。第一标签包括一个正型标签，该第二标签包括一个负型标签，该第三标签包括一个正型标签，该第四标签包括一个负型标签。第一和第三选项卡被配置为提供到时钟的第一电连接。第二和第四选项卡被配置为提供与时钟的第二电连接。一起，第一，第二，第三和第四标签包括两个双标签。

3. 发明授权

US08927879B2 Crosstalk reduction between signal layers in a multilayered package by variable-width mesh plane structures 有权
标题翻译：通过可变宽度网格平面结构在多层封装中的信号层之间的串扰降低
公开(公告)号：US08927879B2
公开(公告)日：2015-01-06
申请号：US12952152
申请日：2010-11-22
申请人： Jinwoo Choi , Sungjun Chun , Jason L. Frankel , Paul R. Walling , Roger D. Weekly
发明人： Jinwoo Choi , Sungjun Chun , Jason L. Frankel , Paul R. Walling , Roger D. Weekly
IPC分类号： H05K1/11 , H05K3/02 , H05K1/02
CPC分类号： H05K1/0224 , G06F17/5081 , H05K1/116 , H05K2201/09681 , H05K2201/09718 , H05K2201/09727 , Y10T29/49004 , Y10T29/49155 , Y10T29/53022
摘要： A first selection of mesh line segments of a mesh layer are of a first width and a second selection of mesh line segments of the mesh layer are of a second width, wherein the second width is greater than the first width. The second selection of mesh line segments of the second width are positioned in parallel to a selection of signal lines in a signal layer that are likely to introduce crosstalk, wherein the widening of the mesh line segments shadowing the selection of signal lines increases the likelihood that the return current associated with the signal will flow in the wider mesh line segment, thereby increasing the likelihood of containing the electromagnetic fields associated with the signal such that crosstalk to other signals is reduced or contained.
摘要翻译：网格层的网格线段的第一选择是第一宽度，并且网格层的网格线段的第二选择具有第二宽度，其中第二宽度大于第一宽度。第二宽度的网格线段的第二选择与信号层中可能引入串扰的信号线的选择平行地布置，其中遮蔽信号线选择的网线段的加宽增加了与信号相关联的返回电流将在更宽的网格线段中流动，从而增加了包含与信号相关联的电磁场的可能性，使得与其他信号的串扰减少或包含。

4. 发明授权

US08407644B2 Reducing crosstalk in the design of module nets 有权
标题翻译：减少模块网设计中的串扰
公开(公告)号：US08407644B2
公开(公告)日：2013-03-26
申请号：US12537767
申请日：2009-08-07
申请人： Dulce M. Altabella Cabrera , Sungjun Chun , Anand Haridass , Tingdong Zhou
发明人： Dulce M. Altabella Cabrera , Sungjun Chun , Anand Haridass , Tingdong Zhou
IPC分类号： G06F17/50
CPC分类号： H01L23/5386 , G06F17/5077 , G06F2217/82 , H01L23/5222 , H01L23/552 , H01L25/0655 , H01L2224/16227 , H01L2224/16235 , H01L2924/15192
摘要： A method, a system and a computer program product for reducing coupling noise in low loss on-module wires used for connecting module components in electrical circuits/devices. During the design stage, an Enhanced Crosstalk Reduction (ECR) utility identifies interconnect wires as driven/aggressor traces or receiver traces. The ECR utility substantially avoids forward crosstalk in a victim trace by specially arranging driver traces adjacent to the receiver victim trace in order to provide a lower level and saturated level of backward crosstalk. In particular, the ECR utility provided a configuration of wire/trace layers based on one or more of: (a) the crosstalk impact of a trace when positioned in a particular location; (b) the crosstalk impact of the trace upon remaining components based on placement in the particular location; and (c) system component specifications. In addition, the ECR utility reduces crosstalk by providing a configuration of receiver wires and transmitter wires without the use of isolation layers.
摘要翻译：一种用于减少用于连接电路/设备中的模块部件的低损耗模块电线中的耦合噪声的方法，系统和计算机程序产品。在设计阶段，增强型串扰降低（ECR）实用程序将互连导线识别为驱动/侵入轨迹或接收器迹线。 ECR实用程序通过专门布置与接收器受害者跟踪相邻的驱动器迹线，基本上避免了受害者跟踪中的前向串扰，以便提供较低级别和饱和的后向串扰水平。特别地，ECR实用程序基于以下中的一个或多个提供了线/迹线层的配置：（a）当定位在特定位置时迹线的串扰影响; （b）基于在特定位置的放置，迹线对剩余部件的串扰影响; 和（c）系统组件规格。此外，ECR实用程序通过提供接收器线和发射器线的配置来减少串扰，而不使用隔离层。

5. 发明申请

US20120331429A1 CIRCUIT MANUFACTURING AND DESIGN TECHNIQUES FOR REFERENCE PLANE VOIDS WITH STRIP SEGMENT 失效
标题翻译：具有条带划分的参考平面电路的电路制造和设计技术
公开(公告)号：US20120331429A1
公开(公告)日：2012-12-27
申请号：US13603732
申请日：2012-09-05
申请人： Sungjun Chun , Anand Haridass , Roger D. Weekly
发明人： Sungjun Chun , Anand Haridass , Roger D. Weekly
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , H05K1/0219 , H05K1/0237 , H05K1/0253 , H05K3/4602 , H05K3/4652 , H05K2201/09536 , H05K2201/09672 , H05K2201/0969 , H05K2201/09718 , Y10T29/49117 , Y10T29/49153 , Y10T29/49155 , Y10T29/49165 , Y10T428/24322
摘要： Manufacturing circuits with reference plane voids over vias with a strip segment interconnect permits routing critical signal paths over vias, while increasing via insertion capacitance only slightly. The transmission line reference plane defines voids above (or below) signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. In order to provide increased routing density, signal paths are routed over the voids, but disruption of the signal paths by the voids is prevented by including a conductive strip through the voids that reduces the coupling to the signal-bearing PTHs and maintains the impedance of the signal path conductor.
摘要翻译：具有带状段互连的通孔上的参考平面空隙的制造电路允许在通孔上路由关键信号路径，同时仅通过插入电容略微增加。传输线参考平面定义了通过刚性衬底芯的信号承载电镀通孔（PTH）上方（或下方）的空隙，使得信号不会被阻抗失配降级，否则会由分流电容引起信号承载PTH的顶部（或底部）到传输线参考平面。为了提供增加的布线密度，信号路径被布置在空隙上，但是通过将导电条包括通过空隙来防止由空隙引起的信号路径的破坏，从而减小与信号承载PTH的耦合并维持信号路径导体。

6. 发明申请

US20120125677A1 CROSSTALK REDUCTION BETWEEN SIGNAL LAYERS IN A MULTILAYERED PACKAGE BY VARIABLE-WIDTH MESH PLANE STRUCTURES 有权
标题翻译：可变宽度MESH PLANE结构在多层包装中的信号层之间的降噪减少
公开(公告)号：US20120125677A1
公开(公告)日：2012-05-24
申请号：US12952152
申请日：2010-11-22
申请人： Jinwoo Choi , Sungjun Chun , Jason L. Frankel , Paul R. Walling , Roger D. Weekly
发明人： Jinwoo Choi , Sungjun Chun , Jason L. Frankel , Paul R. Walling , Roger D. Weekly
IPC分类号： H05K1/11 , H05K3/10
CPC分类号： H05K1/0224 , G06F17/5081 , H05K1/116 , H05K2201/09681 , H05K2201/09718 , H05K2201/09727 , Y10T29/49004 , Y10T29/49155 , Y10T29/53022
摘要： A first selection of mesh line segments of a mesh layer are of a first width and a second selection of mesh line segments of the mesh layer are of a second width, wherein the second width is greater than the first width. The second selection of mesh line segments of the second width are positioned in parallel to a selection of signal lines in a signal layer that are likely to introduce crosstalk, wherein the widening of the mesh line segments shadowing the selection of signal lines increases the likelihood that the return current associated with the signal will flow in the wider mesh line segment, thereby increasing the likelihood of containing the electromagnetic fields associated with the signal such that crosstalk to other signals is reduced or contained.
摘要翻译：网格层的网格线段的第一选择是第一宽度，并且网格层的网格线段的第二选择具有第二宽度，其中第二宽度大于第一宽度。第二宽度的网格线段的第二选择与信号层中可能引入串扰的信号线的选择平行地布置，其中遮蔽信号线选择的网线段的加宽增加了与信号相关联的返回电流将在更宽的网格线段中流动，从而增加了包含与信号相关联的电磁场的可能性，使得与其他信号的串扰减少或包含。

7. 发明授权

US07868608B2 Detecting open ground connections in surface mount connectors 失效
标题翻译：检测表面贴装连接器中的开放接地连接
公开(公告)号：US07868608B2
公开(公告)日：2011-01-11
申请号：US12420089
申请日：2009-04-08
申请人： Anand Haridass , Jesus Montanez , Xiaomin Shen , Sungjun Chun
发明人： Anand Haridass , Jesus Montanez , Xiaomin Shen , Sungjun Chun
IPC分类号： G01R31/28
CPC分类号： G01R31/026 , G01R31/043 , G01R31/2812 , H05K3/341
摘要： A device may include a current source for connecting to a printed circuit board. The device may also include a first FET switch pack and a second FET switch pack for connecting to the surface mount connector of the printed circuit board. Additionally, the device may include a FET controller connected to the first FET switch pack and the second FET switch pack. The FET controller may be utilized for connecting a first FET and a second FET to the first region of the surface mount connector. The FET controller may be configured for supplying the current to the first region of the surface mount connector to produce at least one continuous heat signature characteristic of an improperly connected ground pin. A thermal monitoring module may be used to identify the improper physical connection.
摘要翻译：设备可以包括用于连接到印刷电路板的电流源。该装置还可以包括用于连接到印刷电路板的表面安装连接器的第一FET开关组件和第二FET开关组件。另外，该装置可以包括连接到第一FET开关组和第二FET开关组的FET控制器。 FET控制器可以用于将第一FET和第二FET连接到表面安装连接器的第一区域。 FET控制器可以被配置为将电流提供给表面安装连接器的第一区域，以产生不正确连接的接地引脚的至少一个连续的热标记特性。热监测模块可用于识别不正确的物理连接。

8. 发明申请

US20100261346A1 CIRCUIT MANUFACTURING AND DESIGN TECHNIQUES FOR REFERENCE PLANE VOIDS WITH STRIP SEGMENT 失效
标题翻译：具有条带划分的参考平面电路的电路制造和设计技术
公开(公告)号：US20100261346A1
公开(公告)日：2010-10-14
申请号：US12823316
申请日：2010-06-25
申请人： Sungjun Chun , Anand Haridass , Roger D. Weekly
发明人： Sungjun Chun , Anand Haridass , Roger D. Weekly
IPC分类号： H01L21/768 , G06F17/50
CPC分类号： G06F17/5077 , H05K1/0219 , H05K1/0237 , H05K1/0253 , H05K3/4602 , H05K3/4652 , H05K2201/09536 , H05K2201/09672 , H05K2201/0969 , H05K2201/09718 , Y10T29/49117 , Y10T29/49153 , Y10T29/49155 , Y10T29/49165 , Y10T428/24322
摘要： Manufacturing circuits with reference plane voids over vias with a strip segment interconnect permits routing critical signal paths over vias, while increasing via insertion capacitance only slightly. The transmission line reference plane defines voids above (or below) signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. In order to provide increased routing density, signal paths are routed over the voids, but disruption of the signal paths by the voids is prevented by including a conductive strip through the voids that reduces the coupling to the signal-bearing PTHs and maintains the impedance of the signal path conductor.
摘要翻译：具有带状段互连的通孔上的参考平面空隙的制造电路允许在通孔上路由关键信号路径，同时仅通过插入电容略微增加。传输线参考平面定义了通过刚性衬底芯的信号承载电镀通孔（PTH）上方（或下方）的空隙，使得信号不会被阻抗失配降级，否则会由分流电容引起信号承载PTH的顶部（或底部）到传输线参考平面。为了提供增加的布线密度，信号路径被布置在空隙上，但是通过将导电条包括在通过空隙减少与信号承载PTH的耦合并且维持信号路径导体。

9. 发明申请

US20100259289A1 Detecting Open Ground Connections in Surface Mount Connectors 失效
标题翻译：检测表面贴装连接器中的开放接地连接
公开(公告)号：US20100259289A1
公开(公告)日：2010-10-14
申请号：US12420089
申请日：2009-04-08
申请人： Anand Haridass , Jesus Montanez , Xiaomin Shen , Sungjun Chun
发明人： Anand Haridass , Jesus Montanez , Xiaomin Shen , Sungjun Chun
IPC分类号： G01R31/02 , H01L25/00
CPC分类号： G01R31/026 , G01R31/043 , G01R31/2812 , H05K3/341
摘要： A device may include a current source for connecting to a printed circuit board. The device may also include a first FET switch pack and a second FET switch pack for connecting to the surface mount connector of the printed circuit board. Additionally, the device may include a FET controller connected to the first FET switch pack and the second FET switch pack. The FET controller may be utilized for connecting a first FET and a second FET to the first region of the surface mount connector. The FET controller may be configured for supplying the current to the first region of the surface mount connector to produce at least one continuous heat signature characteristic of an improperly connected ground pin. A thermal monitoring module may be used to identify the improper physical connection.
摘要翻译：设备可以包括用于连接到印刷电路板的电流源。该装置还可以包括用于连接到印刷电路板的表面安装连接器的第一FET开关组件和第二FET开关组件。另外，该装置可以包括连接到第一FET开关组和第二FET开关组的FET控制器。 FET控制器可以用于将第一FET和第二FET连接到表面安装连接器的第一区域。 FET控制器可以被配置为将电流提供给表面安装连接器的第一区域，以产生不正确连接的接地引脚的至少一个连续的热标记特性。热监测模块可用于识别不正确的物理连接。

10. 发明申请

US20070080436A1 System and Method for Noise Reduction in Multi-Layer Ceramic Packages 审中-公开
标题翻译：多层陶瓷封装降噪系统及方法
公开(公告)号：US20070080436A1
公开(公告)日：2007-04-12
申请号：US11538531
申请日：2006-10-04
申请人： Sungjun Chun , Jason Frankel , Anand Haridass , Erich Klink , Brian Singletary
发明人： Sungjun Chun , Jason Frankel , Anand Haridass , Erich Klink , Brian Singletary
IPC分类号： H01L23/495
CPC分类号： H01L23/49822 , H01L23/49838 , H01L23/552 , H01L23/66 , H01L2924/0002 , H01L2924/09701 , H01L2924/3011 , H05K1/0224 , H05K1/0253 , H05K1/0306 , H05K3/4629 , H05K2201/09681 , H01L2924/00
摘要： A system and method for reducing noise in a multi-layer ceramic package are provided. With the system and method, additional shielding wires are inserted into the reference planes wherever there are no signal vias present. These additional lines in the reference planes force stronger signal interaction with the reference (vdd/gnd) thereby reducing the interaction between the signals in the signal layers. As a result, the noise present in the signals of the signal layers is reduced.
摘要翻译：提供了一种用于降低多层陶瓷封装中的噪声的系统和方法。利用系统和方法，在没有信号通孔的地方，附加的屏蔽线插入到参考平面中。参考平面中的这些附加线强制与参考（vdd / gnd）的信号相互作用更强，从而减少信号层中信号之间的相互作用。结果，信号层的信号中存在的噪声降低。

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