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1. 发明授权

US06732349B1 Method and apparatus for improving PIP coverage in programmable logic devices 有权
标题翻译：用于改善可编程逻辑器件中的PIP覆盖的方法和装置
公开(公告)号：US06732349B1
公开(公告)日：2004-05-04
申请号：US10231900
申请日：2002-08-29
申请人： Richard Yachyang Sun , Sandor S. Kalman , Sudip K. Nag
发明人： Richard Yachyang Sun , Sandor S. Kalman , Sudip K. Nag
IPC分类号： G06F1750
CPC分类号： G01R31/318516 , G01R31/31704 , G06F17/5077
摘要： Routing algorithms can be modified to increase the number of programmable interconnect points (PIPs) used in a routing pattern. A file is set up to store information on whether a PIP has been covered. The cost of a node can be decreased by a predetermined value if two nodes are connected by an uncovered PIP. In another embodiment, a file is set up to store a count for each PIP. The count is increased each time the PIP is used in a routing. The cost of a node can be increased by multiplying a predetermined value and the count of a PIP associated with the node.
摘要翻译：可以修改路由算法以增加在路由模式中使用的可编程互连点数（PIP）。设置一个文件来存储PIP是否被覆盖的信息。如果两个节点通过未覆盖的PIP连接，节点的成本可以降低预定值。在另一个实施例中，设置文件以存储每个PIP的计数。每次在路由中使用PIP时，计数都会增加。可以通过将预定值与与节点相关联的PIP的计数相乘来增加节点的成本。

2. 发明授权

US07614025B1 Method of placement for iterative implementation flows 有权
标题翻译：迭代实现流程的放置方法
公开(公告)号：US07614025B1
公开(公告)日：2009-11-03
申请号：US11787785
申请日：2007-04-18
申请人： Raymond Kong , Sandor S. Kalman
发明人： Raymond Kong , Sandor S. Kalman
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5072 , G06F17/5054 , G06F17/5077
摘要： A method of implementing a circuit design in a target device can include identifying routing information for a circuit design that has been at least partially implemented. A plurality of empty sites of the target device within which the circuit design is to be implemented can be identified. The method also can include determining whether each of the plurality of empty sites of the target device has a routing conflict according to the routing information of the circuit design and generating a list specifying each empty site of the target device that has a routing conflict.
摘要翻译：在目标设备中实现电路设计的方法可以包括识别已经至少部分实现的电路设计的路由信息。可以识别要实现电路设计的目标设备的多个空位。该方法还可以包括根据电路设计的路由信息确定目标设备的多个空站点中的每一个是否具有路由冲突，并且生成指定具有路由冲突的目标设备的每个空站点的列表。

3. 发明授权

US08250513B1 Parallel process optimized signal routing 有权
标题翻译：并行过程优化信号路由
公开(公告)号：US08250513B1
公开(公告)日：2012-08-21
申请号：US12939765
申请日：2010-11-04
申请人： Vinay Verma , Gitu Jain , Sanjeev Kwatra , Taneem Ahmed , Sandor S. Kalman
发明人： Vinay Verma , Gitu Jain , Sanjeev Kwatra , Taneem Ahmed , Sandor S. Kalman
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5077 , G06F2217/08
摘要： In one embodiment, a method for routing of a circuit design netlist is provided. A processing cost is determined for each net in the netlist. A plurality of regions are defined for the target device such that the total processing costs of nets are balanced between the plurality of regions. Concurrent with routing one or more nets of a first one of the plurality of regions, one or more nets are routed in at least one other of the plurality of regions. Synchronization and subsequent routing are performed for unrouted nets of the netlist.
摘要翻译：在一个实施例中，提供了一种用于路由电路设计网表的方法。网表中的每个网络确定处理成本。为目标设备定义多个区域，使得网络的总处理成本在多个区域之间平衡。与路由多个区域中的第一个区域的一个或多个网络同时，在多个区域中的至少另一个区域中路由一个或多个网络。为网表的未路由网络执行同步和后续路由。

4. 发明授权

US07797665B1 Patterns for routing nets in a programmable logic device 有权
标题翻译：用于在可编程逻辑器件中路由网络的模式
公开(公告)号：US07797665B1
公开(公告)日：2010-09-14
申请号：US11999559
申请日：2007-12-06
申请人： Hui Xu , Vinay Verma , Anirban Rahut , Jason H. Anderson , Sandor S. Kalman
发明人： Hui Xu , Vinay Verma , Anirban Rahut , Jason H. Anderson , Sandor S. Kalman
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： Nets of a logic design are efficiently routed in a programmable logic device, which includes multiple types of programmable interconnects. Patterns are read from a library in a storage device. Each pattern includes an ordered set of the types of the programmable interconnects. A path is determined from the source to the destination for each net of the logic design. The path is through a sequence of the programmable interconnects having types that correspond to each type in the ordered set of a selected pattern. A description is output of the path for each of the nets.
摘要翻译：逻辑设计的网络可编程逻辑器件有效路由，可编程逻辑器件包括多种类型的可编程互连。从存储设备中的库中读取模式。每个模式包括可编程互连类型的有序集合。对于逻辑设计的每个网络，从源到目的地确定路径。该路径通过可编程互连序列，其具有对应于所选模式的有序集合中的每种类型的类型。描述是每个网络的路径的输出。

5. 发明授权

US07392498B1 Method and apparatus for implementing a pre-implemented circuit design for a programmable logic device 有权
标题翻译：用于实现可编程逻辑器件的预先实现的电路设计的方法和装置
公开(公告)号：US07392498B1
公开(公告)日：2008-06-24
申请号：US10993887
申请日：2004-11-19
申请人： Sankaranarayanan Srinivasan , W. Story Leavesley, III , George L. McHugh , Douglas P. Wieland , Sandor S. Kalman, III
发明人： Sankaranarayanan Srinivasan , W. Story Leavesley, III , George L. McHugh , Douglas P. Wieland , Sandor S. Kalman, III
IPC分类号： G06F17/50 , H03K19/00
CPC分类号： G06F17/5054 , G06F17/5068
摘要： Method and apparatus for implementing a pre-implemented circuit design for a programmable logic device is described. In one example, a definition of the pre-implemented circuit design is obtained (504). The definition includes a first physical implementation and a first logical implementation. A second logical implementation is produced (506) for an instance of the pre-implemented circuit design using the first logical implementation. A second physical implementation is produced (510, 512) for then instance of the pre-implemented circuit design using the first physical implementation.
摘要翻译：描述了用于实现可编程逻辑器件的预先实现的电路设计的方法和装置。在一个示例中，获得预先实现的电路设计的定义（504）。该定义包括第一物理实现和第一逻辑实现。对于使用第一逻辑实现的预先实现的电路设计的实例，产生第二逻辑实现（506）（506）。使用第一物理实现为第二物理实现（510,512）生成预实现电路设计的实例。

6. 发明授权

US07134112B1 Incremental routing in integrated circuit design 有权
标题翻译：集成电路设计中的增量路由
公开(公告)号：US07134112B1
公开(公告)日：2006-11-07
申请号：US10624615
申请日：2003-07-21
申请人： Jason H. Anderson , Vinay Verma , Sandor S. Kalman
发明人： Jason H. Anderson , Vinay Verma , Sandor S. Kalman
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method for completing the routing of a partially routed design is provided. The unrouted pins are routed to generate a first plurality of nets that may contain shorts or overlaps between the nets. The nets are analyzed to obtain timing information, and then divided into a set of critical and a set of non-critical nets. The non-critical nets are hidden, and the critical nets are rerouted to remove overlaps. The non-critical nets are then unhidden. The non-critical nets and rerouted critical nets are then rerouted so as to remove overlaps.
摘要翻译：提供了完成部分路由设计路由的方法。未路由的引脚被路由以产生可以在网之间包含短路或重叠的第一多个网。对网络进行分析以获得定时信息，然后分为一组关键网络和一组非关键网络。非关键网络被隐藏，关键网络被重新路由以消除重叠。然后，非关键网络将被禁止。然后重新路由非关键网络和重新路由的关键网络，以消除重叠。

7. 发明授权

US07111268B1 Post-layout optimization in integrated circuit design 有权
标题翻译：集成电路设计后布局优化
公开(公告)号：US07111268B1
公开(公告)日：2006-09-19
申请号：US10644132
申请日：2003-08-20
申请人： Jason H. Anderson , Sandor S. Kalman , Vinay Verma
发明人： Jason H. Anderson , Sandor S. Kalman , Vinay Verma
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5077
摘要： A method for post-layout timing optimization is disclosed. The method performs timing analysis on a design to obtain timing information such as critical paths and slack values. Incremental placement based on the timing information is performed. A new routed design is generated by applying incremental routing to the result of incremental placement. The routed design is stored if its performance is better than the previous routed design. The above steps are repeated until a predetermined criterion is met.
摘要翻译：公开了一种布局后定时优化的方法。该方法对设计执行定时分析以获得诸如关键路径和松弛值的定时信息。执行基于定时信息的增量放置。通过将增量路由应用于增量放置结果来生成新的路由设计。如果路由设计的性能优于先前的路由设计，则存储路由设计。重复上述步骤直到满足预定标准。

8. 发明授权

US06757879B1 Signal routing in programmable logic devices 有权
标题翻译：可编程逻辑器件中的信号路由
公开(公告)号：US06757879B1
公开(公告)日：2004-06-29
申请号：US10268878
申请日：2002-10-09
申请人： Raymond Kong , Sandor S. Kalman
发明人： Raymond Kong , Sandor S. Kalman
IPC分类号： G06F1750
CPC分类号： G06F17/5077
摘要： The present invention provides a new method to handle power and ground signals in modular design of programmable logic devices. During module implementation, the power and ground signals of each module are associated with area constraint properties. When performing routing in the module implementation phase, the power and ground signals together with regular local signals of the module are routed in accordance with their respective area constraint properties. However, the area constraint properties of the power and ground signals are removed during assembly phase while the area constraint properties of the local signals are retained.
摘要翻译：本发明提供了一种在可编程逻辑器件的模块化设计中处理电源和接地信号的新方法。在模块实现过程中，每个模块的电源和接地信号都与区域约束属性相关联。当在模块实现阶段执行路由时，电源和地面信号与模块的常规本地信号一起根据其各自的区域约束属性进行路由。然而，在组装阶段消除了功率和接地信号的面积约束特性，同时保留了局部信号的面积约束特性。

9. 发明授权

US09003413B1 Thread synchronization by transitioning threads to spin lock and sleep state 有权
标题翻译：线程同步通过转换线程来旋转锁定和睡眠状态
公开(公告)号：US09003413B1
公开(公告)日：2015-04-07
申请号：US12568558
申请日：2009-09-28
申请人： Jason H. Anderson , Taneem Ahmed , Sandor S. Kalman
发明人： Jason H. Anderson , Taneem Ahmed , Sandor S. Kalman
IPC分类号： G06F9/46 , H04L12/26
CPC分类号： H04L12/2634 , G06F9/52
摘要： A method, apparatus, and computer readable medium for synchronizing a main thread and a slave thread executing on a processor system are disclosed. For example, the method includes the following elements: transitioning the slave thread from a sleep state to a spin-lock state in response to a wake-up message from the main thread; transitioning the slave thread out of the spin-lock state to process a first work unit from the main thread; determining, at the main thread, an elapsed time period until receipt of a second work unit for the slave thread; transitioning the slave thread to the spin-lock state if the elapsed time period satisfies a threshold time period; and transitioning the slave thread to the sleep state if the elapsed time period does not satisfy the threshold time period.
摘要翻译：公开了一种用于同步处理器系统上执行的主线程和从线程的方法，装置和计算机可读介质。例如，该方法包括以下元件：响应于来自主线程的唤醒消息将从线程从睡眠状态转换到自旋锁定状态; 将从线程转换到自旋锁定状态以从主线程处理第一工作单元; 在所述主线程处确定直到接收到所述从线程的第二工作单元的经过时间段; 如果经过时间段满足阈值时间段，则将从线程转换到自旋锁定状态; 以及如果经过时间段不满足阈值时间段，则将从线程转换到休眠状态。

10. 发明授权

US08312409B1 Multi-threaded deterministic router 有权
标题翻译：多线程确定性路由器
公开(公告)号：US08312409B1
公开(公告)日：2012-11-13
申请号：US12718945
申请日：2010-03-05
申请人： Gitu Jain , Vinay Verma , Taneem Ahmed , Sandor S. Kalman , Sanjeev Kwatra , Christopher H. Kingsley , Jason H. Anderson , Satyaki Das
发明人： Gitu Jain , Vinay Verma , Taneem Ahmed , Sandor S. Kalman , Sanjeev Kwatra , Christopher H. Kingsley , Jason H. Anderson , Satyaki Das
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5054
摘要： A method is described that includes: determining that nets of the circuit design comprise overlap, where the overlap indicates that at least two of the nets of the circuit design use a same routing resource; dividing the nets with overlap among a plurality of buckets, where for each bucket, a net of the bucket does not overlap any other net in the bucket; sequentially processing each bucket by unrouting and rerouting, via at least one processor, nets in the bucket; and storing routing information specifying routes for nets of the circuit design.
摘要翻译：描述了一种方法，其包括：确定电路设计的网络包括重叠，其中重叠指示电路设计的网络中的至少两个使用相同的路由资源; 在多个桶之间用重叠划分网，其中对于每个桶，桶的网不与桶中的任何其他网重叠; 通过至少一个处理器，通过在桶中的网络进行路由和重新路由来顺序地处理每个桶; 并存储指定电路设计网络的路由的路由信息。

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